[coreboot] New patch to review for coreboot: 598a282 Append logical PME/GPIO device. Fix MPU device number.

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Mon Oct 17 21:33:40 CEST 2011


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/289

-gerrit

commit 598a28212e55d056e01381c017b74ef5846da3b6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sun Oct 16 18:12:59 2011 +0300

    Append logical PME/GPIO device. Fix MPU device number.
    
    A mainboard may require configuration of the superio pins to fully
    support some features. Things like A20# gate, leds, fans, infra-red
    and bootstrap jumpers may be configured and controlled through the
    logical PME device.
    
    Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/superio/smsc/lpc47m10x/lpc47m10x.h |    2 +-
 src/superio/smsc/lpc47m10x/superio.c   |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h
index 4c78d9e..535a414 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x.h
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h
@@ -30,7 +30,7 @@
 #define LPC47M10X2_KBC              7   /* Keyboard & Mouse */
 #define LPC47M10X2_GAME             9   /* GAME */
 #define LPC47M10X2_PME             10   /* PME  reg*/
-#define LPC47M10X2_MPU             10   /* MPE -- who knows --   reg*/ // FIXME
+#define LPC47M10X2_MPU             11   /* MPU-401 MIDI */
 
 #define LPC47M10X2_MAX_CONFIG_REGISTER	0x5F
 
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index 0be8742..3d6a8ed 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -65,6 +65,7 @@ static struct pnp_info pnp_dev_info[] = {
 	{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+	{ &ops, LPC47M10X2_PME, PNP_IO0, { 0x0f80, 0 }, },
 };
 
 /**




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