[coreboot] New patch to review for coreboot: b49e5b5 Enable/fix compilation of i8254 code in ram stage.
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Oct 13 00:48:56 CEST 2011
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/254
-gerrit
commit b49e5b5bb66a9194728471ed7c04badf5897fb46
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Tue Sep 27 16:26:05 2011 -0700
Enable/fix compilation of i8254 code in ram stage.
Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
src/include/pc80/i8254.h | 5 +++--
src/pc80/Makefile.inc | 1 +
src/pc80/i8254.c | 2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index 82f31e6..4c5e703 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -20,8 +20,6 @@
#ifndef PC80_I8254_H
#define PC80_I8254_H
-void setup_i8254(void);
-
/* Ports for the 8254 timer chip */
#define TIMER0_PORT 0x40
#define TIMER1_PORT 0x41
@@ -60,4 +58,7 @@ void setup_i8254(void);
#define PPCB_SPKR 0x02 /* Bit 1 */
#define PPCB_T2GATE 0x01 /* Bit 0 */
+#ifndef __ROMCC__
+void setup_i8254(void);
+#endif
#endif
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 4f126f6..2c8a80e 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -1,5 +1,6 @@
ramstage-y += mc146818rtc.c
ramstage-y += isa-dma.c
+ramstage-y += i8254.c
ramstage-y += i8259.c
ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
ramstage-y += keyboard.c
diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c
index ca993f4..f75216d 100644
--- a/src/pc80/i8254.c
+++ b/src/pc80/i8254.c
@@ -35,7 +35,7 @@ void setup_i8254(void)
outb(0x12, TIMER1_PORT);
}
-#if CONFIG_UDELAY_TIMER2
+#if defined(CONFIG_UDELAY_TIMER2) && CONFIG_UDELAY_TIMER2
static void load_timer2(unsigned int ticks)
{
/* Set up the timer gate, turn off the speaker */
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