[coreboot] Intel GMCH 82815

ali hagigat hagigatali at gmail.com
Wed Nov 30 11:26:51 CET 2011


Dear Peter,

Thank you so much for the reply. I have copied the content of the
three files I use for the RAM initialization, ram.S, ram.ld and
Makefile.

my GCC is:
gcc (GCC) 4.6.1 20110908 (Red Hat 4.6.1-9)
binutils:
Version     : 2.21.53.0.2                       Vendor: Fedora Project
Release     : 1.fc17                        Build Date: Mon 08 Aug
2011 20:53:40 IRDT

It is compiled for Pentium III, 815/ICH2.

Regards



ram.S
******************************************************
.code16
.section .realmode
start:
	cli
	mov    $0, %ax
	mov    %ax, %ds

#-*********************************
#/* Configure the RAM command. */

	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	
	
	movw $0x0CFC, %dx
	in %dx, %eax

	and $0x1fffffff, %eax
	or $0x05000000, %eax

	movw  $0x0CFC, %dx
	out %eax, %dx

#;--------------------------------------------------
#general initialization


#50-53**************************
	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx
	
	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax

#Bios => cas 2clk
	or $0x2fcc0140, %eax

	mov  $0x0cfc, %dx
	out %eax, %dx

#70,72-73**************************
	mov	  $0x0cf8, %dx
	mov   $0x80000070, %eax 			
	out   %eax, %dx	

	mov   $0x0cfc, %dx
	movb   $0xc0, %al
	out   %al, %dx

	mov $0x0cfe, %dx
	inw %dx, %ax

#Res mask
	and $0x7704, %ax
#Bios
	or $0x0012, %ax

	mov  $0x0cfe, %dx
	out %ax, %dx


#92-93****************************
	mov	$0x0cf8, %dx
	mov   $0x80000090, %eax 			
	out   %eax, %dx	

	mov   $0x0cfe, %dx
	movw   $0xff5c, %ax
	out   %ax, %dx


#94-95*****************************
	mov	  $0x0cf8, %dx
	mov   $0x80000094, %eax 			
	out   %eax, %dx	

	mov $0x0cfe, %dx
	inw %dx, %ax

#Res mask
	and $0xffc0, %ax
#Bios
	or $0x001c, %ax

	mov  $0x0cfe, %dx
	out %ax, %dx

#98-9B*****************************
	mov	  $0x0cf8, %dx
	mov   $0x80000098, %eax 			
	out   %eax, %dx

	movw $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x7F887F88, %eax
#Bios
	or $0x80238023, %eax

	movw  $0x0cfc, %dx
	out %eax, %dx

#9c-9f***************************
	mov	  $0x0cf8, %dx
	mov   $0x8000009c, %eax 			
	out   %eax, %dx	
		movw $0x0CFC, %dx
	in %dx, %eax

#Res mask
	and $0xFFFF7FFF, %eax
#Bios
	or $0x00008000, %eax

	movw  $0x0CFC, %dx
	out %eax, %dx

#2c-2f***************************
	mov	  $0x0cf8, %dx
	mov   $0x8000002c, %eax 			
	out   %eax, %dx	
	
	mov   $0x0cfc, %dx
	mov   $0x80271043, %eax
	out   %eax, %dx

#;--------------------------------------------------
#NOP /* 1. Apply NOP. */


	#display 1

	mov   $1, %al
	out   %al, $0x80

#%%%%%%%%%%%%%%%%%%%%

	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	

	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax

#Bios => cas 2clk
	or $0x8fcc0140, %eax

	mov  $0x0cfc, %dx
	out %eax, %dx

#%%%%%%%%%%%%%%%%%%%%%%

	mov   $0x00000000, %ebx
	mov   (%ebx), %eax
/*
	mov   $0x08000000, %ebx
	mov   (%ebx), %eax

	mov   $0x10000000, %ebx
	mov   (%ebx), %eax

	mov   $0x18000000, %ebx
	mov   (%ebx), %eax
*/

#%%%%%%%%%%%%%%%%%%%%%

	mov     $1, %di
delay11r:
	mov     $200000, %ecx
delay1r:
	dec     %ecx
	jnz     delay1r
	dec     %di
	jnz     delay11r


#;--------------------------------------------------
#precharge	/* 2. Precharge all. Wait tRP. */

	#display 2

	mov   $2, %al
	out   %al, $0x80

#%%%%%%%%%%%%%%%%%%%%%%

	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	

	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax
#Bios => cas 2clk
	or $0xafcc0140, %eax
	mov  $0x0cfc, %dx
	out %eax, %dx

#%%%%%%%%%%%%%%%%%%%%%%

	mov   $0x00000000, %ebx
	mov   %ds:(%ebx), %eax
/*
	mov   $0x08000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x10000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x18000000, %ebx
	mov   %ds:(%ebx), %eax
*/
#%%%%%%%%%%%%%%%%%%%%%%%

	mov   $10, %di
delay21r:
	mov   $1000, %ecx
delay2r:
	dec   %ecx
	jnz   delay2r
	dec   %di
	jnz   delay21r

#;--------------------------------------------------
#CBR cycle	/* 3. Perform 8 refresh cycles. Wait tRC each time. */

	#display 3

	mov   $3, %al
	out   %al, $0x80

#%%%%%%%%%%%%%%%%%%%%%%

	mov   $8, %esi
refreshcycler:
	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	


	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax

#Bios => cas 2clk
	or $0xefcc0140, %eax

	mov  $0x0cfc, %dx
	out %eax, %dx
#%%%%%%%%%%%%%%%%%%%%%%%

	mov   $0x00000000, %ebx
	mov   %ds:(%ebx), %eax
/*
	mov   $0x08000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x10000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x18000000, %ebx
	mov   %ds:(%ebx), %eax
*/
#%%%%%%%%%%%%%%%%%%%%%%%

	mov   $10, %di
delay31r:
	mov   $1000, %ecx
delay3r:
	dec   %ecx
	jnz   delay3r
	dec   %di
	jnz   delay31r

	dec   %esi
	jnz   refreshcycler

#;--------------------------------------------------
#mode register set	/* 4. Mode register set. Wait two memory cycles. */

	#display 4

	mov   $4, %al
	out   %al, $0x80

#%%%%%%%%%%%%%%%%%%%%%%%%%

	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	

	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax
#Bios => cas 2clk
	or $0xafcc0140, %eax

	mov  $0x0cfc, %dx
	out %eax, %dx

#%%%%%%%%%%%%%%%%%%%%%%%%

#1d0 => 150

	mov   $0x000001d0, %ebx
	mov   %ds:(%ebx), %eax
/*
	mov   $0x08000150, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x10000650, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x18000650, %esi
	mov   %ds:(%ebx), %eax
*/
#%%%%%%%%%%%%%%%%%%%%%%%%%%%

	mov   $10, %di
delay41r:
	mov   $1000, %ecx
delay4r:
	dec     %ecx
	jnz     delay4r
	dec     %di
	jnz     delay41r

#;--------------------------------------------------
#normal operation	/* 5. Normal operation (enables refresh at 15.6usec). */

	#display 5

	mov   $5, %al
	out   %al, $0x80

#%%%%%%%%%%%%%%%%%%%%%%%%%%

	mov	  $0x0cf8, %dx
	mov   $0x80000050, %eax 			
	out   %eax, %dx	
	
	mov $0x0cfc, %dx
	in %dx, %eax

#Res mask
	and $0x0000F823, %eax
#Bios => cas 2clk
	or $0x2fcc0140, %eax

	mov  $0x0cfc, %dx
	out %eax, %dx

#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

	mov   $0x00000000, %ebx
	mov   %ds:(%ebx), %eax
/*
	mov   $0x08000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x10000000, %ebx
	mov   %ds:(%ebx), %eax

	mov   $0x18000000, %ebx
	mov   %ds:(%ebx), %eax
*/
#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

	mov   $10, %di
delay51r:
	mov   $1000, %ecx
delay5r:
	dec     %ecx
	jnz     delay5r
	dec     %di
	jnz     delay51r

#;--------------------------------------------------
	mov   $10, %al
	out   %al, $0x80
#;--------------------------------------------------
	
	mov $0xffff, %cx
delayea1r:
	dec %cx
	jnz delayea1r

#*********************..................**************




#;enabling protected mode

	cli 	

	lgdtl  %cs:32

	mov    $0x10, %ax
	mov    %ax, %ds
	mov    %ax, %es
	mov    %ax, %fs
	mov    %ax, %gs
	mov    %ax, %ss

	mov  $0x34, %al
	out  %al, $0x80


 	mov    %cr0, %eax
	or     $1, %eax
	mov    %eax, %cr0


data32   ljmp   $0x0008, $0xfffc0000

.section .gdtsection
gdt:
.byte  0, 0, 0, 0, 0, 0, 0, 0
.byte  0xff, 0xff, 0, 0, 0, 0x9a, 0xdf, 0
.byte  0xff, 0xff, 0, 0, 0, 0x92, 0xdf, 0
.byte  0xff, 0xff, 0, 0, 0, 0x92, 0xdf, 0
.byte  32, 0, 0, 0, 0xff, 0xff

.code32
.section .protectedmode
protectedmode:

	mov    $0x42, %al
	out    %al, $0x80	

#*********************..................***********************

	
	mov $0xffff, %cx
delayea1:
	dec %cx
	jnz delayea1


#write

	mov $0x8ffff, %ebx
	mov $0x59, %al
	mov %al, (%ebx)

#read

	mov $0x8ffff, %ebx
	mov (%ebx), %al
	outb %al, $0x80

#*********************..................**************


end: jmp end

.code16
.section .reset
	jmp start


ram.ld
*****************************************************
SECTIONS
{
	/DISCARD/ : {
		*(.comment)
		*(.note.*)
		*(.note)
	}
}

SECTIONS
{
	. = 0xfffc0000;
	.text : {
		compstart = .;
		*(.protectedmode);
		. = compstart + 0x30000;
		compstart = .;
		*(.gdtsection);	
		. = compstart + 0x8200;
		compstart = .;
		*(.realmode);
		. = compstart + 0x7df0;
		compstart = .;
		*(.reset);
		. = compstart + 0x10;
		
	}

}

Makefile
****************************************************
all:
	as -march=pentiumiii -mtune=pentiumiii -o ram.o ram.S
	ld ram.o -o ram -T ram.ld
	objcopy -O binary ram ram.img

****************************************************


On Wed, Nov 30, 2011 at 12:57 PM, Peter Stuge <peter at stuge.se> wrote:
> ali hagigat wrote:
>> I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801.
>>
>> I managed to initialize DRAM controller to recognize the first 640 K
>> of the memory correctly in the real mode.
>>
>> When i switch to the protected mode, CPU writes to the first 64K only.
>> Every other read/write from the higher addresses leads to CPU restart.
>>
>> Can anybody say what is going on?
>
> Not unless you show your code.
>
> One explanation would be that you haven't done a proper switch into
> protected mode (setting up a descriptor table and initializing
> selectors) which would make the CPU triple fault and reset on
> accesses outside whatever the descriptors happen to be. If this is
> the case, I think that Intel's IA-32 architecture manuals have good
> info on what you need to do, and of course you can study both
> coreboot sources as well as some good old DOS extenders such as
> Tran's PMODE32, DOS4GW from Watcom or my personal favorite DOS32.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




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