[coreboot] New patch to review for coreboot: f803b6e Refactor src/southbridge/intel/i82801ex/smbus.h

Idwer Vollering (vidwer@gmail.com) gerrit at coreboot.org
Sat Nov 5 19:42:29 CET 2011


Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/414

-gerrit

commit f803b6e3c01a9dffd11ed72b95026e26d4822a92
Author: Idwer Vollering <vidwer at gmail.com>
Date:   Sat Nov 5 19:41:53 2011 +0100

    Refactor src/southbridge/intel/i82801ex/smbus.h
    
    Change-Id: I67a43222e9d8f2c859c7351fc4c13557462c1fec
    Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
 src/southbridge/intel/i82801ex/early_smbus.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index 618bec7..37799a8 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -6,7 +6,7 @@ static void enable_smbus(void)
 
 	print_spew("SMBus controller enabled\n");
 
-	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
+	pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | 1);
 	printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE));
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 1);




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