[coreboot] New patch to review for coreboot: c23f922 Remove XIP_ROM_BASE
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Tue Nov 1 18:41:26 CET 2011
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/366
-gerrit
commit c23f922f4a25f3f270390eb490934486d3df27f2
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Mon Oct 31 17:07:52 2011 +0100
Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/cpu/amd/agesa/family10/Kconfig | 4 ----
src/cpu/amd/agesa/family12/Kconfig | 5 -----
src/cpu/amd/agesa/family14/Kconfig | 5 -----
src/cpu/amd/car/cache_as_ram.inc | 4 ++--
src/cpu/amd/socket_AM2r2/Kconfig | 5 -----
src/cpu/amd/socket_AM3/Kconfig | 5 -----
src/cpu/amd/socket_ASB2/Kconfig | 5 -----
src/cpu/amd/socket_C32/Kconfig | 5 -----
src/cpu/amd/socket_F_1207/Kconfig | 5 -----
src/cpu/intel/car/cache_as_ram.inc | 4 ++--
src/cpu/intel/model_106cx/cache_as_ram.inc | 4 ++--
src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++--
src/cpu/intel/model_6fx/cache_as_ram.inc | 4 ++--
src/cpu/via/car/cache_as_ram.inc | 2 +-
src/cpu/x86/Kconfig | 4 ----
src/include/cpu/x86/mtrr.h | 12 +-----------
src/mainboard/supermicro/h8dmr_fam10/README | 5 -----
17 files changed, 12 insertions(+), 70 deletions(-)
diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig
index 81070e5..abaa898 100755
--- a/src/cpu/amd/agesa/family10/Kconfig
+++ b/src/cpu/amd/agesa/family10/Kconfig
@@ -40,10 +40,6 @@ config CDB
hex
default 0x18
-config XIP_ROM_BASE
- hex
- default 0xfff80000
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index 5679396..c53ee57 100755
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -57,11 +57,6 @@ config CDB
default 0x18
depends on CPU_AMD_AGESA_FAMILY12
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY12
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index 8f3e766..702270c 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -57,11 +57,6 @@ config CDB
default 0x18
depends on CPU_AMD_AGESA_FAMILY14
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY14
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index b9e02f3..955aec9 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out:
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out:
wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index c7cff14..ae4d458 100644
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_AM2R2
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_AM2R2
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
index c718ead..ed656f1 100644
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_AM3
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_AM3
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
index 964a59f..7784a8d 100644
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_ASB2
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_ASB2
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index 7ffa374..56324dc 100644
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_C32
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_C32
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
index 224059a..df98566 100644
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -29,11 +29,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_F_1207
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_F_1207
-
config XIP_ROM_SIZE
hex
default 0x80000
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 26fec6e..7742a68 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/*
* Enable write base caching so we can do execute in place (XIP)
@@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 9f7ceaf..eb3d650 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -98,7 +98,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@@ -115,7 +115,7 @@ clear_mtrrs:
xorl %edx, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 3a12cf6..18ada29 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -98,7 +98,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@@ -115,7 +115,7 @@ clear_mtrrs:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2ba1872..dfc4f3b 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -105,7 +105,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@@ -122,7 +122,7 @@ clear_mtrrs:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index ad2805e..aad2369 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -240,7 +240,7 @@ testok:
movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
- /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
+ /* Cache XIP_ROM area to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index eed7d8f..348f0ef 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -27,10 +27,6 @@ config TSC_CALIBRATE_WITH_IO
bool
default n
-config XIP_ROM_BASE
- hex
- default 0xffff0000
-
config XIP_ROM_SIZE
hex
default 0x10000
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index dc238e7..c3b3e22 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -45,23 +45,13 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
void x86_setup_fixed_mtrrs(void);
#endif
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
#if !defined(CONFIG_RAMTOP)
# error "CONFIG_RAMTOP not defined"
#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
index 040c244..485e7c8 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/README
+++ b/src/mainboard/supermicro/h8dmr_fam10/README
@@ -21,8 +21,3 @@ See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/
Ward, 2009-09-22
-mansoor at iwavesystems.com said, about the last issue:
-
- Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board.
-
-So, that's a todo.
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