[coreboot] U-Boot-x86 / coreboot Integration

Rudolf Marek r.marek at assembler.cz
Sun May 15 21:20:09 CEST 2011

Hi all,

Sorry for the delay. I'm adding some of mine ideas for the discussion. What I 
like on u-boot is interactive command line ;) this is why I started to tickle this.

The coreboot + u-boot is a win for u-boot because it can run on then on any 
coreboot supported board (including QEMU).

 From the "target" application of use I would like to see the u-boot as kind of 
alternative bootloader/monitor, where the BIOS compatibility is NOT needed. This 
limit us most likely to just linux kernel or coreboot payloads for now. We can 
have a u-boot and SeaBIOS payload in same image.

Therefore its booting job should be just loading the image (from supported 
interfaces plus CBFS ROM image) and letting this execute.

I would go with the native drivers approach, there is a plenty of them already 
for IDE, AHCI, USB if they are usable. I discuss the libpayload stuff later. The 
BIOS emulation should be restricted as much as possible because it is not the 
goal. The VGA init can be done in coreboot, as there is similar x86 emulator for 
VGA option ROM.

Do we need interrupt system up and running? I guess there are no peripherals 
using IRQ besides PPC405?

To make u-boot and coreboot work and boot on legacy IDE, following extra code is 

x86/coreboot/sdram.c -> it just reads the coreboot tables in coreboto ROM/RAM 
stage and gets memsize for u-boot. The code can be taken from libpayload (2 
files, BSD lic) or from SeaBIOS (if relicensed to GPL v2 or later). Or written 
from scratch. This file should also move ACPI RSDP table, PIR table and MP-table 
to F0000 segment.

board/coreboot.c -> the PIC should be init before CPU irq or we get div 0
x86/coreboot/pci.c -> we tell the PCI subsystem that first usable PCI address is 
right after RAM (which is not true, but the PCI is setup already from coreboot, 
should be enough to make it work).

u-boot relocation fix:

So far my patches just put into 32MB RAM, I let it relocate to the end of memory 
which I read from coreboot tables. There is a small issue with the LMA/VMA 
problem for .bios and .realmode switch section.

This is OK so far, but both sections are loaded low and its content may be 
overwritten because they tend to be used just in the booting phase.

Maybe Graeme can fix this later.

So far not much else is needed, however for the future it would be nice to for 
example write u-boot env to flash (on x86 through upcoming libflashrom). Or 
setup coreboot CMOS variables (this can be done via libpayload).

Also not sure how advanced is the PCI SATA/IDE stuff or the USB keyboard in 
u-boot. Problem is that all this is already done in libpayload and it looks like 
a waste of time to duplicate it again.

Maybe for a start I will prepare the patches to have at least the minimal 
functionality ready, so other people might jump in. Current plan is to prepare 
patches during Coreboot hackaton in prague in two weeks.

I re-read the thread regarding the libpayload/libflashrom but could not find the 
decision how to solve this.


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