[coreboot] New patch to review: 2bea70b Move existing AMD Ffamily14 code to f14 folder

Frank Vibrans III (efdesign98@gmail.com) gerrit at coreboot.org
Tue Jun 21 03:15:55 CEST 2011


Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/52

-gerrit

commit 2bea70b63e83700860e4f65407495605cab01b72
Author: efdesign98 <efdesign98 at gmail.com>
Date:   Mon Jun 20 18:12:43 2011 -0700

    Move existing AMD Ffamily14 code to f14 folder
    
    This change moves the AMD Family14 cpu Agesa code to
    the vendorcode/amd/agesa/f14 folder to complete the
    transition to the family oriented folder structure.
    
    Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
    Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
    Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
 src/cpu/amd/Makefile.inc                           |    2 +-
 src/cpu/amd/agesa/family14/Makefile.inc            |    2 +-
 src/mainboard/advansus/a785e-i/Makefile.inc        |   14 +-
 src/mainboard/amd/inagua/Makefile.inc              |    2 +-
 src/mainboard/amd/persimmon/Makefile.inc           |    2 +-
 src/mainboard/asrock/e350m1/Makefile.inc           |    2 +-
 src/northbridge/amd/Makefile.inc                   |    2 +-
 src/vendorcode/amd/agesa/AGESA.h                   | 3022 -----
 src/vendorcode/amd/agesa/AMD.h                     |  482 -
 src/vendorcode/amd/agesa/Dispatcher.h              |   54 -
 src/vendorcode/amd/agesa/Include/AdvancedApi.h     |  168 -
 src/vendorcode/amd/agesa/Include/BrazosInstall.h   |  102 -
 src/vendorcode/amd/agesa/Include/CommonReturns.h   |  125 -
 src/vendorcode/amd/agesa/Include/DanNiInstall.h    |  117 -
 src/vendorcode/amd/agesa/Include/DanubeInstall.h   |  102 -
 src/vendorcode/amd/agesa/Include/DevTestInstall.h  |  111 -
 src/vendorcode/amd/agesa/Include/DragonInstall.h   |  102 -
 src/vendorcode/amd/agesa/Include/Filecode.h        |  849 --
 src/vendorcode/amd/agesa/Include/GeneralServices.h |  203 -
 src/vendorcode/amd/agesa/Include/GnbInterface.h    |   96 -
 .../amd/agesa/Include/GnbInterfaceStub.h           |  232 -
 src/vendorcode/amd/agesa/Include/Ids.h             |  927 --
 src/vendorcode/amd/agesa/Include/IdsHt.h           |  126 -
 src/vendorcode/amd/agesa/Include/LynxInstall.h     |  102 -
 .../amd/agesa/Include/MaranelloInstall.h           |  118 -
 src/vendorcode/amd/agesa/Include/NileInstall.h     |  102 -
 src/vendorcode/amd/agesa/Include/OptionC6Install.h |  151 -
 .../amd/agesa/Include/OptionCpbInstall.h           |  122 -
 .../Include/OptionCpuCacheFlushOnHaltInstall.h     |  120 -
 .../agesa/Include/OptionCpuCoreLevelingInstall.h   |  115 -
 .../amd/agesa/Include/OptionCpuFamiliesInstall.h   |  406 -
 .../amd/agesa/Include/OptionCpuFeaturesInstall.h   |   78 -
 src/vendorcode/amd/agesa/Include/OptionDmi.h       |   92 -
 .../amd/agesa/Include/OptionDmiInstall.h           |  194 -
 .../amd/agesa/Include/OptionFamily10hInstall.h     | 1996 ----
 .../amd/agesa/Include/OptionFamily12hEarlySample.h |  138 -
 .../amd/agesa/Include/OptionFamily12hInstall.h     |  665 --
 .../amd/agesa/Include/OptionFamily14hEarlySample.h |  170 -
 .../amd/agesa/Include/OptionFamily14hInstall.h     |  661 --
 .../amd/agesa/Include/OptionFamily15hInstall.h     |  717 --
 .../amd/agesa/Include/OptionGfxRecovery.h          |   84 -
 .../amd/agesa/Include/OptionGfxRecoveryInstall.h   |   56 -
 src/vendorcode/amd/agesa/Include/OptionGnb.h       |   92 -
 .../amd/agesa/Include/OptionGnbInstall.h           |  449 -
 .../amd/agesa/Include/OptionHtAssistInstall.h      |  109 -
 src/vendorcode/amd/agesa/Include/OptionHtInstall.h |  301 -
 .../amd/agesa/Include/OptionHwC1eInstall.h         |   83 -
 .../amd/agesa/Include/OptionIdsInstall.h           |  417 -
 .../amd/agesa/Include/OptionIoCstateInstall.h      |  135 -
 .../amd/agesa/Include/OptionLowPwrPstateInstall.h  |   89 -
 src/vendorcode/amd/agesa/Include/OptionMemory.h    |  342 -
 .../amd/agesa/Include/OptionMemoryInstall.h        | 4051 -------
 .../amd/agesa/Include/OptionMemoryRecovery.h       |   65 -
 .../agesa/Include/OptionMemoryRecoveryInstall.h    |  602 -
 .../amd/agesa/Include/OptionMsgBasedC1eInstall.h   |  119 -
 .../amd/agesa/Include/OptionMultiSocket.h          |  169 -
 .../amd/agesa/Include/OptionMultiSocketInstall.h   |   92 -
 .../agesa/Include/OptionPreserveMailboxInstall.h   |  107 -
 src/vendorcode/amd/agesa/Include/OptionPstate.h    |  118 -
 .../amd/agesa/Include/OptionPstateInstall.h        |  243 -
 .../amd/agesa/Include/OptionS3ScriptInstall.h      |   94 -
 src/vendorcode/amd/agesa/Include/OptionSlit.h      |   99 -
 .../amd/agesa/Include/OptionSlitInstall.h          |   82 -
 src/vendorcode/amd/agesa/Include/OptionSrat.h      |   85 -
 .../amd/agesa/Include/OptionSratInstall.h          |   76 -
 .../amd/agesa/Include/OptionSwC1eInstall.h         |   83 -
 src/vendorcode/amd/agesa/Include/OptionWhea.h      |   86 -
 .../amd/agesa/Include/OptionWheaInstall.h          |   77 -
 src/vendorcode/amd/agesa/Include/Options.h         |   94 -
 src/vendorcode/amd/agesa/Include/OptionsHt.h       |  103 -
 src/vendorcode/amd/agesa/Include/OptionsPage.h     |  375 -
 src/vendorcode/amd/agesa/Include/PlatformInstall.h | 2599 ----
 .../agesa/Include/PlatformMemoryConfiguration.h    |  314 -
 src/vendorcode/amd/agesa/Include/SabineInstall.h   |  117 -
 .../amd/agesa/Include/SanMarinoInstall.h           |  118 -
 src/vendorcode/amd/agesa/Include/ScorpiusInstall.h |  117 -
 src/vendorcode/amd/agesa/Include/TigrisInstall.h   |  102 -
 src/vendorcode/amd/agesa/Include/Topology.h        |  165 -
 src/vendorcode/amd/agesa/Include/gcc-intrin.h      |  630 -
 .../agesa/Legacy/PlatformMemoryConfiguration.inc   |  402 -
 src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c  |  161 -
 src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat    |  286 -
 .../amd/agesa/Legacy/Proc/agesaCallouts.c          |  397 -
 src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm  | 2674 -----
 src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c |  394 -
 src/vendorcode/amd/agesa/Legacy/agesa.inc          | 2547 ----
 src/vendorcode/amd/agesa/Legacy/amd.inc            |  461 -
 src/vendorcode/amd/agesa/Legacy/bridge32.inc       |  577 -
 src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm     |  151 -
 src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm     |  110 -
 src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm     |   84 -
 src/vendorcode/amd/agesa/Lib/amdlib.c              | 1340 ---
 src/vendorcode/amd/agesa/Lib/amdlib.h              |  421 -
 src/vendorcode/amd/agesa/Lib/helper.c              |   68 -
 src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm      |  591 -
 src/vendorcode/amd/agesa/MainPage.h                |  121 -
 src/vendorcode/amd/agesa/Makefile.inc              |   62 -
 src/vendorcode/amd/agesa/Porting.h                 |  296 -
 .../agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c |  119 -
 .../amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c   |  294 -
 .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c   | 1527 ---
 .../agesa/Proc/CPU/Family/0x10/F10PackageType.h    |   85 -
 .../Proc/CPU/Family/0x10/F10PmAsymBoostInit.c      |  182 -
 .../Proc/CPU/Family/0x10/F10PmAsymBoostInit.h      |   79 -
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c    |  246 -
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h    |   79 -
 .../agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c |  300 -
 .../agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h |   78 -
 .../agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c |  188 -
 .../agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h |   78 -
 .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c  | 1942 ---
 .../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c    |  151 -
 .../Family/0x10/RevC/BL/F10BlEquivalenceTable.c    |  107 -
 .../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c     |  123 -
 .../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c |  107 -
 .../0x10/RevC/BL/F10BlMicrocodePatchTables.c       |  107 -
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c  |  107 -
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c  |  197 -
 .../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c    |  144 -
 .../Family/0x10/RevC/DA/F10DaEquivalenceTable.c    |  108 -
 .../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c     |  284 -
 .../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c |  108 -
 .../0x10/RevC/DA/F10DaMicrocodePatchTables.c       |  107 -
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c  |  107 -
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c  |  193 -
 .../Family/0x10/RevC/F10MicrocodePatch01000085.c   | 1038 --
 .../Family/0x10/RevC/F10MicrocodePatch010000c6.c   | 1038 --
 .../Family/0x10/RevC/F10MicrocodePatch010000c7.c   | 1038 --
 .../Family/0x10/RevC/F10MicrocodePatch010000c8.c   | 1038 --
 .../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c |  440 -
 .../agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c |  189 -
 .../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c   |  134 -
 .../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c   |  266 -
 .../agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c |  182 -
 .../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c   |  436 -
 .../Family/0x10/RevC/RB/F10RbEquivalenceTable.c    |  111 -
 .../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c     |  121 -
 .../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c |  115 -
 .../0x10/RevC/RB/F10RbMicrocodePatchTables.c       |  107 -
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c  |  121 -
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c  |  235 -
 .../Family/0x10/RevD/F10MicrocodePatch010000c4.c   | 1040 --
 .../Family/0x10/RevD/F10MicrocodePatch010000c5.c   | 1040 --
 .../agesa/Proc/CPU/Family/0x10/RevD/F10RevD32.asm  |  113 -
 .../agesa/Proc/CPU/Family/0x10/RevD/F10RevD64.asm  |  127 -
 .../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c    |  466 -
 .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c |  277 -
 .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c   |  370 -
 .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c    |  107 -
 .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c     | 1295 --
 .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c  |  137 -
 .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c |  109 -
 .../0x10/RevD/HY/F10HyMicrocodePatchTables.c       |  107 -
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c  |  138 -
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c  |  350 -
 .../Family/0x10/RevE/F10MicrocodePatch010000bf.c   | 1040 --
 .../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c |  374 -
 .../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c   |  135 -
 .../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c   |  227 -
 .../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c   |  370 -
 .../Family/0x10/RevE/PH/F10PhEquivalenceTable.c    |  106 -
 .../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c     |  118 -
 .../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c |   97 -
 .../0x10/RevE/PH/F10PhMicrocodePatchTables.c       |  106 -
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c   |  330 -
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h   |  100 -
 .../amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandId.c |  145 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c  |  333 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c |  138 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c  |  134 -
 .../Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c     |  175 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c  |  128 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c |  129 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c |  144 -
 .../Proc/CPU/Family/0x10/cpuF10CacheDefaults.c     |  127 -
 .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c  |  144 -
 .../amd/agesa/Proc/CPU/Family/0x10/cpuF10Cpb.c     |  179 -
 .../amd/agesa/Proc/CPU/Family/0x10/cpuF10Dmi.c     |  478 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.c   |  424 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.h   |   80 -
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c   |  394 -
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h   |  196 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c |  752 --
 .../agesa/Proc/CPU/Family/0x10/cpuF10MsrTables.c   |  275 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10PciTables.c   |  773 --
 .../agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.c  |  421 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.h  |   84 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h   |  548 -
 .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c  |  176 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.c  |  484 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.h  |   78 -
 .../amd/agesa/Proc/CPU/Family/0x10/cpuF10Pstate.c  |  863 --
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c   |  124 -
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h   |   80 -
 .../agesa/Proc/CPU/Family/0x10/cpuF10Utilities.c   | 1119 --
 .../agesa/Proc/CPU/Family/0x10/cpuF10Utilities.h   |  165 -
 .../CPU/Family/0x10/cpuF10WheaInitDataTables.c     |  121 -
 .../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c  |  106 -
 .../amd/agesa/Proc/CPU/Family/0x14/F14C6State.c    |  238 -
 .../amd/agesa/Proc/CPU/Family/0x14/F14IoCstate.c   |  285 -
 .../CPU/Family/0x14/F14MicrocodePatch0500000B.c    | 1645 ---
 .../CPU/Family/0x14/F14MicrocodePatch0500001A.c    | 1645 ---
 .../CPU/Family/0x14/F14MicrocodePatch05000025.c    | 1645 ---
 .../agesa/Proc/CPU/Family/0x14/F14PackageType.h    |   77 -
 .../CPU/Family/0x14/ON/F14OnEquivalenceTable.c     |  125 -
 .../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c  |  309 -
 .../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h  |   69 -
 .../Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c |  102 -
 .../CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c |  102 -
 .../Proc/CPU/Family/0x14/cpuCommonF14Utilities.c   |  518 -
 .../Proc/CPU/Family/0x14/cpuCommonF14Utilities.h   |  104 -
 .../amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandId.c |  139 -
 .../agesa/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c  |  145 -
 .../Proc/CPU/Family/0x14/cpuF14CacheDefaults.c     |  123 -
 .../amd/agesa/Proc/CPU/Family/0x14/cpuF14Dmi.c     |  272 -
 .../agesa/Proc/CPU/Family/0x14/cpuF14MsrTables.c   |  198 -
 .../agesa/Proc/CPU/Family/0x14/cpuF14PciTables.c   |  716 --
 .../Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c  |  102 -
 .../agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.c  |  358 -
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 .../CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c  |  133 -
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 .../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h   |   80 -
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 src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuDmi.c |  681 --
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 src/vendorcode/amd/agesa/Proc/CPU/S3.c             | 1219 --
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 src/vendorcode/amd/agesa/Proc/CPU/Table.c          | 1664 ---
 src/vendorcode/amd/agesa/Proc/CPU/Table.h          | 1238 --
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 src/vendorcode/amd/agesa/Proc/CPU/cahalt64.asm     |  157 -
 .../amd/agesa/Proc/CPU/cpuApicUtilities.c          | 1466 ---
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 src/vendorcode/amd/agesa/Proc/CPU/cpuBist.c        |  173 -
 src/vendorcode/amd/agesa/Proc/CPU/cpuBrandId.c     |  309 -
 src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.c   |  404 -
 src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.h   |  250 -
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 src/vendorcode/amd/agesa/Proc/CPU/cpuEventLog.c    |  399 -
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 .../amd/agesa/Proc/CPU/cpuGeneralServices.c        | 1277 --
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 src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.h    |  821 --
 .../amd/agesa/Proc/CPU/cpuMicrocodePatch.c         |  441 -
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 src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmt.c   |  253 -
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 .../amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c        |  298 -
 .../amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c     |  127 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrp.c           |  261 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c      |  183 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c      |  111 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c      |  111 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c        |  178 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c     |  183 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c  |   93 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c     |  199 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c        |  218 -
 .../amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c        |  188 -
 .../amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c   |  189 -
 .../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c    |  244 -
 .../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c    |  360 -
 .../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c    |  326 -
 .../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h    |  132 -
 .../agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c    |  347 -
 .../amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c     |  287 -
 .../amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c     |  115 -
 .../amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c     |  437 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c |  129 -
 .../amd/agesa/Proc/Recovery/Mem/mrinit.c           |  126 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c   |  288 -
 .../amd/agesa/Proc/Recovery/Mem/mrport.h           |   82 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h  |  121 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm |  187 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h   |  140 -
 src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c  |  267 -
 .../amd/agesa/Proc/Recovery/recoveryPage.h         |   59 -
 src/vendorcode/amd/agesa/cpcar.inc                 | 1124 --
 src/vendorcode/amd/agesa/cpcarmac.inc              |  447 -
 src/vendorcode/amd/agesa/errno.h                   |   38 -
 src/vendorcode/amd/agesa/f14/AGESA.h               | 3022 +++++
 src/vendorcode/amd/agesa/f14/AMD.h                 |  482 +
 src/vendorcode/amd/agesa/f14/Dispatcher.h          |   54 +
 src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h |  168 +
 .../amd/agesa/f14/Include/BrazosInstall.h          |  102 +
 .../amd/agesa/f14/Include/CommonReturns.h          |  125 +
 .../amd/agesa/f14/Include/DanNiInstall.h           |  117 +
 .../amd/agesa/f14/Include/DanubeInstall.h          |  102 +
 .../amd/agesa/f14/Include/DevTestInstall.h         |  111 +
 .../amd/agesa/f14/Include/DragonInstall.h          |  102 +
 src/vendorcode/amd/agesa/f14/Include/Filecode.h    |  849 ++
 .../amd/agesa/f14/Include/GeneralServices.h        |  203 +
 .../amd/agesa/f14/Include/GnbInterface.h           |   96 +
 .../amd/agesa/f14/Include/GnbInterfaceStub.h       |  232 +
 src/vendorcode/amd/agesa/f14/Include/Ids.h         |  927 ++
 src/vendorcode/amd/agesa/f14/Include/IdsHt.h       |  126 +
 src/vendorcode/amd/agesa/f14/Include/LynxInstall.h |  102 +
 .../amd/agesa/f14/Include/MaranelloInstall.h       |  118 +
 src/vendorcode/amd/agesa/f14/Include/NileInstall.h |  102 +
 .../amd/agesa/f14/Include/OptionC6Install.h        |  151 +
 .../amd/agesa/f14/Include/OptionCpbInstall.h       |  122 +
 .../f14/Include/OptionCpuCacheFlushOnHaltInstall.h |  120 +
 .../f14/Include/OptionCpuCoreLevelingInstall.h     |  115 +
 .../agesa/f14/Include/OptionCpuFamiliesInstall.h   |  406 +
 .../agesa/f14/Include/OptionCpuFeaturesInstall.h   |   78 +
 src/vendorcode/amd/agesa/f14/Include/OptionDmi.h   |   92 +
 .../amd/agesa/f14/Include/OptionDmiInstall.h       |  194 +
 .../amd/agesa/f14/Include/OptionFamily10hInstall.h | 1996 ++++
 .../agesa/f14/Include/OptionFamily12hEarlySample.h |  138 +
 .../amd/agesa/f14/Include/OptionFamily12hInstall.h |  665 ++
 .../agesa/f14/Include/OptionFamily14hEarlySample.h |  170 +
 .../amd/agesa/f14/Include/OptionFamily14hInstall.h |  661 ++
 .../amd/agesa/f14/Include/OptionFamily15hInstall.h |  717 ++
 .../amd/agesa/f14/Include/OptionGfxRecovery.h      |   84 +
 .../agesa/f14/Include/OptionGfxRecoveryInstall.h   |   56 +
 src/vendorcode/amd/agesa/f14/Include/OptionGnb.h   |   92 +
 .../amd/agesa/f14/Include/OptionGnbInstall.h       |  449 +
 .../amd/agesa/f14/Include/OptionHtAssistInstall.h  |  109 +
 .../amd/agesa/f14/Include/OptionHtInstall.h        |  301 +
 .../amd/agesa/f14/Include/OptionHwC1eInstall.h     |   83 +
 .../amd/agesa/f14/Include/OptionIdsInstall.h       |  417 +
 .../amd/agesa/f14/Include/OptionIoCstateInstall.h  |  135 +
 .../agesa/f14/Include/OptionLowPwrPstateInstall.h  |   89 +
 .../amd/agesa/f14/Include/OptionMemory.h           |  342 +
 .../amd/agesa/f14/Include/OptionMemoryInstall.h    | 4051 +++++++
 .../amd/agesa/f14/Include/OptionMemoryRecovery.h   |   65 +
 .../f14/Include/OptionMemoryRecoveryInstall.h      |  602 +
 .../agesa/f14/Include/OptionMsgBasedC1eInstall.h   |  119 +
 .../amd/agesa/f14/Include/OptionMultiSocket.h      |  169 +
 .../agesa/f14/Include/OptionMultiSocketInstall.h   |   92 +
 .../f14/Include/OptionPreserveMailboxInstall.h     |  107 +
 .../amd/agesa/f14/Include/OptionPstate.h           |  118 +
 .../amd/agesa/f14/Include/OptionPstateInstall.h    |  243 +
 .../amd/agesa/f14/Include/OptionS3ScriptInstall.h  |   94 +
 src/vendorcode/amd/agesa/f14/Include/OptionSlit.h  |   99 +
 .../amd/agesa/f14/Include/OptionSlitInstall.h      |   82 +
 src/vendorcode/amd/agesa/f14/Include/OptionSrat.h  |   85 +
 .../amd/agesa/f14/Include/OptionSratInstall.h      |   76 +
 .../amd/agesa/f14/Include/OptionSwC1eInstall.h     |   83 +
 src/vendorcode/amd/agesa/f14/Include/OptionWhea.h  |   86 +
 .../amd/agesa/f14/Include/OptionWheaInstall.h      |   77 +
 src/vendorcode/amd/agesa/f14/Include/Options.h     |   94 +
 src/vendorcode/amd/agesa/f14/Include/OptionsHt.h   |  103 +
 src/vendorcode/amd/agesa/f14/Include/OptionsPage.h |  375 +
 .../amd/agesa/f14/Include/PlatformInstall.h        | 2599 ++++
 .../f14/Include/PlatformMemoryConfiguration.h      |  314 +
 .../amd/agesa/f14/Include/SabineInstall.h          |  117 +
 .../amd/agesa/f14/Include/SanMarinoInstall.h       |  118 +
 .../amd/agesa/f14/Include/ScorpiusInstall.h        |  117 +
 .../amd/agesa/f14/Include/TigrisInstall.h          |  102 +
 src/vendorcode/amd/agesa/f14/Include/Topology.h    |  165 +
 src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h  |  630 +
 .../f14/Legacy/PlatformMemoryConfiguration.inc     |  402 +
 .../amd/agesa/f14/Legacy/Proc/Dispatcher.c         |  161 +
 .../amd/agesa/f14/Legacy/Proc/Legacy.bat           |  286 +
 .../amd/agesa/f14/Legacy/Proc/agesaCallouts.c      |  397 +
 .../amd/agesa/f14/Legacy/Proc/arch2008.asm         | 2674 +++++
 .../amd/agesa/f14/Legacy/Proc/hobTransfer.c        |  394 +
 src/vendorcode/amd/agesa/f14/Legacy/agesa.inc      | 2547 ++++
 src/vendorcode/amd/agesa/f14/Legacy/amd.inc        |  461 +
 src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc   |  577 +
 src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm |  151 +
 src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm |  110 +
 src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm |   84 +
 src/vendorcode/amd/agesa/f14/Lib/amdlib.c          | 1340 +++
 src/vendorcode/amd/agesa/f14/Lib/amdlib.h          |  421 +
 src/vendorcode/amd/agesa/f14/Lib/helper.c          |   68 +
 src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm  |  591 +
 src/vendorcode/amd/agesa/f14/MainPage.h            |  121 +
 src/vendorcode/amd/agesa/f14/Makefile.inc          |   62 +
 src/vendorcode/amd/agesa/f14/Porting.h             |  296 +
 .../f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c   |  119 +
 .../agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c   |  294 +
 .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c   | 1527 +++
 .../f14/Proc/CPU/Family/0x10/F10PackageType.h      |   85 +
 .../f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c  |  182 +
 .../f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h  |   79 +
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c    |  246 +
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h    |   79 +
 .../f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c   |  300 +
 .../f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h   |   78 +
 .../f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c   |  188 +
 .../f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.h   |   78 +
 .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c  | 1942 +++
 .../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c    |  151 +
 .../Family/0x10/RevC/BL/F10BlEquivalenceTable.c    |  107 +
 .../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c     |  123 +
 .../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c |  107 +
 .../0x10/RevC/BL/F10BlMicrocodePatchTables.c       |  107 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c  |  107 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c  |  197 +
 .../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c    |  144 +
 .../Family/0x10/RevC/DA/F10DaEquivalenceTable.c    |  108 +
 .../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c     |  284 +
 .../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c |  108 +
 .../0x10/RevC/DA/F10DaMicrocodePatchTables.c       |  107 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c  |  107 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c  |  193 +
 .../Family/0x10/RevC/F10MicrocodePatch01000085.c   | 1038 ++
 .../Family/0x10/RevC/F10MicrocodePatch010000c6.c   | 1038 ++
 .../Family/0x10/RevC/F10MicrocodePatch010000c7.c   | 1038 ++
 .../Family/0x10/RevC/F10MicrocodePatch010000c8.c   | 1038 ++
 .../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c |  440 +
 .../f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c   |  189 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c   |  134 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c   |  266 +
 .../f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c   |  182 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c   |  436 +
 .../Family/0x10/RevC/RB/F10RbEquivalenceTable.c    |  111 +
 .../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c     |  121 +
 .../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c |  115 +
 .../0x10/RevC/RB/F10RbMicrocodePatchTables.c       |  107 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c  |  121 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c  |  235 +
 .../Family/0x10/RevD/F10MicrocodePatch010000c4.c   | 1040 ++
 .../Family/0x10/RevD/F10MicrocodePatch010000c5.c   | 1040 ++
 .../f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm    |  113 +
 .../f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm    |  127 +
 .../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c    |  466 +
 .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c |  277 +
 .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c   |  370 +
 .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c    |  107 +
 .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c     | 1295 ++
 .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c  |  137 +
 .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c |  109 +
 .../0x10/RevD/HY/F10HyMicrocodePatchTables.c       |  107 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c  |  138 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c  |  350 +
 .../Family/0x10/RevE/F10MicrocodePatch010000bf.c   | 1040 ++
 .../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c |  374 +
 .../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c   |  135 +
 .../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c   |  227 +
 .../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c   |  370 +
 .../Family/0x10/RevE/PH/F10PhEquivalenceTable.c    |  106 +
 .../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c     |  118 +
 .../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c |   97 +
 .../0x10/RevE/PH/F10PhMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c   |  330 +
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h   |  100 +
 .../agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c |  145 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c    |  333 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c   |  138 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c    |  134 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c |  175 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c    |  128 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c   |  129 +
 .../f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c   |  144 +
 .../f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c |  127 +
 .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c  |  144 +
 .../amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c |  179 +
 .../amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c |  478 +
 .../f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c     |  424 +
 .../f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.h     |   80 +
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c   |  394 +
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h   |  196 +
 .../f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c   |  752 ++
 .../f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c     |  275 +
 .../f14/Proc/CPU/Family/0x10/cpuF10PciTables.c     |  773 ++
 .../f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c    |  421 +
 .../f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.h    |   84 +
 .../f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h     |  548 +
 .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c  |  176 +
 .../f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c    |  484 +
 .../f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.h    |   78 +
 .../agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c  |  863 ++
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c   |  124 +
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h   |   80 +
 .../f14/Proc/CPU/Family/0x10/cpuF10Utilities.c     | 1119 ++
 .../f14/Proc/CPU/Family/0x10/cpuF10Utilities.h     |  165 +
 .../CPU/Family/0x10/cpuF10WheaInitDataTables.c     |  121 +
 .../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c  |  106 +
 .../agesa/f14/Proc/CPU/Family/0x14/F14C6State.c    |  238 +
 .../agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c   |  285 +
 .../CPU/Family/0x14/F14MicrocodePatch0500000B.c    | 1645 +++
 .../CPU/Family/0x14/F14MicrocodePatch0500001A.c    | 1645 +++
 .../CPU/Family/0x14/F14MicrocodePatch05000025.c    | 1645 +++
 .../f14/Proc/CPU/Family/0x14/F14PackageType.h      |   77 +
 .../CPU/Family/0x14/ON/F14OnEquivalenceTable.c     |  125 +
 .../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c  |  309 +
 .../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h  |   69 +
 .../Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c |  102 +
 .../CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c |  102 +
 .../Proc/CPU/Family/0x14/cpuCommonF14Utilities.c   |  518 +
 .../Proc/CPU/Family/0x14/cpuCommonF14Utilities.h   |  104 +
 .../agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c |  139 +
 .../f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c    |  145 +
 .../f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c |  123 +
 .../amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c |  272 +
 .../f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c     |  198 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PciTables.c     |  716 ++
 .../Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c  |  102 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c    |  358 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.h    |   83 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h     |  477 +
 .../CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c  |  133 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c    |  272 +
 .../f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.h    |   78 +
 .../agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c  |  364 +
 .../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c   |  112 +
 .../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h   |   80 +
 .../f14/Proc/CPU/Family/0x14/cpuF14Utilities.c     |  539 +
 .../f14/Proc/CPU/Family/0x14/cpuF14Utilities.h     |  132 +
 .../CPU/Family/0x14/cpuF14WheaInitDataTables.c     |  117 +
 .../agesa/f14/Proc/CPU/Family/cpuFamRegisters.h    |  213 +
 .../agesa/f14/Proc/CPU/Feature/PreserveMailbox.c   |  218 +
 .../agesa/f14/Proc/CPU/Feature/PreserveMailbox.h   |   89 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c    |  262 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h    |  156 +
 .../f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c     |  193 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c  |  744 ++
 .../amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h  |  134 +
 .../agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c   |  353 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c        |  177 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h        |  135 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c        |  681 ++
 .../f14/Proc/CPU/Feature/cpuFeatureLeveling.c      |  266 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c   |  198 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h   |  267 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c   |  357 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h   |  301 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c      |  175 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h      |  127 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c   |  209 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h   |  285 +
 .../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c   |  206 +
 .../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h   |  133 +
 .../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c    |  213 +
 .../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h    |  129 +
 .../agesa/f14/Proc/CPU/Feature/cpuPstateGather.c   |  397 +
 .../agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c | 1073 ++
 .../agesa/f14/Proc/CPU/Feature/cpuPstateTables.c   |  830 ++
 .../agesa/f14/Proc/CPU/Feature/cpuPstateTables.h   |  329 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c       |  357 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c       |  565 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c      |  176 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h      |  121 +
 .../amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c       |  271 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c         | 1219 ++
 src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h         |  395 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c      | 1664 +++
 src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h      | 1238 ++
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm   |  345 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c     |  317 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm |  157 +
 .../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c      | 1466 +++
 .../amd/agesa/f14/Proc/CPU/cpuApicUtilities.h      |  262 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c    |  173 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c |  309 +
 .../amd/agesa/f14/Proc/CPU/cpuEarlyInit.c          |  404 +
 .../amd/agesa/f14/Proc/CPU/cpuEarlyInit.h          |  250 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEnvInit.h |   75 +
 .../amd/agesa/f14/Proc/CPU/cpuEventLog.c           |  399 +
 .../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c  |  483 +
 .../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h  |  957 ++
 .../amd/agesa/f14/Proc/CPU/cpuGeneralServices.c    | 1277 ++
 .../amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c     |  119 +
 .../amd/agesa/f14/Proc/CPU/cpuLateInit.c           |  286 +
 .../amd/agesa/f14/Proc/CPU/cpuLateInit.h           |  821 ++
 .../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c     |  441 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPage.h    |   62 +
 .../amd/agesa/f14/Proc/CPU/cpuPostInit.c           |  481 +
 .../amd/agesa/f14/Proc/CPU/cpuPostInit.h           |  228 +
 .../amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c          |  253 +
 .../agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c   |  432 +
 .../agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.h   |  102 +
 .../agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c  |  246 +
 .../agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.h  |  102 +
 .../agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h  |   94 +
 .../amd/agesa/f14/Proc/CPU/cpuRegisters.h          |  407 +
 .../amd/agesa/f14/Proc/CPU/cpuServices.h           |  347 +
 .../amd/agesa/f14/Proc/CPU/cpuWarmReset.c          |  237 +
 .../amd/agesa/f14/Proc/CPU/heapManager.c           |  853 ++
 .../amd/agesa/f14/Proc/CPU/heapManager.h           |  230 +
 .../amd/agesa/f14/Proc/Common/AmdInitEarly.c       |  281 +
 .../amd/agesa/f14/Proc/Common/AmdInitEnv.c         |  176 +
 .../amd/agesa/f14/Proc/Common/AmdInitLate.c        |  292 +
 .../amd/agesa/f14/Proc/Common/AmdInitMid.c         |  162 +
 .../amd/agesa/f14/Proc/Common/AmdInitPost.c        |  339 +
 .../amd/agesa/f14/Proc/Common/AmdInitRecovery.c    |  171 +
 .../amd/agesa/f14/Proc/Common/AmdInitReset.c       |  245 +
 .../amd/agesa/f14/Proc/Common/AmdInitResume.c      |  233 +
 .../amd/agesa/f14/Proc/Common/AmdLateRunApTask.c   |  160 +
 .../amd/agesa/f14/Proc/Common/AmdS3LateRestore.c   |  215 +
 .../amd/agesa/f14/Proc/Common/AmdS3Save.c          |  381 +
 .../amd/agesa/f14/Proc/Common/CommonInits.c        |  137 +
 .../amd/agesa/f14/Proc/Common/CommonInits.h        |   66 +
 .../amd/agesa/f14/Proc/Common/CommonPage.h         |  118 +
 .../amd/agesa/f14/Proc/Common/CommonReturns.c      |  174 +
 .../amd/agesa/f14/Proc/Common/CreateStruct.c       |  315 +
 .../amd/agesa/f14/Proc/Common/CreateStruct.h       |  197 +
 .../amd/agesa/f14/Proc/Common/S3RestoreState.c     |  443 +
 .../amd/agesa/f14/Proc/Common/S3SaveState.c        |  647 +
 .../amd/agesa/f14/Proc/Common/S3SaveState.h        |  357 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h |  104 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h   |   80 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbGfx.h         |  290 +
 .../agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h  |   63 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c |  116 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.h |   56 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbPcie.h        |  352 +
 .../agesa/f14/Proc/GNB/Common/GnbPcieFamServices.h |  117 +
 .../amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h |12425 ++++++++++++++++++++
 .../f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c  |  524 +
 .../f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h    |   62 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c     |  131 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h     |   74 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c        |  722 ++
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.h        |   56 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c  |  112 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.h  |   55 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c  |  131 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h  |   56 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c     |  126 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h     |   56 +
 .../f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c  |  666 ++
 .../f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h  |   57 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c |  364 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.h |   98 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c    |  209 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.h    |  113 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c     |  315 +
 .../amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h     |   78 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c        |   95 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c          |  112 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtLate.c         |   93 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtMid.c          |   93 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtPost.c         |  115 +
 .../amd/agesa/f14/Proc/GNB/GnbInitAtReset.c        |   90 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h    | 1858 +++
 .../Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c   |  222 +
 .../GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h    |   66 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h   |   58 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c     |  460 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.h     |  148 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c   |  130 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h   |   66 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c |  129 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h |   63 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c    |  123 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h    |   67 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c   |  126 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h   |   74 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c  |  405 +
 .../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h  |  148 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c   |  157 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h   |   74 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c   |  176 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c  |  180 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h  |   55 +
 .../Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h   |   56 +
 .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c |  185 +
 .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h |   64 +
 .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c    |  574 +
 .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.h    |   65 +
 .../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c    |  572 +
 .../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h    |  200 +
 .../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h  |   56 +
 .../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c    |  247 +
 .../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h    |   74 +
 .../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c  |  351 +
 .../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h  |   83 +
 .../GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl   |   68 +
 .../GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl     |  373 +
 .../GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl  |  328 +
 .../GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl     |  682 ++
 .../Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h |   54 +
 .../GNB/Modules/GnbPcieConfig/PcieConfigData.c     |  379 +
 .../GNB/Modules/GnbPcieConfig/PcieConfigData.h     |   65 +
 .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c |  356 +
 .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h |  123 +
 .../GNB/Modules/GnbPcieConfig/PcieInputParser.c    |  218 +
 .../GNB/Modules/GnbPcieConfig/PcieInputParser.h    |   75 +
 .../GNB/Modules/GnbPcieConfig/PcieMapTopology.c    |  720 ++
 .../GNB/Modules/GnbPcieConfig/PcieMapTopology.h    |   58 +
 .../Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h    |   62 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c   |  346 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h   |   57 +
 .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c   |  141 +
 .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.h   |   56 +
 .../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c |  192 +
 .../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h |   56 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c |  197 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h |   61 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c |  558 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.h |  107 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c  |  230 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h  |   95 +
 .../Modules/GnbPcieInitLibV1/PciePortServices.c    |  406 +
 .../Modules/GnbPcieInitLibV1/PciePortServices.h    |  101 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c   |  350 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h   |   75 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c |  221 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.h |   83 +
 .../Modules/GnbPcieInitLibV1/PcieSiliconServices.c |  255 +
 .../Modules/GnbPcieInitLibV1/PcieSiliconServices.h |   73 +
 .../GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl    |  217 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c  |  100 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h  |   56 +
 .../GnbPcieInitLibV1/PcieTopologyServices.c        |  692 ++
 .../GnbPcieInitLibV1/PcieTopologyServices.h        |  134 +
 .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c  |  437 +
 .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h  |  128 +
 .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c   |  291 +
 .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h   |  128 +
 .../Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h  |   52 +
 .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c   |  828 ++
 .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.h   |   64 +
 .../Modules/GnbPcieTrainingV1/PcieWorkarounds.c    |  375 +
 .../Modules/GnbPcieTrainingV1/PcieWorkarounds.h    |   56 +
 .../f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c     |  348 +
 .../Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c   |  222 +
 .../Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h   |   55 +
 .../f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c   |  636 +
 .../f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h   |   61 +
 .../f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c    |  678 ++
 .../agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c   |   98 +
 .../f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h |  981 ++
 .../f14/Proc/GNB/Nb/Family/NbFamilyServices.h      |  109 +
 .../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c    |  401 +
 .../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.h    |   54 +
 .../amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c  |  109 +
 .../amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.h  |   61 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c       |   95 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbConfigData.h       |   69 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c  |  204 +
 src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.h  |   55 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c      |  123 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.h      |   54 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c        |  124 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h        |   58 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c   |  122 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h   |   56 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c       |  122 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.h       |   54 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c      |   96 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.h      |   54 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c        |  600 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h        |   70 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c           |  652 +
 .../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h           |  185 +
 .../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c    |   72 +
 .../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl  |  126 +
 .../Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h    |  660 ++
 .../GNB/PCIe/Family/0x14/F14PcieComplexConfig.c    |  125 +
 .../GNB/PCIe/Family/0x14/F14PcieComplexServices.c  |  243 +
 .../Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c |  167 +
 .../Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c |  120 +
 .../GNB/PCIe/Family/0x14/F14PcieWrapperServices.c  |  631 +
 .../Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h |  241 +
 .../Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h |  102 +
 .../f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h  |  135 +
 .../f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl     |  217 +
 .../f14/Proc/GNB/PCIe/Feature/PciePowerGate.c      |  372 +
 .../f14/Proc/GNB/PCIe/Feature/PciePowerGate.h      |   69 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c         |  349 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h         |   67 +
 .../agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c  |  125 +
 .../agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.h  |   55 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c    |   93 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h    |   55 +
 .../agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c   |  114 +
 .../agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.h   |   55 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c   |  139 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.h   |   62 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c     |  154 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h     |   56 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c      |  158 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.h      |   56 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c     |  256 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h     |   62 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c |  229 +
 .../amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.h |   55 +
 .../agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c    |  163 +
 .../agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h    |   67 +
 .../amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c        |  362 +
 .../agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c |  121 +
 .../agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h |   58 +
 .../f14/Proc/HT/Fam10/htNbOptimizationFam10.c      |  222 +
 .../f14/Proc/HT/Fam10/htNbOptimizationFam10.h      |   74 +
 .../amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c  |  402 +
 .../amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.h  |   91 +
 .../agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c   |  445 +
 .../agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.h   |  129 +
 .../amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c        |  147 +
 .../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c   |  139 +
 .../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h   |   68 +
 .../f14/Proc/HT/Features/htFeatDynamicDiscovery.c  |  783 ++
 .../f14/Proc/HT/Features/htFeatDynamicDiscovery.h  |   80 +
 .../amd/agesa/f14/Proc/HT/Features/htFeatGanging.c |  218 +
 .../amd/agesa/f14/Proc/HT/Features/htFeatGanging.h |   80 +
 .../agesa/f14/Proc/HT/Features/htFeatNoncoherent.c |  375 +
 .../agesa/f14/Proc/HT/Features/htFeatNoncoherent.h |   81 +
 .../f14/Proc/HT/Features/htFeatOptimization.c      |  886 ++
 .../f14/Proc/HT/Features/htFeatOptimization.h      |  140 +
 .../amd/agesa/f14/Proc/HT/Features/htFeatRouting.c |  493 +
 .../amd/agesa/f14/Proc/HT/Features/htFeatRouting.h |   90 +
 .../amd/agesa/f14/Proc/HT/Features/htFeatSets.c    |  114 +
 .../agesa/f14/Proc/HT/Features/htFeatSublinks.c    |  232 +
 .../agesa/f14/Proc/HT/Features/htFeatSublinks.h    |   80 +
 .../Proc/HT/Features/htFeatTrafficDistribution.c   |  278 +
 .../Proc/HT/Features/htFeatTrafficDistribution.h   |   79 +
 .../amd/agesa/f14/Proc/HT/Features/htIds.c         |  153 +
 .../amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c  |  492 +
 .../amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h  |  178 +
 .../agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c   |  142 +
 .../agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.h   |   62 +
 .../agesa/f14/Proc/HT/NbCommon/htNbOptimization.c  |  258 +
 .../agesa/f14/Proc/HT/NbCommon/htNbOptimization.h  |   91 +
 .../amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c |  335 +
 .../amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.h |  108 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c      |  112 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.h      |  562 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h     |  144 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph.c        |  199 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph1.c       |   70 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph2.c       |   71 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph3Line.c   |   76 +
 .../agesa/f14/Proc/HT/htGraph/htGraph3Triangle.c   |   77 +
 .../agesa/f14/Proc/HT/htGraph/htGraph4Degenerate.c |   80 +
 .../f14/Proc/HT/htGraph/htGraph4FullyConnected.c   |   83 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph4Kite.c   |   81 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph4Line.c   |   80 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph4Square.c |   80 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph4Star.c   |   80 +
 .../f14/Proc/HT/htGraph/htGraph5FullyConnected.c   |   80 +
 .../f14/Proc/HT/htGraph/htGraph5TwistedLadder.c    |   89 +
 .../f14/Proc/HT/htGraph/htGraph6DoubloonLower.c    |   75 +
 .../f14/Proc/HT/htGraph/htGraph6DoubloonUpper.c    |   75 +
 .../f14/Proc/HT/htGraph/htGraph6FullyConnected.c   |   86 +
 .../f14/Proc/HT/htGraph/htGraph6TwinTriangles.c    |   92 +
 .../f14/Proc/HT/htGraph/htGraph6TwistedLadder.c    |   92 +
 .../f14/Proc/HT/htGraph/htGraph7FullyConnected.c   |   78 +
 .../f14/Proc/HT/htGraph/htGraph7TwistedLadder.c    |   95 +
 .../agesa/f14/Proc/HT/htGraph/htGraph8DoubloonM.c  |   76 +
 .../f14/Proc/HT/htGraph/htGraph8FullyConnected.c   |   79 +
 .../amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c |   96 +
 .../Proc/HT/htGraph/htGraph8TwinFullyFourWays.c    |   96 +
 .../f14/Proc/HT/htGraph/htGraph8TwistedLadder.c    |   95 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c |  242 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.h |  490 +
 .../amd/agesa/f14/Proc/HT/htInterfaceCoherent.c    |  264 +
 .../amd/agesa/f14/Proc/HT/htInterfaceCoherent.h    |  115 +
 .../amd/agesa/f14/Proc/HT/htInterfaceGeneral.c     |  539 +
 .../amd/agesa/f14/Proc/HT/htInterfaceGeneral.h     |  162 +
 .../amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c |  394 +
 .../amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.h |  138 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c      |  579 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c        |  247 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htNb.h        | 1112 ++
 .../amd/agesa/f14/Proc/HT/htNbHardwareFam10.h      |  123 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c    |  670 ++
 src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h    |  298 +
 src/vendorcode/amd/agesa/f14/Proc/HT/htPage.h      |   66 +
 .../amd/agesa/f14/Proc/HT/htTopologies.h           |   72 +
 src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h     |  128 +
 src/vendorcode/amd/agesa/f14/Proc/IDS/IdsPage.h    |   59 +
 src/vendorcode/amd/agesa/f14/Proc/IDS/OptionsIds.h |   69 +
 .../amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c     |  594 +
 .../amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c     |  357 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c        |  207 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c        |  261 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c        |  260 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c        |  274 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c        |  429 +
 .../amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c        |  260 +
 .../amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c        |  578 +
 .../amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c        |  357 +
 .../amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c        |  261 +
 .../amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c        |  260 +
 .../amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c        |  274 +
 .../amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c        |  259 +
 .../amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c        |  261 +
 .../amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c        |  260 +
 .../amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c        |  260 +
 .../amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c        |  259 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c    |  141 +
 .../amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c    |  213 +
 .../amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h    |   82 +
 .../amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c    |  341 +
 .../amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h    |   82 +
 .../amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c        |  573 +
 .../amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c        |  321 +
 .../amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h        |   82 +
 .../amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c        |  174 +
 .../f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c     |  195 +
 .../agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c  |  528 +
 .../agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.h  |  110 +
 .../agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c    |  152 +
 .../agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h    |   82 +
 .../amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c  |  172 +
 .../amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.h  |   80 +
 .../amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c  |  144 +
 .../amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c    |  218 +
 .../amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h    |   80 +
 .../f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c      |  176 +
 .../f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h      |   79 +
 .../amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c    |  171 +
 .../amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h    |   81 +
 .../f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c  |  286 +
 .../f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c  |   88 +
 .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c          |  714 ++
 .../amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c      |  324 +
 .../amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c    |  372 +
 .../amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c      |  379 +
 .../amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c      |  373 +
 .../amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c      |  372 +
 .../amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c      |  292 +
 .../amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c      |  380 +
 .../amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c      |  380 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c  |  143 +
 .../amd/agesa/f14/Proc/Mem/Main/merrhdl.c          |  189 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c |  138 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c    |  240 +
 .../amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c |  697 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c |  128 +
 .../amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c    |  218 +
 .../amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c         |  265 +
 .../amd/agesa/f14/Proc/Mem/Main/mmMemClr.c         |  110 +
 .../amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c     |  597 +
 .../amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c |  138 +
 .../amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c    |  158 +
 .../agesa/f14/Proc/Mem/Main/mmParallelTraining.c   |  273 +
 .../agesa/f14/Proc/Mem/Main/mmStandardTraining.c   |  111 +
 .../amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c       |  242 +
 .../amd/agesa/f14/Proc/Mem/Main/mmflow.c           |  384 +
 .../amd/agesa/f14/Proc/Mem/Main/mmlvddr3.h         |   82 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm  |  497 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c    |  253 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c   |  652 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c  |  224 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c        |  731 ++
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.h        |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c          |  485 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h          |  196 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c       |  365 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c      |  136 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c  |  139 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c       |  195 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c        |  241 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c       |  167 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnprotoc32.c     |   67 +
 .../amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c       |  627 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c    |  226 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c          |  748 ++
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.h          |   85 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c |  490 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h |  210 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c         |  469 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c        |  140 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c    |  140 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c         |  199 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c          |  201 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c       |   87 +
 .../amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c         |  574 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c    |  226 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c          |  716 ++
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c         |  515 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c |  482 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.h |  199 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c        |  142 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c    |  140 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c         |  186 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c          |  200 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c       |  170 +
 .../amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c         |  548 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c    |  224 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c          |  740 ++
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c         |  409 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c        |  135 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c |  487 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h |  202 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c    |  139 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c         |  195 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c          |  241 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c         |  183 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnprotohy.c       |   67 +
 .../amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c         |  630 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c |  495 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h |  114 +
 .../amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c          |  747 ++
 .../amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c        |  141 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c          |  576 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c         |  490 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c        |  168 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c    |  136 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c         |  252 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c |  456 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h |  250 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c          |  230 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c         |  244 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c       |  165 +
 .../amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c         |  600 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c |  494 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h |  125 +
 .../amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c          |  776 ++
 .../amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c        |  142 +
 .../amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c    |  141 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c |  494 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h |  125 +
 .../amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c          |  776 ++
 .../amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.h          |   85 +
 .../amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c        |  142 +
 .../amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c    |  141 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c      |  527 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c    |  929 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c   | 2651 +++++
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c  | 1268 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c  |  268 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c   | 1184 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c   | 1377 +++
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c   |  437 +
 .../amd/agesa/f14/Proc/Mem/NB/mntrain2.c           |  133 +
 .../amd/agesa/f14/Proc/Mem/NB/mntrain3.c           |  236 +
 .../amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c       |  326 +
 .../amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c       |  205 +
 .../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c          |  161 +
 .../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c          |  257 +
 .../amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c          |  210 +
 .../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c          |  166 +
 .../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c          |  205 +
 .../amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c          |  192 +
 .../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c          |  166 +
 .../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c          |  161 +
 .../amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c          |  325 +
 .../amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c          |  221 +
 .../amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c          |  199 +
 .../amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c          |  257 +
 .../amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c          |  235 +
 .../amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c          |  181 +
 .../amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c          |  182 +
 .../amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c          |  257 +
 .../amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c          |  211 +
 .../amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c          |  257 +
 .../amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c          |  211 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c      |  510 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c |  190 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c |  111 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c |  111 +
 .../amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c          |  250 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c   |  179 +
 .../amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c           |  189 +
 .../amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c        |  163 +
 .../amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c           |  210 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c   |  229 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c   |  200 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c         |  234 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h         |  126 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c       |  164 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h       |   90 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c      | 1117 ++
 .../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h      |  184 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c         |  237 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h         |  136 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c   | 1102 ++
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h   |  127 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c       |  170 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h       |   92 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c      |  297 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h      |   89 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c      |  493 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h      |   98 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c      | 1153 ++
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h      |  177 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c     |  166 +
 .../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c      |  686 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c    |  264 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c |  127 +
 .../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c    |  896 ++
 .../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h    |  119 +
 .../amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c         | 1279 ++
 .../amd/agesa/f14/Proc/Mem/Tech/mttecc.c           |  209 +
 .../amd/agesa/f14/Proc/Mem/Tech/mtthrc.c           |  306 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c |  255 +
 .../amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c        |  427 +
 .../amd/agesa/f14/Proc/Mem/Tech/mttsrc.c           |  346 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/ma.h         |  318 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/memPage.h    |   59 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/merrhdl.h    |  105 +
 .../amd/agesa/f14/Proc/Mem/mfParallelTraining.h    |  115 +
 .../amd/agesa/f14/Proc/Mem/mfStandardTraining.h    |   83 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h   |   85 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h       |  283 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h      |   82 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h         | 1003 ++
 src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h         | 1375 +++
 src/vendorcode/amd/agesa/f14/Proc/Mem/mp.h         |  569 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mport.h      |   69 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mt.h         |  435 +
 src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h         |  238 +
 .../amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c  |  104 +
 .../amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h  |   77 +
 .../amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c  |  112 +
 .../amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h  |   77 +
 .../amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c  |  103 +
 .../agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c   |  138 +
 .../agesa/f14/Proc/Recovery/GNB/NbInitRecovery.h   |   57 +
 .../agesa/f14/Proc/Recovery/HT/htInitRecovery.c    |  163 +
 .../amd/agesa/f14/Proc/Recovery/HT/htInitReset.c   |  332 +
 .../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c    |  711 ++
 .../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h    |  110 +
 .../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c |  162 +
 .../f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c     |   62 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c  |  651 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h  |  110 +
 .../agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c   |  165 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c  |  655 ++
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h  |  110 +
 .../agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c   |  167 +
 .../agesa/f14/Proc/Recovery/Mem/NB/HY/mrndcthy.c   |   76 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c  |  710 ++
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h  |  110 +
 .../agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c   |  162 +
 .../agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c |   62 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c  |  651 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h  |   97 +
 .../agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c   |  363 +
 .../agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c   |  191 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c  |  653 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h  |  125 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c  |  652 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h  |   97 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c  |  651 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h  |   97 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c       |  190 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c    | 1502 +++
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c    |  298 +
 .../amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c |  127 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c       |  261 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c  |  183 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c  |  111 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c  |  111 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c    |  178 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c |  183 +
 .../agesa/f14/Proc/Recovery/Mem/Ps/mrprc10opspd.c  |   93 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c |  199 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c    |  218 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c    |  188 +
 .../agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c   |  189 +
 .../f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c      |  244 +
 .../f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c      |  360 +
 .../f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c      |  326 +
 .../f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h      |  132 +
 .../f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c      |  347 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c |  287 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c |  115 +
 .../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c |  437 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mrdef.c        |  129 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mrinit.c       |  126 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mrm.c          |  288 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mrport.h       |   82 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mrt3.h         |  121 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mru.asm        |  187 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mru.h          |  140 +
 .../amd/agesa/f14/Proc/Recovery/Mem/mruc.c         |  267 +
 .../amd/agesa/f14/Proc/Recovery/recoveryPage.h     |   59 +
 src/vendorcode/amd/agesa/f14/cpcar.inc             | 1124 ++
 src/vendorcode/amd/agesa/f14/cpcarmac.inc          |  447 +
 src/vendorcode/amd/agesa/f14/errno.h               |   38 +
 src/vendorcode/amd/agesa/f14/gcccar.inc            | 1606 +++
 src/vendorcode/amd/agesa/gcccar.inc                | 1606 ---
 1775 files changed, 272635 insertions(+), 272635 deletions(-)

diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index dfa6d1e..c29b730 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -15,4 +15,4 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
 
 subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index ea6c51a..1e0f37b 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -20,7 +20,7 @@
 ramstage-y += chip_name.c
 driver-y += model_14_init.c
 
-AGESA_ROOT = ../../../../vendorcode/amd/agesa
+AGESA_ROOT = ../../../../vendorcode/amd/agesa/f14
 
 agesa_lib_src  = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index 94433b7..a81d135 100644
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -6,14 +6,14 @@ ramstage-y += pmio.c
 
 #SB800 CIMx share AGESA V5 lib code
 ifneq ($(CONFIG_AMD_AGESA),y)
- romstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
- ramstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
+ romstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
+ ramstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
 
- AGESA_INC := -Isrc/vendorcode/amd/agesa/ \
-	      -Isrc/vendorcode/amd/agesa/Include \
-	      -Isrc/vendorcode/amd/agesa/Proc/IDS/ \
-	      -Isrc/vendorcode/amd/agesa/Proc/CPU/ \
-	      -Isrc/vendorcode/amd/agesa/Proc/CPU/Family
+ AGESA_INC := -Isrc/vendorcode/amd/agesa/f14/ \
+	      -Isrc/vendorcode/amd/agesa/f14/Include \
+	      -Isrc/vendorcode/amd/agesa/f14/Proc/IDS/ \
+	      -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/ \
+	      -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family
 
  CFLAGS += $(AGESA_INC)
 endif
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
 ramstage-y += reset.c
 ramstage-y += pmio.c
 
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
 ramstage-y += reset.c
 ramstage-y += pmio.c
 
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
 ramstage-y += reset.c
 ramstage-y += pmio.c
 
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index 328fd0f..aeb373e 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -5,4 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 
 subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14
diff --git a/src/vendorcode/amd/agesa/AGESA.h b/src/vendorcode/amd/agesa/AGESA.h
deleted file mode 100644
index 0f348d6..0000000
--- a/src/vendorcode/amd/agesa/AGESA.h
+++ /dev/null
@@ -1,3022 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA core interface
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Include
- * @e \$Revision: 41504 $   @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-
-#ifndef _AGESA_H_
-#define _AGESA_H_
-
-#include  "Porting.h"
-#include  "AMD.h"
-
-//
-//
-// AGESA Types and Definitions
-//
-//
-
-// AGESA BASIC CALLOUTS
-#define AGESA_MEM_RELEASE              0x00028000
-
-// AGESA ADVANCED CALLOUTS, Processor
-#define AGESA_CHECK_UMA                0x00028100
-#define AGESA_DO_RESET                 0x00028101
-#define AGESA_ALLOCATE_BUFFER          0x00028102
-#define AGESA_DEALLOCATE_BUFFER        0x00028103
-#define AGESA_LOCATE_BUFFER            0x00028104
-#define AGESA_RUNFUNC_ONAP             0x00028105
-
-// AGESA ADVANCED CALLOUTS, HyperTransport
-
-// AGESA ADVANCED CALLOUTS, Memory
-#define AGESA_READ_SPD                 0x00028140
-#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
-#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
-#define AGESA_READ_SPD_RECOVERY        0x00028143
-#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
-#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
-
-// AGESA IDS CALLOUTS
-#define AGESA_GET_IDS_INIT_DATA       0x00028200
-
-// AGESA GNB CALLOUTS
-#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
-
-//------------------------------------------------------------------------
-//
-// HyperTransport Interface
-
-
-
-//-----------------------------------------------------------------------------
-//                         HT DEFINITIONS AND MACROS
-//
-//-----------------------------------------------------------------------------
-
-
-// Width equates for call backs
-#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
-#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
-#define HT_WIDTH_4_BITS              4
-#define HT_WIDTH_2_BITS              2
-#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
-
-// Frequency Limit equates for call backs which take a frequency supported mask.
-#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
-#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
-#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
-
-// Unit ID Clumping special values
-#define HT_CLUMPING_DISABLE          0x00000000
-#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
-
-#define HT_LIST_TERMINAL             0xFF             ///< End of list.
-#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
-#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
-
-// Event Notify definitions
-
-// Event definitions.
-
-// Coherent subfunction events
-#define HT_EVENT_COH_EVENTS             0x10001000
-#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
-#define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
-#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
-#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
-#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
-
-// Non-coherent subfunction events
-#define HT_EVENT_NCOH_EVENTS         0x10002000
-#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
-#define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
-#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
-#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
-#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
-#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
-
-// Optimization subfunction events
-#define HT_EVENT_OPT_EVENTS               0x10003000
-#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
-#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
-
-// HW Fault events
-#define HT_EVENT_HW_EVENTS           0x10004000
-#define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
-#define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
-
-// The Recovery HT component uses 0x10005000 for events.
-// For consistency, we avoid that range here.
-
-#define HT_MAX_NC_BUIDS 32
-//----------------------------------------------------------------------------
-//                         HT TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-/// Specify the state redundant links are to be left in after match.
-///
-/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
-/// or powered off.
-
-typedef enum {
-  MATCHED,                               ///< The link matches the requested customization.
-                                         ///< When used with IGNORE_LINK,
-                                         ///< this will generally require other software to initialize the link.
-                                         ///< When used with SKIP_REGANG,
-                                         ///< the two unganged links will be available for distribution.
-
-  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
-                                         ///< Power Off is only supported for coherent links.
-                                         ///< Link power off may occur at a warm reset rather than immediately.
-                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
-
-  UNMATCHED,                             ///< The link should be processed according to normal defaults.
-                                         ///< Effectively, the link does not match the requested customization.
-                                         ///< This can be used to exclude links from a following match any.
-
-  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
-} FINAL_LINK_STATE;
-
-/// Swap a device from its current id to a new one.
-
-typedef struct {
-  IN       UINT8 FromId;                 ///< The device responding to FromId,
-  IN       UINT8 ToId;                   ///< will be moved to ToId.
-} BUID_SWAP_ITEM;
-
-
-/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
-/// the final in order list of device ids is provided. (There can be more swaps than devices.)
-/// The unused entries in both are filled with 0xFF.
-
-typedef struct {
-  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
-  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
-} BUID_SWAP_LIST;
-
-
-/// Control Manual Initialization of Non-Coherent Chains
-///
-/// This interface is checked every time a non-coherent chain is
-/// processed.  BUID assignment may be controlled explicitly on a
-/// non-coherent chain. Provide a swap list.  Swaps controls the
-/// BUID assignment and FinalIds provides the device to device
-/// Linking.  Device orientation can be detected automatically, or
-/// explicitly.  See interface documentation for more details.
-///
-/// If a manual swap list is not supplied,
-/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
-/// based on each device's unit count.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
-  IN       UINT8 Link;                         ///< The Link on the host for this chain
-  // Override fields
-  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
-} MANUAL_BUID_SWAP_LIST;
-
-
-/// Override options for DEVICE_CAP_OVERRIDE.
-///
-/// Specify which override actions should be performed.  For Checks, 1 means to check the item
-/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
-/// 0 means to ignore the override.
-
-typedef struct {
-  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
-  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
-  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
-  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
-  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
-  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
-  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
-} DEVICE_CAP_OVERRIDE_OPTIONS;
-
-/// Override capabilities of a device.
-///
-/// This interface is checked once for every Link on every IO device.
-/// Provide the width and frequency capability if needed for this device.
-/// This is used along with device capabilities, the limit interfaces, and northbridge
-/// limits to compute the default settings.  The components of the device's PCI config
-/// address are provided, so its settings can be consulted if need be.
-/// The optional callout is a catch all.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
-  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
-  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
-  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
-  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
-  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
-  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
-  // Override fields
-  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
-  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
-  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
-  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
-  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
-} DEVICE_CAP_OVERRIDE;
-
-/// Callout param struct for override capabilities of a device.
-///
-/// If the optional callout is implemented this param struct is passed to it.
-
-typedef struct {
-  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
-  // Match fields
-  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
-  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
-  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
-  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
-  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
-  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
-  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
-  // Override fields
-     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
-     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
-     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
-     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
-} DEVICE_CAP_CALLOUT_PARAMS;
-
-///  Limits for CPU to CPU Links.
-///
-///  For each coherent connection this interface is checked once.
-///  Provide the frequency and width if needed for this Link (usually based on board
-///  restriction).  This is used with CPU device capabilities and northbridge limits
-///  to compute the default settings.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
-  IN       UINT8 LinkA;                  ///< The Link on this Node
-  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
-  IN       UINT8 LinkB;                  ///< The Link on that Node
-  // Limit fields
-  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
-  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
-  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
-} CPU_TO_CPU_PCB_LIMITS;
-
-///  Get limits for non-coherent Links.
-///
-/// For each non-coherent connection this interface is checked once.
-/// Provide the frequency and width if needed for this Link (usually based on board
-/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
-/// to compute the default settings.
-///
-typedef struct {
-  // Match fields
-  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
-  IN       UINT8 HostLink;                 ///< The Link about to be initialized
-  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
-  // Limit fields
-  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
-  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
-  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
-} IO_PCB_LIMITS;
-
-///  Manually control bus number assignment.
-///
-/// This interface is checked every time a non-coherent chain is processed.
-/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
-/// assignments, this interface can provide explicit control.  For each chain, provide
-/// the bus number range to use.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
-  IN       UINT8 Link;                   ///< The Link on the host for this chain
-  // Override fields
-  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
-  IN       UINT8 SubBus;                 ///< Subordinate Bus number
-} OVERRIDE_BUS_NUMBERS;
-
-
-///  Ignore a Link.
-///
-///  This interface is checked every time a coherent Link is found and then every
-///  time a non-coherent Link from a CPU is found.
-///  Any coherent or non-coherent Link from a CPU can be ignored and not used
-///  for discovery or initialization.  Useful for connection based systems.
-///  (Note: not checked for IO device to IO Device Links.)
-///  (Note: not usable for internal links (MCM processors).)
-
-typedef struct {
-  // Match fields
-  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
-  IN       UINT8 Link;                   ///< The Link about to be initialized
-  // Customization fields
-  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
-} IGNORE_LINK;
-
-
-///  Skip reganging of subLinks.
-///
-///  This interface is checked whenever two subLinks are both connected to the same CPUs.
-///  Normally, unganged sublinks between the same two CPUs are reganged.
-///  Provide a matching structure to leave the Links unganged.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
-  IN       UINT8 LinkA;                  ///< The Link on this Node
-  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
-  IN       UINT8 LinkB;                  ///< The Link on that Node
-  // Customization fields
-  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
-} SKIP_REGANG;
-
-///  The System Socket layout, which sockets are physically connected.
-///
-///  The hardware method for Socket naming is preferred.  Use this software method only
-///  if required.
-
-typedef struct {
-  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
-  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
-  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
-} SYSTEM_PHYSICAL_SOCKET_MAP;
-
-//----------------------------------------------------------------------------
-///
-/// This is the input structure for AmdHtInitialize.
-///
-typedef struct {
-  // Basic level customization
-  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
-                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
-  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
-                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
-  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
-                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
-
-  // Advanced Level Customization
-  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
-                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
-  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
-                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
-  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
-                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
-                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
-  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
-                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
-                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
-  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
-                                                          ///< Use either auto bus numbering or override bus
-                                                          ///< numbers, not both.
-                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
-
-  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
-                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
-  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
-                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
-                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
-
-  // Expert Level Customization
-  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
-                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
-  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
-                                                     ///< The hardware socket naming method is preferred,
-                                                     ///<  If it can't be used, this provides a software method.
-                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
-} AMD_HT_INTERFACE;
-
-//-----------------------------------------------------------------------------
-//
-// HT Recovery Interface
-//
-
-
-/*-----------------------------------------------------------------------------
- *              HT Recovery DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-// BBHT subfunction events
-#define HT_EVENT_BB_EVENTS         0x10005000
-#define HT_EVENT_BB_BUID_EXCEED    0x10015000
-#define HT_EVENT_BB_DEVICE_FAILED  0x10055000
-#define HT_EVENT_BB_AUTO_DEPTH     0x10065000
-
-/*----------------------------------------------------------------------------
- *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/// The Interface structure to Recovery HT.
-
-typedef struct {
-  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
-                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
-     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
-                                   ///< else, for manual init unmodified.
-} AMD_HT_RESET_INTERFACE;
-
-/*----------------------------------------------------------------------------
- *   CPU Feature related info
- *----------------------------------------------------------------------------
- */
-
-/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
-typedef enum {
-  C1eModeDisabled                   = 0,   ///< Disabled
-  C1eModeHardware                   = 1,   ///< Hardware method
-  C1eModeMsgBased                   = 2,   ///< Message-based method
-  C1eModeSoftwareDeprecated         = 3,   ///< Deprecated software SMI method.
-                                           ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
-                                           ///< example host BIOS SMM Handler implementation
-  C1eModeHardwareSoftwareDeprecated = 4,   ///< Hardware or deprecated software SMI method
-  MaxC1eMode                        = 5    ///< Not a valid value, used for verifying input
-} PLATFORM_C1E_MODES;
-
-/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
-typedef enum {
-  CStateModeDisabled = 0,           ///< Disabled
-  CStateModeC6       = 1,           ///< C6 State
-  MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
-} PLATFORM_CSTATE_MODES;
-
-/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
-typedef enum {
-  CpbModeAuto     = 0,           ///< Auto
-  CpbModeDisabled = 1,           ///< Disabled
-  MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
-} PLATFORM_CPB_MODES;
-
-/*----------------------------------------------------------------------------
- *   GNB PCIe configuration info
- *----------------------------------------------------------------------------
- */
-
-// Event definitions
-
-
-#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
-#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
-#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
-#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
-#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
-#define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
-#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
-#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
-#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
-#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
-
-
-#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
-
-/// PCIe port misc extended controls
-typedef struct  {
-  IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
-  IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
-                                                             *  @li @b 0 - port can advertize muximum supported capability
-                                                             *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
-                                                             */
-} PCIe_PORT_MISC_CONTROL;
-
-
-/// PCIe port configuration data
-typedef struct  {
-  IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
-  IN       UINT8                   ChannelType;              /**< Channel type.
-                                                               *  @li @b 0 - "lowLoss",
-                                                               *  @li @b 1 - "highLoss",
-                                                               *  @li @b 2 - "mob0db",
-                                                               *  @li @b 3 - "mob3db",
-                                                               *  @li @b 4 - "extnd6db"
-                                                               *  @li @b 5 - "extnd8db"
-                                                               */
-  IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
-                                                               *   @li @b 0 - Native port device number
-                                                               *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14LaneConfigurations "Family 0x14")
-                                                               */
-  IN       UINT8                   FunctionNumber;           ///< Reserved for future use
-  IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
-                                                               *  @li @b 0 - Maximum supported by silicon
-                                                               *  @li @b 1 - Gen1
-                                                               *  @li @b 2 - Gen2
-                                                               *  @li @b 3 - Gen3
-                                                               */
-  IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
-                                                               *  @li @b 0 - Disabled
-                                                               *  @li @b 1 - L0s only
-                                                               *  @li @b 2 - L1 only
-                                                               *  @li @b 3 - L0s and L1
-                                                               */
-  IN       UINT8                   LinkHotplug;              /**< Hotplug control.
-                                                               *  @li @b 0 - Disabled
-                                                               *  @li @b 1 - Basic
-                                                               *  @li @b 2 - Server
-                                                               *  @li @b 3 - Enhanced
-                                                               */
-  IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
-                                                               *   identification which control reset for given port.
-                                                               *   Each port with unique GPIO should have unique ResetId assigned.
-                                                               *   All ports use same GPIO to control reset should have same ResetId assigned.
-                                                               *   see AgesaPcieSlotResetContol.
-                                                               */
-  IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
-} PCIe_PORT_DATA;
-
-/// DDI channel lane mapping
-typedef struct {                                          ///< Structure that discribe lane mapping
-  IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
-                                                           *  @li @b 0 - Map to lane 0
-                                                           *  @li @b 1 - Map to lane 1
-                                                           *  @li @b 2 - Map to lane 2
-                                                           *  @li @b 2 - Map to lane 3
-                                                           */
-  IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
-  IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
-  IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
-} CHANNEL_MAPPING;                                        ///< Lane mapping
-
-/// Common Channel Mapping
-typedef union {
-  IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
-  IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
-} CONN_CHANNEL_MAPPING;
-
-/// DDI Configuration data
-typedef struct  {
-  IN       UINT8                ConnectorType;            /**< Display Connector Type
-                                                            *  @li @b 0 - DP
-                                                            *  @li @b 1 - eDP
-                                                            *  @li @b 2 - Single Link DVI-D
-                                                            *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
-                                                            *  @li @b 4 - HDMI
-                                                            *  @li @b 5 - Travis DP-to-VGA
-                                                            *  @li @b 6 - Travis DP-to-LVDS
-                                                            *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
-                                                            *  @li @b 8 - Single Link DVI-I
-                                                            *  @li @b 9 - Native CRT (Family 0x14)
-                                                            *  @li @b 10 - Native LVDS (Family 0x14)
-                                                            *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
-                                                            *              The auto detection method only support panel with EDID.
-                                                            */
-  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
-                                                            *  @li @b 0 - AUX1
-                                                            *  @li @b 1 - AUX2
-                                                            *  @li @b 2 - AUX3
-                                                            *  @li @b 3 - AUX4
-                                                            *  @li @b 4 - AUX5
-                                                            *  @li @b 5 - AUX6
-                                                            */
-  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
-                                                            *  @li @b 0 - HDP1
-                                                            *  @li @b 1 - HDP2
-                                                            *  @li @b 2 - HDP3
-                                                            *  @li @b 3 - HDP4
-                                                            *  @li @b 4 - HDP5
-                                                            *  @li @b 5 - HDP6
-                                                            */
-  IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
-                                                            *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
-                                                            *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
-                                                            *  if Mapping[x] set to 0 than default mapping assumed
-                                                            */
-} PCIe_DDI_DATA;
-
-/// Engine Configuration
-typedef struct {
-  IN       UINT8                EngineType;               /**< Engine type
-                                                           *  @li @b 0 -  Ignore engine configuration
-                                                           *  @li @b 1 -  PCIe port
-                                                           *  @li @b 2 -  DDI
-                                                           */
-  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
-                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
-                                                           * @ref F14PcieLaneDescription "Family 0x14".
-                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
-                                                           * @ref F14LaneConfigurations "Family 0x14".
-                                                           */
-  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
-                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
-                                                           * @ref F14PcieLaneDescription "Family 0x14".
-                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
-                                                           * @ref F14LaneConfigurations "Family 0x14".
-                                                           */
-
-} PCIe_ENGINE_DATA;
-
-/// PCIe port descriptor
-typedef struct {
-  IN       UINT32               Flags;                    /**< Descriptor flags
-                                                           * @li @b Bit31 - last descriptor in complex
-                                                           */
-  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
-  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
-} PCIe_PORT_DESCRIPTOR;
-
-/// DDI descriptor
-typedef struct {
-  IN       UINT32               Flags;                    /**< Descriptor flags
-                                                           * @li @b Bit31 - last descriptor in complex
-                                                           */
-  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
-  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
-} PCIe_DDI_DESCRIPTOR;
-
-/// PCIe Complex descriptor
-typedef struct {
-  IN       UINT32               Flags;                    /**< Descriptor flags
-                                                           * @li @b Bit31 - last descriptor in topology
-                                                           */
-  IN       UINT32               SocketId;                 ///< Socket Id
-  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
-  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
-  IN       VOID                 *Reserved;                ///< Reserved for future use
-} PCIe_COMPLEX_DESCRIPTOR;
-
-/// Action to control PCIe slot reset
-typedef enum {
-  AssertSlotReset,                                        ///< Assert slot reset
-  DeassertSlotReset                                       ///< Deassert slot reset
-} PCIE_RESET_CONTROL;
-
-///Slot Reset Info
-typedef struct {
-  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
-  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
-  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
-} PCIe_SLOT_RESET_INFO;
-
-/// Engine descriptor type
-typedef enum {
-  PcieUnusedEngine = 0,                                   ///< Unused descriptor
-  PciePortEngine = 1,                                     ///< PCIe port
-  PcieDdiEngine = 2,                                      ///< DDI
-  MaxPcieEngine                                           ///< Max engine type for boundary check.
-} PCIE_ENGINE_TYPE;
-
-/// PCIe link capability/speed
-typedef enum  {
-  PcieGenMaxSupported,                                    ///< Maximum supported
-  PcieGen1 = 1,                                           ///< Gen1
-  PcieGen2,                                               ///< Gen2
-  MaxPcieGen                                              ///< Max Gen for boundary check
-} PCIE_LINK_SPEED_CAP;
-
-/// PCIe PSPP Power policy
-typedef enum  {
-  PsppDisabled,                                           ///< PSPP disabled
-  PsppPerformance = 1,                                    ///< Performance
-  PsppBalanceHigh,                                        ///< Balance-High
-  PsppBalanceLow,                                         ///< Balance-Low
-  PsppPowerSaving,                                        ///< Power Saving
-  MaxPspp                                                 ///< Max Pspp for boundary check
-} PCIE_PSPP_POLICY;
-
-/// DDI display connector type
-typedef enum {
-  ConnectorTypeDP,                                        ///< DP
-  ConnectorTypeEDP,                                       ///< eDP
-  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
-  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
-  ConnectorTypeHDMI,                                      ///< HDMI
-  ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
-  ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
-  ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
-  ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
-  ConnectorTypeCrt,                                       ///< CRT (VGA)
-  ConnectorTypeLvds,                                      ///< LVDS
-  ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
-  MaxConnectorType                                        ///< Not valid value, used to verify input
-} PCIE_CONNECTOR_TYPE;
-
-/// PCIe link channel type
-typedef enum {
-  ChannelTypeLowLoss,                                     ///< Low Loss
-  ChannelTypeHighLoss,                                    ///< High Loss
-  ChannelTypeMob0db,                                      ///< Mobile 0dB
-  ChannelTypeMob3db,                                      ///< Mobile 3dB
-  ChannelTypeExt6db,                                      ///< Extended 6dB
-  ChannelTypeExt8db,                                      ///< Extended 8dB
-  MaxChannelType                                          ///< Not valid value, used to verify input
-} PCIE_CHANNEL_TYPE;
-
-/// PCIe link ASPM
-typedef enum {
-  AspmDisabled,                                           ///< Disabled
-  AspmL0s,                                                ///< PCIe L0s link state
-  AspmL1,                                                 ///< PCIe L1 link state
-  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
-  MaxAspm                                                 ///< Not valid value, used to verify input
-} PCIE_ASPM_TYPE;
-
-/// PCIe link hotplug support
-typedef enum {
-  HotplugDisabled,                                        ///< Hotplug disable
-  HotplugBasic,                                           ///< Basic Hotplug
-  HotplugServer,                                          ///< Server Hotplug
-  HotplugEnhanced,                                        ///< Enhanced
-  HotplugInboard,                                         ///< Inboard
-  MaxHotplug                                              ///< Not valid value, used to verify input
-} PCIE_HOTPLUG_TYPE;
-
-/// PCIe link initialization
-typedef enum {
-  PortDisabled,                                           ///< Disable
-  PortEnabled                                             ///< Enable
-} PCIE_PORT_ENABLE;
-
-/// DDI Aux channel
-typedef enum {
-  Aux1,                                                   ///< Aux1
-  Aux2,                                                   ///< Aux2
-  Aux3,                                                   ///< Aux3
-  Aux4,                                                   ///< Aux4
-  Aux5,                                                   ///< Aux5
-  Aux6,                                                   ///< Aux6
-  MaxAux                                                  ///< Not valid value, used to verify input
-} PCIE_AUX_TYPE;
-
-/// DDI Hdp Index
-typedef enum {
-  Hdp1,                                                   ///< Hdp1
-  Hdp2,                                                   ///< Hdp2
-  Hdp3,                                                   ///< Hdp3
-  Hdp4,                                                   ///< Hdp4
-  Hdp5,                                                   ///< Hdp5
-  Hdp6,                                                   ///< Hdp6
-  MaxHdp                                                  ///< Not valid value, used to verify input
-} PCIE_HDP_TYPE;
-
-// Macro for statically initialization of various structures
-#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
-#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
-{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
-#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
-{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}}
-#define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \
-{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}
-
-
-/*----------------------------------------------------------------------------
- *   GNB configuration info
- *----------------------------------------------------------------------------
- */
-/// Configuration settings for GNB.
-typedef struct {
-  IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
-                                          ///< @li 0 = Stereo 3D is disabled (default).
-                                          ///< @li 1 = Use processor pin HPD1.
-                                          ///< @li 2 = Use processor pin HPD2
-                                          ///< @li 3 = Use processor pin HPD3
-                                          ///< @li 4 = Use processor pin HPD4
-                                          ///< @li 5 = Use processor pin HPD5
-                                          ///< @li 6 = Use processor pin HPD6
-                                          ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
-  IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
-                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
-  IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
-                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
-} GNB_ENV_CONFIGURATION;
-
-/// GNB configuration info
-typedef struct {
-  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
-                                                        * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
-                                                        * Example of topology definition for single socket system:
-                                                        * @code
-                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
-                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
-                                                        *    {
-                                                        *      0,   //Descriptor flags
-                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
-                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
-                                                        *    },
-                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
-                                                        *    {
-                                                        *      0,   //Descriptor flags
-                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
-                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
-                                                        *    },
-                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-                                                        *    {
-                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
-                                                        *    }
-                                                        *  };
-                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
-                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
-                                                        *    {
-                                                        *      0,   //Descriptor flags
-                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
-                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
-                                                        *    },
-                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
-                                                        *    {
-                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
-                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
-                                                        *    }
-                                                        *  };
-                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
-                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
-                                                        *   0,  //Socket ID
-                                                        *   &PortList[0],
-                                                        *   &DdiList[0],
-                                                        * }
-                                                        * @endcode
-                                                        */
-  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
-                                                         *  @li @b 0 - Disabled
-                                                         *  @li @b 1 - Performance
-                                                         *  @li @b 2 - Balance-High
-                                                         *  @li @b 3 - Balance-Low
-                                                         *  @li @b 4 - Power Saving
-                                                         */
-
-} GNB_CONFIGURATION;
-//
-//  MEMORY-SPECIFIC DATA STRUCTURES
-//
-//
-//
-//
-// AGESA MAXIMIUM VALUES
-//
-//   These Max values are used to define array sizes and associated loop
-//   counts in the code.  They reflect the maximum values that AGESA
-//   currently supports and does not necessarily reflect the hardware
-//   capabilities of configuration.
-//
-
-#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
-#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
-#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
-#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
-                                    ///< Eg: UINT16  *RcvEnDlys;
-                                    ///<     UINT8   *WrDqsDlys;
-                                    ///<     UINT8   *RdDqsDlys;
-                                    ///<     UINT8   *WrDatDlys;
-                                    ///<     UINT8   *RdDqsMinDlys;
-                                    ///<     UINT8   *RdDqsMaxDlys;
-                                    ///<     UINT8   *WrDatMinDlys;
-                                    ///<     UINT8   *WrDatMaxDlys;
-#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
-
-#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
-
-#define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
-#define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
-
-#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
-#define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
-#define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
-
-typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
-
-//        AGESA DEFINITIONS
-//
-//        Many of these are derived from the platform and hardware specific definitions
-
-/// EccSymbolSize override value
-#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
-#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
-#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
-/// CPU Package Type
-#define PT_L1       0                 ///< L1 Package type
-#define PT_M2       1                 ///< AM Package type
-#define PT_S1       2                 ///< S1 Package type
-
-/// Structures use to pass system Logical CPU-ID
-typedef struct {
-  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
-  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
-} CPU_LOGICAL_ID;
-
-/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-typedef enum {
-  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
-  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
-  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
-} AMD_PLATFORM_TYPE;
-
-/// Dram technology type
-typedef enum {
-  DDR2_TECHNOLOGY,      ///< DDR2 technology
-  DDR3_TECHNOLOGY       ///< DDR3 technology
-} TECHNOLOGY_TYPE;
-
-/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-typedef enum {
-  DDR400_FREQUENCY = 200,     ///< DDR 400
-  DDR533_FREQUENCY = 266,     ///< DDR 533
-  DDR667_FREQUENCY = 333,     ///< DDR 667
-  DDR800_FREQUENCY = 400,     ///< DDR 800
-  DDR1066_FREQUENCY = 533,    ///< DDR 1066
-  DDR1333_FREQUENCY = 667,    ///< DDR 1333
-  DDR1600_FREQUENCY = 800,    ///< DDR 1600
-  DDR1866_FREQUENCY = 933,    ///< DDR 1866
-  UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
-} MEMORY_BUS_SPEED;
-
-/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-typedef enum {
-  QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
-  QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
-} QUANDRANK_TYPE;
-
-/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-typedef enum {
-  TIMING_MODE_AUTO,           ///< Use best rate possible
-  TIMING_MODE_LIMITED,        ///< Set user top limit
-  TIMING_MODE_SPECIFIC        ///< Set user specified speed
-} USER_MEMORY_TIMING_MODE;
-
-/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
-typedef enum {
-  POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
-  POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
-  POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
-} POWER_DOWN_MODE;
-
-/// Low voltage support
-typedef enum {
-  VOLT1_5,                   ///< 1.5 Volt
-  VOLT1_35,                  ///< 1.35 Volt
-  VOLT1_25,                  ///< 1.25 Volt
-  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
-} DIMM_VOLTAGE;
-
-/// UMA Mode
-typedef enum {
-  UMA_NONE = 0,              ///< UMA None
-  UMA_SPECIFIED = 1,         ///< UMA Specified
-  UMA_AUTO = 2               ///< UMA Auto
-} UMA_MODE;
-
-/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
-typedef enum {
-  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
-  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
-  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
-  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
-} UMA_ALIGNMENT;
-
-///
-///   Global MCT Configuration Status Word (GStatus)
-///
-typedef enum {
-  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
-  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
-  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
-  GsbSoftHole,               ///< A Node Base gap was created
-  GsbHWHole,                 ///< A HW dram remap was created
-  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
-  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
-  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
-
-  GsbEOL                     ///< End of list
-} GLOBAL_STATUS_FIELD;
-
-///
-///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-///
-typedef enum {
-  EsbNoDimms,                  ///< No DIMMs
-  EsbSpdChkSum,                ///< SPD Checksum fail
-  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
-  EsbDimmMismatchT,            ///< dimm CL/T mismatch
-  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
-  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
-  EsbNoCycTime,                ///< SPD missing byte 23 or 25
-  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
-  EsbDramECCDis,               ///< Dram ECC requested but not enabled
-  EsbSpareDis,                 ///< Online spare requested but not enabled
-  EsbMinimumMode,              ///< Running in Minimum Mode
-  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
-  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
-  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
-  EsbSmallDqs,                 ///< DQS-DQ passing window too small
-  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
-
-  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
-  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
-                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
-  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
-                               ///< memory size of each DCT is not a power of two.
-
-  EsbEOL                       ///< End of list
-} ERROR_STATUS_FIELD;
-
-///
-///  Local Configuration Status (DIE_STRUCT.Status[31:0])
-///
-typedef enum {
-  SbRegistered,                ///< All DIMMs are Registered
-  SbEccDimms,                  ///< All banks ECC capable
-  SbParDimms,                  ///< All banks Addr/CMD Parity capable
-  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
-  Sb128bitmode,                ///< DCT in 128-bit mode operation
-  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
-  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
-  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
-  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
-  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
-  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
-  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
-  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
-  SbLrdimms,                   ///< All DIMMs are LRDIMMs
-
-  SbEOL                        ///< End of list
-} LOCAL_STATUS_FIELD;
-
-
-///< CPU MSR Register definitions ------------------------------------------
-#define SYS_CFG     0xC0010010
-#define TOP_MEM     0xC001001A
-#define TOP_MEM2    0xC001001D
-#define HWCR        0xC0010015
-#define NB_CFG      0xC001001F
-
-#define FS_BASE     0xC0000100
-#define IORR0_BASE  0xC0010016
-#define IORR0_MASK  0xC0010017
-#define BU_CFG      0xC0011023
-#define BU_CFG2     0xC001102A
-#define COFVID_STAT 0xC0010071
-#define TSC         0x10
-
-//-----------------------------------------------------------------------------
-///
-/// SPD Data for each DIMM.
-///
-typedef struct _SPD_DEF_STRUCT {
-  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
-  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
-} SPD_DEF_STRUCT;
-
-///
-/// Channel Definition Structure.
-/// This data structure defines entries that are specific to the channel initialization
-///
-typedef struct _CH_DEF_STRUCT {
-  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
-  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
-  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
-                                 ///<  DIMM#  Select Signal
-                                 ///<  0      MA0_CS_L[0, 1]
-                                 ///<  1      MB0_CS_L[0, 1]
-                                 ///<  2      MA1_CS_L[0, 1]
-                                 ///<  3      MB1_CS_L[0, 1]
-                                 ///<  4      MA2_CS_L[0, 1]
-                                 ///<  5      MB2_CS_L[0, 1]
-                                 ///<  6      MA3_CS_L[0, 1]
-                                 ///<  7      MB3_CS_L[0, 1]
-
-  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
-  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
-  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
-  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
-                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
-  OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
-                                 ///<
-  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
-  OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
-  OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
-  OUT UINT8   Loads;             ///< Number of devices loading bus
-  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
-  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
-  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
-                                 ///< FALSE = 1T
-                                 ///< TRUE = 2T
-  ///< The following pointers will be pointed to dynamically allocated buffers.
-  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
-  ///< Example: If DIMM and Byte based training, then
-  ///< XX is a value in Hex
-  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
-  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
-  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
-  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
-  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
-  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
-  OUT UINT8   *WrDatDlys;       ///< Write Data delays
-  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
-  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
-  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
-  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
-  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
-  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
-  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
-  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
-  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
-  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
-  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
-  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
-  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
-  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
-  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
-  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
-  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
-  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
-  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
-  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
-  OUT UINT8   Pattern;            ///< Current pattern
-  OUT UINT8   DqsDelay;           ///< Current DQS delay value
-  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
-  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
-  OUT UINT16  DctMaxRdLat;        ///< Max Read Latency (ns) for the DCT
-  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
-  OUT UINT8   MaxCh;              ///< Max number of CH in system
-  OUT UINT8   Dct;                ///< Dct pointer
-  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
-  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
-
-  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
-  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
-  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
-  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
-  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
-  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
-
-  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
-  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
-  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
-  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
-  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
-  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
-  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
-  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
-
-  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
-  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
-  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
-  OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
-  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
-  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
-  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
-  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
-  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
-  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
-  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
-  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
-  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
-  OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
-  OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
-  OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
-
-  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
-                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
-                                  ///<  base on this array to disable unused MemClk to save power.
-                                  ///<
-                                  ///<  The array must have 8 entries. Each entry, which associates with
-                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
-                                  ///<    Example:
-                                  ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
-                                  ///<    is like below:
-                                  ///<         Bit AM3/S1g3 pin name
-                                  ///<         0   M[B,A]_CLK_H/L[0]
-                                  ///<         1   M[B,A]_CLK_H/L[1]
-                                  ///<         2   M[B,A]_CLK_H/L[2]
-                                  ///<         3   M[B,A]_CLK_H/L[3]
-                                  ///<         4   M[B,A]_CLK_H/L[4]
-                                  ///<         5   M[B,A]_CLK_H/L[5]
-                                  ///<         6   M[B,A]_CLK_H/L[6]
-                                  ///<         7   M[B,A]_CLK_H/L[7]
-                                  ///<    And platform has the following routing:
-                                  ///<         CS0   M[B,A]_CLK_H/L[4]
-                                  ///<         CS1   M[B,A]_CLK_H/L[2]
-                                  ///<         CS2   M[B,A]_CLK_H/L[3]
-                                  ///<         CS3   M[B,A]_CLK_H/L[5]
-                                  ///<    Then MemClkDisMap should be pointed to the following array:
-                                  ///<               CLK_2 CLK_3 CLK_4 CLK_5
-                                  ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
-                                  ///<  Each entry of the array is the bitmask of 8 chip selects.
-
-  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
-                                  ///<  the routing of CKE pins to the DIMMs' ranks.
-                                  ///<  The array must have 2 entries. Each entry, which associates with
-                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
-                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
-
-  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
-                                  ///<  the routing of ODT pins to the DIMMs' ranks.
-                                  ///<  The array must have 4 entries. Each entry, which associates with
-                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
-                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
-
-  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
-                                  ///<  the routing of chip select pins to the DIMMs' ranks.
-                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
-                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
-
-  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
-
-  OUT UINT8   Reserved[100];      ///< Reserved
-} CH_DEF_STRUCT;
-
-///
-/// DCT Channel Timing Parameters.
-/// This data structure sets timings that are specific to the channel.
-///
-typedef struct _CH_TIMING_STRUCT {
-  OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
-  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
-  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
-  OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
-  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
-  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
-  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
-  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
-  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
-  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
-  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
-  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
-  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
-  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
-  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
-
-  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
-  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
-  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
-  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
-  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
-  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
-  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
-  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
-  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
-  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
-  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
-                                  ///<  400 (MHz)
-                                  ///<  533 (MHz)
-                                  ///<  667 (MHz)
-                                  ///<  800 (MHz)
-                                  ///<  and so on...
-  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
-  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
-  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
-  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
-  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
-  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
-  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
-  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
-  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
-  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
-  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
-                                  ///<  0 = 75ns (for 256Mb devs)
-                                  ///<  1 = 105ns (for 512Mb devs)
-                                  ///<  2 = 127.5ns (for 1Gb devs)
-                                  ///<  3 = 195ns (for 2Gb devs)
-                                  ///<  4 = 327.5ns (for 4Gb devs)
-  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
-  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
-  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
-  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
-                                  ///<
-  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
-                                  ///< FALSE = 1T
-                                  ///< TRUE = 2T
-  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
-  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
-  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
-  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
-  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
-  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
-  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
-  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
-  OUT UINT16  MaxRdLat;           ///< Max Read Latency
-  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
-  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
-} CH_TIMING_STRUCT;
-
-///
-/// Data for each DCT.
-/// This data structure defines data used to configure each DRAM controller.
-///
-typedef struct _DCT_STRUCT {
-  OUT UINT8   Dct;                ///< Current Dct
-  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
-  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
-  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
-} DCT_STRUCT;
-
-
-///
-/// Data Structure defining each Die.
-/// This data structure contains information that is used to configure each Die.
-///
-typedef struct _DIE_STRUCT {
-
-  /// Advanced:
-
-  OUT UINT8   NodeId;              ///< Node ID of current controller
-  OUT UINT8   SocketId;            ///< Socket ID of this Die
-  OUT UINT8   DieId;               ///< ID of this die relative to the socket
-  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
-  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
-                                   ///<  0x0 = AGESA_SUCCESS
-                                   ///<  0x1 = AGESA_UNSUPPORTED
-                                   ///<  0x2 = AGESA_BOUNDS_CHK
-                                   ///<  0x3 = AGESA_ALERT
-                                   ///<  0x4 = AGESA_WARNING
-                                   ///<  0x5 = AGESA_ERROR
-                                   ///<  0x6 = AGESA_CRITICAL
-                                   ///<  0x7 = AGESA_FATAL
-                                   ///<
-  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
-                                   ///<
-  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
-                                   ///<
-  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
-                                   ///<
-  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
-                                   ///<
-  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
-                                   ///<
-  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
-                                   ///<
-  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
-                                   ///<   DIMM#  Select Signal
-                                   ///<   0      MA0_CS_L[0, 1]
-                                   ///<   1      MB0_CS_L[0, 1]
-                                   ///<   2      MA1_CS_L[0, 1]
-                                   ///<   3      MB1_CS_L[0, 1]
-                                   ///<   4      MA2_CS_L[0, 1]
-                                   ///<   5      MB2_CS_L[0, 1]
-                                   ///<   6      MA3_CS_L[0, 1]
-                                   ///<   7      MB3_CS_L[0, 1]
-                                   ///<
-  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
-  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
-  OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
-  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
-  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
-                                   ///<
-  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
-  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
-                                   ///<  0 in any bit field indicates Channel 0
-                                   ///<  1 in any bit field indicates Channel 1
-  OUT UINT8   Dct;                 ///<  Need to be removed
-                                   ///<  DCT pointer
-  OUT BOOLEAN GangedMode;          ///< Ganged mode
-                                   ///<  0 = disabled
-                                   ///<  1 = enabled
-  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
-                                   ///<
-  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
-                                   ///<
-  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
-                                   ///<
-  OUT UINT8   MLoad;               ///< Need to be removed
-                                   ///< Number of devices loading MAA bus
-                                   ///<
-  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
-                                   ///<
-  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
-                                   ///<
-  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
-                                   ///<
-  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
-  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
-  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
-  OUT UINT8   Reserved[16];        ///< Reserved
-} DIE_STRUCT;
-
-/**********************************************************************
- * S3 Support structure
- **********************************************************************/
-/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-typedef struct {
-     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
-     OUT   UINT16 Version;             ///< S3 Params version number
-  IN OUT   UINT32 Flags;               ///< Indicates operation
-  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
-  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
-  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
-  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
-} AMD_S3_PARAMS;
-
-///===============================================================================
-/// MEM_PARAMETER_STRUCT
-/// This data structure is used to pass wrapper parameters to the memory configuration code
-///
-typedef struct _MEM_PARAMETER_STRUCT {
-
-  // Basic (Return parameters)
-  // (This section contains the outbound parameters from the memory init code)
-
-  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
-                                  ///<
-  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
-                                  ///<
-  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
-                                  ///<
-  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
-                                  ///<
-
-  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
-                                  ///< 0 = 1.5v
-                                  ///< 1 = 1.35v
-                                  ///< 2 = 1.2v
-                                  ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
-                                  ///<        from the system.
-                                  ///<
-
-  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
-
-  //  Advanced (Optional parameters)
-  //  Optional (all defaults values will be initialized by the
-  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
-  //  to the IBV/OEM to change the defaults after initialization
-  //  but prior to the main entry to the memory code):
-
-  // Memory Map/Mgt.
-
-  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
-                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
-                                   ///<
-  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
-                                   ///<  FALSE = disable
-                                   ///<  TRUE  = enable
-
-
-  // Dram Timing
-
-  IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
-                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
-
-  IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
-                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
-
-
-  // Dram Configuration
-
-  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
-                                   ///<  - FALSE =disable (default)
-                                   ///<  - TRUE = enable
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
-
-  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
-                                   ///<   - FALSE = disable (default)
-                                   ///<   - TRUE = enable
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
-
-  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
-                                   ///<   - FALSE = disable (default)
-                                   ///<   - TRUE = enable
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
-  // ECC
-
-  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
-                                   ///<   - FALSE = disable (default)
-                                   ///<   - TRUE = enable
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
-  // Dram Power
-
-  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
-                                   ///<   - FALSE =disable (default)
-                                   ///<   - TRUE =enable
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
-
-  // Online Spare
-
-  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
-                                   ///<  - FALSE = disable Spare (default)
-                                   ///<  - TRUE = enable Spare
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
-
-  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
-
-  IN PSO_TABLE *PlatformMemoryConfiguration;
-                                   ///< A table that contains platform specific settings.
-                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
-                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
-                                   ///< contains default conservative settings. Platform BIOS can either tweak
-                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
-                                   ///<
-  IN BOOLEAN EnableParity;         ///< Parity control.
-                                   ///<  - TRUE = enable
-                                   ///<  - FALSE = disable (default)
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
-
-  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
-                                   ///<  - FALSE = disable
-                                   ///<  - TRUE = enable  (default)
-                                   ///<
-                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
-
-                                   ///<
-
-  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
-                                   ///<  - FALSE = disable
-                                   ///<  - TRUE = enable  (default)
-                                   ///<
-
-  // Uma Configuration
-
-  IN UMA_MODE UmaMode;             ///<  Uma Mode
-                                   ///<  0 = None
-                                   ///<  1 = Specified
-                                   ///<  2 = Auto
-  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
-                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
-                                   ///<
-  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
-                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
-                                   ///<
-
-  /// Memory Restore Feature
-
-  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
-                                   ///<   FALSE = perform memory init as normal (AMD default)
-                                   ///<   TRUE = restore memory context and skip training. This requires
-                                   ///<          MemContext is valid before AmdInitPost
-                                   ///<
-  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
-                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
-                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
-                                   ///<           expected to call S3Save later in POST if it wants to
-                                   ///<           use memory context restore feature.
-                                   ///<
-  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
-                                   ///< save and restore for memory context restore feature to work.
-                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
-                                   ///< may save only S3 block and uses it for both S3 resume and
-                                   ///< memory context restore.
-                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
-                                   ///<    before AmdInitPost.
-                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
-                                   ///<    right after AmdInitPost.
-                                   ///<
-} MEM_PARAMETER_STRUCT;
-
-
-///
-/// Function definition.
-/// This data structure passes function pointers to the memory configuration code.
-/// The wrapper can use this structure with customized versions.
-///
-typedef struct _MEM_FUNCTION_STRUCT {
-
-  // PUBLIC required Internal functions
-
-  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
-  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
-
-  // PUBLIC optional functions
-
-  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
-  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
-  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
-  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
-  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
-  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
-  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
-  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
-  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
-  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
-  IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);                ///< NB code for LRDIMMs
-
-  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
-} MEM_FUNCTION_STRUCT;
-
-///
-/// Socket Structure
-///
-///
-typedef struct _MEM_SOCKET_STRUCT {
-  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
-
-  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
-} MEM_SOCKET_STRUCT;
-
-///
-/// Contains all data relevant to Memory Initialization.
-///
-typedef struct _MEM_DATA_STRUCT {
-  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
-
-  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
-
-  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
-
-  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
-
-  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
-
-
-  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
-                                   ///< SocketList is a shortcut for IBVs to retrieve training
-                                   ///< and timing data for each channel indexed by socket/channel,
-                                   ///< eliminating their need to parse die/dct/channel etc.
-                                   ///< It contains pointers to the populated data structures for
-                                   ///< each channel and skips the channel structures that are
-                                   ///< unpopulated. In the case of channels sharing the same DCT,
-                                   ///< the pTimings pointers will point to the same DCT Timing data.
-
-  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
-  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
-
-  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
-
-  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
-
-  IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
-
-  OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
-
-} MEM_DATA_STRUCT;
-
-///
-/// Uma Structure
-///
-///
-typedef struct _UMA_INFO {
-  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
-  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
-  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
-  OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
-  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
-  OUT UINT8 Reserved[3];       ///< Reserved for future usage
-} UMA_INFO;
-
-//  AGESA MEMORY ERRORS
-
-// AGESA_ALERT Memory Errors
-#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
-                                                       ///< cannot be applied to current configurations.
-#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
-#define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
-
-// AGESA_ERROR Memory Errors
-#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
-#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
-#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
-#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
-#define MEM_ERROR_ECC_DIS 0x04010400                  ///< ECC has been disabled as a result of an internal issue
-#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
-#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
-#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
-#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
-#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
-#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
-#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
-#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
-#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
-#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
-#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
-#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
-#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
-#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
-#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
-#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
-#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
-#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
-#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
-#define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
-#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
-#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
-
-// AGESA_WARNING Memory Errors
-#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
-#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
-#define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
-#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
-#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
-                                                        ///< bank interleaving, or bank swizzle is enabled.
-#define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
-#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
-
-// AGESA_FATAL Memory Errors
-#define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
-#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
-#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
-#define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
-#define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
-#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
-#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
-
-// AGESA_CRITICAL Memory Errors
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
-#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
-
-
-
-/*----------------------------------------------------------------------------
- *
- *                END OF MEMORY-SPECIFIC DATA STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-
-/*----------------------------------------------------------------------------
- *
- *                    CPU RELATED DEFINITIONS
- *
- *----------------------------------------------------------------------------
- */
-
-// CPU Event definitions.
-
-// Defines used to filter CPU events based on functional blocks
-#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
-#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
-
-//================================================================
-// CPU General events
-//    Heap allocation                     (AppFunction =      01h)
-#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
-#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
-#define CPU_ERROR_HEAP_IS_FULL                          0x08020100
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
-//    BrandId                             (AppFunction =      02h)
-#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
-//    Micro code patch                    (AppFunction =      03h)
-#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
-//    Power management                    (AppFunction =      04h)
-#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
-#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
-#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
-#define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
-//    BIST                                (AppFunction =      05h)
-#define CPU_EVENT_BIST_ERROR                            0x08000500
-
-//=================================================================
-// CPU Feature events
-//    Execution cache                     (AppFunction =      21h)
-//        AGESA_CACHE_SIZE_REDUCED                            2101
-//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
-//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
-//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
-//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
-//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
-//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
-#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
-//    Core Leveling                       (AppFunction =      22h)
-#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
-//    HT Assist                           (AppFunction =      23h)
-#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
-
-// CPU Build Configuration structures and definitions
-
-/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
-typedef struct {
-  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
-  IN  UINT64 MsrData;     ///< MTRR Settings
-} AP_MTRR_SETTINGS;
-
-#define AMD_AP_MTRR_FIX64k_00000    0x00000250
-#define AMD_AP_MTRR_FIX16k_80000    0x00000258
-#define AMD_AP_MTRR_FIX16k_A0000    0x00000259
-#define AMD_AP_MTRR_FIX4k_C0000     0x00000268
-#define AMD_AP_MTRR_FIX4k_C8000     0x00000269
-#define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
-#define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
-#define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
-#define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
-#define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
-#define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
-#define CPU_LIST_TERMINAL           0xFFFFFFFF
-
-/************************************************************************
- *
- *  AGESA interface Call-Out function parameter structures
- *
- ***********************************************************************/
-
-/// Parameters structure for interface call-out AgesaAllocateBuffer
-typedef struct {
-  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
-  IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
-  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
-  OUT       VOID                *BufferPointer; ///< location of the created buffer
-} AGESA_BUFFER_PARAMS;
-
-/// Parameters structure for interface call-out AgesaRunCodeOnAp
-typedef struct {
-  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
-  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
-  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
-  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
-} AP_EXE_PARAMS;
-
-/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-typedef struct {
-  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
-  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
-  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
-  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
-  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
-  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
-} AGESA_READ_SPD_PARAMS;
-
-/// Buffer Handles
-typedef enum {
-  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
-  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
-  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
-  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
-  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
-  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
-  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
-  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
-  AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
-  AMD_ACPI_ALIB_BUFFER_HANDLE                   ///< Assign 0x000D009 buffer handle to ALIB SSDT table
-} AMD_BUFFER_HANDLE;
-/************************************************************************
- *
- *  AGESA interface Call-Out function prototypes
- *
- ***********************************************************************/
-
-VOID
-AgesaDoReset (
-  IN        UINTN               ResetType,
-  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
-  );
-
-AGESA_STATUS
-AgesaAllocateBuffer (
-  IN      UINTN                 FcnData,
-  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
-  );
-
-AGESA_STATUS
-AgesaDeallocateBuffer (
-  IN      UINTN                 FcnData,
-  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
-  );
-
-AGESA_STATUS
-AgesaLocateBuffer (
-  IN      UINTN                 FcnData,
-  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
-  );
-
-AGESA_STATUS
-AgesaReadSpd (
-  IN        UINTN                 FcnData,
-  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
-  );
-
-AGESA_STATUS
-AgesaReadSpdRecovery (
-  IN        UINTN                 FcnData,
-  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
-  );
-
-AGESA_STATUS
-AgesaHookBeforeDramInitRecovery (
-  IN       UINTN           FcnData,
-  IN OUT   MEM_DATA_STRUCT *MemData
-  );
-
-AGESA_STATUS
-AgesaRunFcnOnAp (
-  IN        UINTN               ApicIdOfCore,
-  IN        AP_EXE_PARAMS       *LaunchApParams
-  );
-
-AGESA_STATUS
-AgesaHookBeforeDramInit (
-  IN        UINTN               FcnData,
-  IN OUT    MEM_DATA_STRUCT     *MemData
-  );
-
-AGESA_STATUS
-AgesaHookBeforeDQSTraining (
-  IN        UINTN               FcnData,
-  IN OUT    MEM_DATA_STRUCT     *MemData
-  );
-
-AGESA_STATUS
-AgesaHookBeforeExitSelfRefresh (
-  IN        UINTN               FcnData,
-  IN OUT    MEM_DATA_STRUCT     *MemData
-  );
-
-AGESA_STATUS
-AgesaPcieSlotResetControl (
-  IN      UINTN                 FcnData,
-  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
- );
-
-/************************************************************************
- *
- *  AGESA interface structure definition and function prototypes
- *
- ***********************************************************************/
-
-/**********************************************************************
- * Platform Configuration:  The parameters in boot branch function
- **********************************************************************/
-
-///  The possible platform control flow settings.
-typedef enum  {
-  Nfcm,                                          ///< Normal Flow Control Mode.
-  UmaDr,                                         ///< UMA using Display Refresh flow control.
-  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
-  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
-  Iommu,                                         ///< An IOMMU is in use in the system.
-  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
-} PLATFORM_CONTROL_FLOW;
-
-///  Platform Deemphasis Levels.
-///
-/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
-/// set based on the level of the far transmitter.
-typedef enum {
-  DeemphasisLevelNone,                           ///< No Deemphasis.
-  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
-  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
-  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
-  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
-  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
-  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
-  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
-  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
-  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
-  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
-  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
-  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
-  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
-  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
-  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
-} PLATFORM_DEEMPHASIS_LEVEL;
-
-///  Provide Deemphasis Levels for HT Links.
-///
-///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
-///  is in the inclusive range HighFreq:LoFreq.
-///  AGESA does not set deemphasis in IO devices, only in processors.
-
-typedef struct {
-  // Match fields
-  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
-  IN       UINT8 Link;                                          ///< The Link on this Processor.
-  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
-  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
-  // Value fields
-  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
-  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
-} CPU_HT_DEEMPHASIS_LEVEL;
-
-///  The possible platform power policy settings.
-typedef enum  {
-  Performance,                                   ///< Optimize for performance.
-  BatteryLife,                                   ///< Optimize for battery life.
-  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
-} PLATFORM_POWER_POLICY;
-
-///  Platform performance settings for optimized settings.
-///  Several configuration settings for the processor depend upon other parts and
-///  general designer choices for the system. The determination of these data points
-///  is not standard for all platforms, so the host environment needs to provide these
-///  to specify how the system is to be configured.
-typedef struct {
-  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
-                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
-  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
-                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
-  IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
-                                                       ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
-  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
-                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
-  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
-                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
-  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
-                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
-} PERFORMANCE_PROFILE;
-
-///  Platform settings that describe the voltage regulator modules of the system.
-///  Many power management settings are dependent upon the characteristics of the
-///  on-board voltage regulator module (VRM).  The host environment needs to provide
-///  these to specify how the system is to be configured.
-typedef struct {
-  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
-  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
-  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
-  IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
-  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
-  IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
-                                                   ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
-                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
-} PLATFORM_VRM_CONFIGURATION;
-
-///  The VRM types to characterize.
-typedef enum  {
-  CoreVrm,                                       ///< VDD plane.
-  NbVrm,                                         ///< VDDNB plane.
-  MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
-} PLATFORM_VRM_TYPE;
-
-
-/// Build Option/Configuration Boolean Structure.
-typedef struct {
-  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
-
-  //Build Option Area
-  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
-  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
-  IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
-  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
-  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
-  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
-  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
-  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
-  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
-  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
-  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
-  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
-  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
-  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
-  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
-  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
-  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
-  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
-
-  //Build Configuration Area
-  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
-  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
-  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
-  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
-  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
-  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
-  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
-  IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
-  IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
-  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
-  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
-  IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
-  IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
-  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
-  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
-  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
-
-  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
-  IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
-
-  IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
-  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
-  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
-  IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
-  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
-  IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
-  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
-  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
-  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
-  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
-  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
-  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
-  IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
-  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
-  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
-  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
-  IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
-  IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
-  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
-  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
-  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
-  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
-  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
-  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
-  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
-  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
-  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
-  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
-  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
-  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
-  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
-  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
-  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
-  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
-  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
-  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
-  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
-  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
-  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
-  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
-  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
-  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
-  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
-  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
-  IN UINT8   CfgAbmSupport;                       ///< Abm Support
-  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
-  IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
-  IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
-  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
-  IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
-  IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
-  IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
-                                                  ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
-  IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
-  IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
-                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
-  IN BOOLEAN Reserved;                            ///< reserved...
-} BUILD_OPT_CFG;
-
-///  A structure containing platform specific operational characteristics. This
-///  structure is initially populated by the initializer with a copy of the same
-///  structure that was created at build time using the build configuration controls.
-typedef struct _PLATFORM_CONFIGURATION {
-  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
-  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
-                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
-  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
-                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
-  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
-  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
-  IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
-  IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
-  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
-  IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
-                                                      ///< If CStateMode is CStateModeC6, this item is reserved
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
-  IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
-                                                      ///< can be used to allow the CPU to enter Cstates.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
-  IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
-  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
-  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
-  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
-  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
-  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
-  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
-  IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
-                                                      ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
-  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
-                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
-  IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
-  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
-                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
-  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
-                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
-  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
-                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
-  IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
-                                                      ///< essentially it enables function 1 of graphics device.
-                                                      ///< @li 0 = HD Audio disable
-                                                      ///< @li 1 = HD Audio enable
-                                                      ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
-  IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
-                                                      ///< characteristic specific to display panel which used by platform design.
-                                                      ///< @li 0 = ABM support disabled
-                                                      ///< @li 1 = ABM support enabled
-                                                      ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
-  IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
-                                                      ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
-  IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
-                                                      ///< If equal to 0 backlight not controlled by iGPU
-                                                      ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
-} PLATFORM_CONFIGURATION;
-
-
-/**********************************************************************
- * Structures for: AmdInitLate
- **********************************************************************/
-#define PROC_VERSION_LENGTH 48
-#define MAX_DIMMS_PER_SOCKET 16
-
-/*  Interface Parameter Structures  */
-/// DMI Type4 - Processor ID
-typedef struct {
-  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
-  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
-} TYPE4_PROC_ID;
-
-/// DMI Type 4 - Processor information
-typedef struct {
-  OUT UINT8                     T4ProcType;             ///< CPU Type
-  OUT UINT8                     T4ProcFamily;           ///< Family 1
-  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
-  OUT UINT8                     T4Voltage;              ///< Voltage
-  OUT UINT16                    T4ExternalClock;        ///< External clock
-  OUT UINT16                    T4MaxSpeed;             ///< Max speed
-  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
-  OUT UINT8                     T4Status;               ///< Status
-  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
-  OUT UINT8                     T4CoreCount;            ///< Core count
-  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
-  OUT UINT8                     T4ThreadCount;          ///< Thread count
-  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
-  OUT UINT16                    T4ProcFamily2;          ///< Family 2
-  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
-} TYPE4_DMI_INFO;
-
-/// DMI Type 7 - Cache information
-typedef struct _TYPE7_DMI_INFO {
-  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
-  OUT UINT16                    T7MaxCacheSize;         ///< Max size
-  OUT UINT16                    T7InstallSize;          ///< Install size
-  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
-  OUT UINT16                    T7CurrentSramType;      ///< Current type
-  OUT UINT8                     T7CacheSpeed;           ///< Speed
-  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
-  OUT UINT8                     T7SystemCacheType;      ///< Cache type
-  OUT UINT8                     T7Associativity;        ///< Associativity
-} TYPE7_DMI_INFO;
-
-/// DMI Type 16 offset 04h - Location
-typedef enum {
-  OtherLocation = 0x01,                                 ///< Assign 01 to Other
-  UnknownLocation,                                      ///< Assign 02 to Unknown
-  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
-  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
-  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
-  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
-  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
-  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
-  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
-  NuBus,                                                ///< Assign 0A to NuBus
-  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
-  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
-  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
-  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
-} DMI_T16_LOCATION;
-
-/// DMI Type 16 offset 05h - Memory Error Correction
-typedef enum {
-  OtherUse = 0x01,                                      ///< Assign 01 to Other
-  UnknownUse,                                           ///< Assign 02 to Unknown
-  SystemMemory,                                         ///< Assign 03 to system memory
-  VideoMemory,                                          ///< Assign 04 to video memory
-  FlashMemory,                                          ///< Assign 05 to flash memory
-  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
-  CacheMemory                                           ///< Assign 07 to cache memory
-} DMI_T16_USE;
-
-/// DMI Type 16 offset 07h - Maximum Capacity
-typedef enum {
-  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
-  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
-  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
-  Dmi16Parity,                                          ///< Assign 04 to parity
-  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
-  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
-  Dmi16Crc                                              ///< Assign 07 to CRC
-} DMI_T16_ERROR_CORRECTION;
-
-/// DMI Type 16 - Physical Memory Array
-typedef struct {
-  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
-                                                        ///< whether on the system board or an add-in board.
-  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
-                                                        ///< is used.
-  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
-                                                        ///< detection method supported by this memory array.
-  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
-                                                        ///< for the array.
-  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
-                                                        ///< for memory devices in this array.
-} TYPE16_DMI_INFO;
-
-/// DMI Type 17 offset 0Eh - Form Factor
-typedef enum {
-  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
-  UnknowFormFactor,                                     ///< Assign 02 to Unknown
-  SimmFormFactor,                                       ///< Assign 03 to SIMM
-  SipFormFactor,                                        ///< Assign 04 to SIP
-  ChipFormFactor,                                       ///< Assign 05 to Chip
-  DipFormFactor,                                        ///< Assign 06 to DIP
-  ZipFormFactor,                                        ///< Assign 07 to ZIP
-  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
-  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
-  TsopFormFactor,                                       ///< Assign 10 to TSOP
-  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
-  RimmFormFactor,                                       ///< Assign 12 to RIMM
-  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
-  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
-  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
-} DMI_T17_FORM_FACTOR;
-
-/// DMI Type 17 offset 12h - Memory Type
-typedef enum {
-  OtherMemType = 0x01,                                  ///< Assign 01 to Other
-  UnknownMemType,                                       ///< Assign 02 to Unknown
-  DramMemType,                                          ///< Assign 03 to DRAM
-  EdramMemType,                                         ///< Assign 04 to EDRAM
-  VramMemType,                                          ///< Assign 05 to VRAM
-  SramMemType,                                          ///< Assign 06 to SRAM
-  RamMemType,                                           ///< Assign 07 to RAM
-  RomMemType,                                           ///< Assign 08 to ROM
-  FlashMemType,                                         ///< Assign 09 to Flash
-  EepromMemType,                                        ///< Assign 10 to EEPROM
-  FepromMemType,                                        ///< Assign 11 to FEPROM
-  EpromMemType,                                         ///< Assign 12 to EPROM
-  CdramMemType,                                         ///< Assign 13 to CDRAM
-  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
-  SdramMemType,                                         ///< Assign 15 to SDRAM
-  SgramMemType,                                         ///< Assign 16 to SGRAM
-  RdramMemType,                                         ///< Assign 17 to RDRAM
-  DdrMemType,                                           ///< Assign 18 to DDR
-  Ddr2MemType,                                          ///< Assign 19 to DDR2
-  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
-  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
-  Fbd2MemType                                           ///< Assign 25 to FBD2
-} DMI_T17_MEMORY_TYPE;
-
-/// DMI Type 17 offset 13h - Type Detail
-typedef struct {
-  OUT UINT16                    Reserved1:1;            ///< Reserved
-  OUT UINT16                    Other:1;                ///< Other
-  OUT UINT16                    Unknown:1;              ///< Unknown
-  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
-  OUT UINT16                    StaticColumn:1;         ///< Static column
-  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
-  OUT UINT16                    Rambus:1;               ///< RAMBUS
-  OUT UINT16                    Synchronous:1;          ///< Synchronous
-  OUT UINT16                    Cmos:1;                 ///< CMOS
-  OUT UINT16                    Edo:1;                  ///< EDO
-  OUT UINT16                    WindowDram:1;           ///< Window DRAM
-  OUT UINT16                    CacheDram:1;            ///< Cache Dram
-  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
-  OUT UINT16                    Reserved2:3;            ///< Reserved
-} DMI_T17_TYPE_DETAIL;
-
-/// DMI Type 17 - Memory Device
-typedef struct {
-  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
-  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
-  OUT UINT16                    MemorySize;             ///< The size of the memory device.
-  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
-  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
-                                                        ///< Memory Devices that must be populated with all devices of
-                                                        ///< the same type and size, and the set to which this device belongs.
-  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
-  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
-  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
-  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
-  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
-  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
-  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
-  OUT CHAR8                     PartNumber[19];         ///< Part Number.
-  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
-  OUT UINT32                    ExtSize;                ///< Extended Size.
-  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
-} TYPE17_DMI_INFO;
-
-/// Memory DMI Type 17 and 20 - for memory use
-typedef struct {
-  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
-  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
-  OUT UINT16                    MemorySize;             ///< The size of the memory device.
-  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
-  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
-  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
-  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
-  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
-  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
-  OUT UINT8                     PartNumber[18];         ///< Part Number.
-  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
-  OUT UINT32                    ExtSize;                ///< Extended Size.
-  OUT UINT8                     Socket:3;               ///< Socket ID
-  OUT UINT8                     Channel:2;              ///< Channel ID
-  OUT UINT8                     Dimm:2;                 ///< DIMM ID
-  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
-  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
-                                                        ///< of memory mapped to the referenced Memory Device.
-  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
-                                                        ///< the Memory Device structure to which this address
-                                                        ///< range is mapped.
-  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
-} MEM_DMI_INFO;
-
-/// DMI Type 19 - Memory Array Mapped Address
-typedef struct {
-  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
-                                                        ///< of a range of memory mapped to the
-                                                        ///< specified physical memory array.
-  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
-                                                        ///< last kilobyte of a range of addresses
-                                                        ///< mapped to the specified physical memory array.
-  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
-                                                        ///< with the physical memory array to which this
-                                                        ///< address range is mapped.
-  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
-                                                        ///< form a single row of memory for the address
-                                                        ///< partition defined by this structure.
-} TYPE19_DMI_INFO;
-
-///DMI Type 20 - Memory Device Mapped Address
-typedef struct {
-  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
-                                                        ///< of memory mapped to the referenced Memory Device.
-  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
-                                                        ///< the Memory Device structure to which this address
-                                                        ///< range is mapped.
-  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
-                                                        ///< the Memory Device structure to which this address
-                                                        ///< range is mapped.
-  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
-                                                        ///< with the Memory Array Mapped Address structure to
-                                                        ///< which this device address range is mapped.
-  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
-                                                        ///< Device in a row of the address partition.
-  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
-                                                        ///< an interleave.
-  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
-                                                        ///< referenced Memory Device that are accessed in a
-                                                        ///< single interleaved transfer.
-} TYPE20_DMI_INFO;
-
-/// Collection of pointers to the DMI records
-typedef struct {
-  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
-  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
-  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
-  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
-  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
-  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
-  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
-  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
-} DMI_INFO;
-
-/**********************************************************************
- * Interface call:  AllocateExecutionCache
- **********************************************************************/
-#define MAX_CACHE_REGIONS    3
-
-/// AllocateExecutionCache sub param structure for cached memory region
-typedef struct {
-  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
-  IN OUT   UINT32               ExeCacheSize;           ///< Size
-} EXECUTION_CACHE_REGION;
-
-/**********************************************************************
- * Interface call:  AmdGetAvailableExeCacheSize
- **********************************************************************/
-/// Get available Cache remain
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
-     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
-} AMD_GET_EXE_SIZE_PARAMS;
-
-AGESA_STATUS
-AmdGetAvailableExeCacheSize (
-  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
-  );
-
-/// Selection type for core leveling
-typedef enum {
-  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
-  CORE_LEVEL_TWO,               ///< Level to 2 cores
-  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
-  CORE_LEVEL_NONE,              ///< Do no leveling
-  CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
-  CORE_LEVEL_ONE,               ///< Level to 1 core
-  CORE_LEVEL_THREE,             ///< Level to 3 cores
-  CORE_LEVEL_FOUR,              ///< Level to 4 cores
-  CORE_LEVEL_FIVE,              ///< Level to 5 cores
-  CORE_LEVEL_SIX,               ///< Level to 6 cores
-  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
-  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
-  CORE_LEVEL_NINE,              ///< Level to 9 cores
-  CORE_LEVEL_TEN,               ///< Level to 10 cores
-  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
-  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
-  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
-  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
-  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
-  CoreLevelModeMax              ///< Used for bounds checking
-} CORE_LEVELING_TYPE;
-
-
-
-
-
-/************************************************************************
- *
- *  AGESA Basic Level interface structure definition and function prototypes
- *
- ***********************************************************************/
-
-/**********************************************************************
- * Interface call:  AmdCreateStruct
- **********************************************************************/
-AGESA_STATUS
-AmdCreateStruct (
-  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
-  );
-
-/**********************************************************************
- * Interface call:  AmdReleaseStruct
- **********************************************************************/
-AGESA_STATUS
-AmdReleaseStruct (
-  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
-  );
-
-/**********************************************************************
- * Interface call:  AmdInitReset
- **********************************************************************/
-/// AmdInitReset param structure
-typedef struct {
-  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
-  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
-  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
-} AMD_RESET_PARAMS;
-
-AGESA_STATUS
-AmdInitReset (
-  IN OUT   AMD_RESET_PARAMS     *ResetParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdInitEarly
- **********************************************************************/
-/// InitEarly param structure
-///
-/// Provide defaults or customizations to each service performed in AmdInitEarly.
-///
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
-  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
-  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
-} AMD_EARLY_PARAMS;
-
-AGESA_STATUS
-AmdInitEarly (
-  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdInitPost
- **********************************************************************/
-/// AmdInitPost param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
-} AMD_POST_PARAMS;
-
-AGESA_STATUS
-AmdInitPost (
-  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdInitEnv
- **********************************************************************/
-/// AmdInitEnv param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
-  IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
-} AMD_ENV_PARAMS;
-
-AGESA_STATUS
-AmdInitEnv (
-  IN OUT   AMD_ENV_PARAMS       *EnvParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdInitMid
- **********************************************************************/
-/// AmdInitMid param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-} AMD_MID_PARAMS;
-
-AGESA_STATUS
-AmdInitMid (
-  IN OUT   AMD_MID_PARAMS       *MidParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdInitLate
- **********************************************************************/
-/// AmdInitLate param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
-     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
-     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
-     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
-     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
-     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
-     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
-     OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
-} AMD_LATE_PARAMS;
-
-AGESA_STATUS
-AmdInitLate (
-  IN OUT   AMD_LATE_PARAMS      *LateParams
-  );
-
-/**********************************************************************
- * Interface call:  AmdInitRecovery
- **********************************************************************/
-/// CPU Recovery Parameters
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-} AMD_CPU_RECOVERY_PARAMS;
-
-/// AmdInitRecovery param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
-  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
-  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
-  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
-} AMD_RECOVERY_PARAMS;
-
-AGESA_STATUS
-AmdInitRecovery (
-  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
-  );
-
-/**********************************************************************
- * Interface call:  AmdInitResume
- **********************************************************************/
-/// AmdInitResume param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
-  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
-} AMD_RESUME_PARAMS;
-
-AGESA_STATUS
-AmdInitResume (
-  IN       AMD_RESUME_PARAMS    *ResumeParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdS3LateRestore
- **********************************************************************/
-/// AmdS3LateRestore param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
-} AMD_S3LATE_PARAMS;
-
-AGESA_STATUS
-AmdS3LateRestore (
-  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdS3Save
- **********************************************************************/
-/// AmdS3Save param structure
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
-  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
-     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
-} AMD_S3SAVE_PARAMS;
-
-AGESA_STATUS
-AmdS3Save (
-  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
-  );
-
-
-/**********************************************************************
- * Interface call:  AmdLateRunApTask
- **********************************************************************/
-/**
- * Entry point for AP tasking.
- */
-AGESA_STATUS
-AmdLateRunApTask (
-  IN       AP_EXE_PARAMS  *AmdApExeParams
-);
-
-//
-// General Services API
-//
-
-/**********************************************************************
- * Interface service call:  AmdGetApicId
- **********************************************************************/
-/// Request the APIC ID of a particular core.
-
-typedef struct {
-  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
-  IN       UINT8             Socket;           ///< The Core's Socket.
-  IN       UINT8             Core;             ///< The Core id.
-     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
-     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
-} AMD_APIC_PARAMS;
-
-/**
- * Get a specified Core's APIC ID.
- */
-AGESA_STATUS
-AmdGetApicId (
-  IN OUT AMD_APIC_PARAMS *AmdParamApic
-);
-
-/**********************************************************************
- * Interface service call:  AmdGetPciAddress
- **********************************************************************/
-/// Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-typedef struct {
-  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
-  IN       UINT8             Socket;           ///< The Processor's socket
-  IN       UINT8             Module;           ///< The Module in that Processor
-     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
-     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
-} AMD_GET_PCI_PARAMS;
-
-/**
- * Get Processor Module's PCI Config Space address.
- */
-AGESA_STATUS
-AmdGetPciAddress (
-  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
-);
-
-/**********************************************************************
- * Interface service call:  AmdIdentifyCore
- **********************************************************************/
-/// Request the identity (Socket, Module, Core) of the current Processor Core
-
-typedef struct {
-  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
-     OUT   UINT8             Socket;            ///< The current Core's Socket
-     OUT   UINT8             Module;            ///< The current Core's Processor Module
-     OUT   UINT8             Core;              ///< The current Core's core id.
-} AMD_IDENTIFY_PARAMS;
-
-/**
- * "Who am I" for the current running core.
- */
-AGESA_STATUS
-AmdIdentifyCore (
-  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
-);
-
-/**********************************************************************
- * Interface service call:  AmdReadEventLog
- **********************************************************************/
-/// An Event Log Entry.
-typedef struct {
-  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
-     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
-     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
-     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
-     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
-     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
-     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
-} EVENT_PARAMS;
-
-/**
- * Read an Event from the Event Log.
- */
-AGESA_STATUS
-AmdReadEventLog (
-  IN       EVENT_PARAMS *Event
-);
-
-/**********************************************************************
- * Interface service call:  AmdIdentifyDimm
- **********************************************************************/
-/// Request the identity of dimm from system address
-
-typedef struct {
-  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
-  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
-  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
-  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
-  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
-} AMD_IDENTIFY_DIMM;
-
-/**
- * Get the dimm identification for the address.
- */
-AGESA_STATUS
-AmdIdentifyDimm (
-  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
-);
-
-/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
-/// and the option value.
-///
-typedef struct {
-  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
-  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
-} IDS_NV_ITEM;
-
-/// Data Structure for IDS CallOut Function
-typedef struct {
-  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
-  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
-  IN OUT UINTN Reserved;              ///< reserved
-} IDS_CALLOUT_STRUCT;
-
-AGESA_STATUS
-AmdIdsRunApTaskLate (
-  IN       AP_EXE_PARAMS  *AmdApExeParams
-  );
-
-
-#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
-#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
-/// WARNING: Don't change the comment below, it used as signature for script
-/// AGESA IDS NV ID Definitions
-typedef enum {
-  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
-
-  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
-
-  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
-  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
-
-  AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
-  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
-  AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
-  AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
-
-  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
-  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
-  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
-  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
-  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
-  AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
-  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
-  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
-
-  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
-  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
-  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
-  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
-  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
-  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
-  AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
-  AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
-  AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
-
-  AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
-
-  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
-  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
-  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
-  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
-  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
-
-  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
-
-  AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
-
-  AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
-  AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
-  AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
-  AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
-  AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
-
-  AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
-  AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
-} IDS_EX_NV_ID;
-
-
-#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
-
-#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/AMD.h b/src/vendorcode/amd/agesa/AMD.h
deleted file mode 100644
index f788da8..0000000
--- a/src/vendorcode/amd/agesa/AMD.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA core interface
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Include
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-#define AGESA_REVISION  "Arch2008"
-#define AGESA_ID        "AGESA"
-
-#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
-#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
-//
-//
-// AGESA Types and Definitions
-//
-//
-#define LAST_ENTRY          0xFFFFFFFF
-#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-
-/// The return status for all AGESA public services.
-///
-/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
-/// will have log entries with more detail.
-///
-typedef enum {
-  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
-  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
-                                 ///<  Not logged.
-  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
-                                 ///< Example, memory address not installed, heap buffer handle not found.
-                                 ///< Not Logged.
-  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
-  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
-                                 ///<  See log.  Example, HT CRC.
-  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
-  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
-  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
-  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
-                                 ///< may not be able to reliably produce log events.
-  AgesaStatusMax                 ///< Not a status, for limit checking.
-} AGESA_STATUS;
-
-/// For checking whether a status is at or above the mandatory log level.
-#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
-
-/**
- * Callout method to the host environment.
- *
- * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
- *
- * @param[in]        Function      The specific callout function being invoked.
- * @param[in]        FcnData       Function specific data item.
- * @param[in,out]    ConfigPtr     Reference to Callout params.
- */
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (
-  IN       UINT32  Function,
-  IN       UINTN   FcnData,
-  IN OUT   VOID    *ConfigPtr
-  );
-
-typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
-  PreMemHeap = 0,                                           ///< Create heap in cache.
-  PostMemDram,                                              ///< Create heap in memory.
-  ByHost                                                    ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
-  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
-  AccessWidth16,                                            ///< Access width is 16 bits.
-  AccessWidth32,                                            ///< Access width is 32 bits.
-  AccessWidth64,                                            ///< Access width is 64 bits.
-
-  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
-  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
-  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
-  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-/// AGESA struct name
-typedef enum {
-  // AGESA BASIC FUNCTIONS
-  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
-  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
-  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
-  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
-  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
-  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
-  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
-  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
-  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
-  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
-  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
-  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
-  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
-  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
-  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
-  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
-  AMD_GET_EXECACHE_SIZE,                                    ///< AmdGetAvailableExeCacheSize general service handle
-  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
-  AMD_IDENTIFY_DIMMS                                        ///< AmdIdentifyDimm general service handle
-} AGESA_STRUCT_NAME;
-
-  /*  ResetType constant values */
-#define WARM_RESET_WHENEVER 1
-#define COLD_RESET_WHENEVER 2
-#define WARM_RESET_IMMEDIATELY 3
-#define COLD_RESET_IMMEDIATELY 4
-
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-/// For internal AGESA naming conventions, see @ref amdconfigparamname .
-typedef struct {
-  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
-  IN       UINT32          Func;             ///< The service desired
-  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
-  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
-  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
-  IN       UINT64          HeapBasePtr;      ///< Location of the heap
-  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-
-/// Create Struct Interface.
-typedef struct {
-  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
-  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
-  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
-  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
-  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
-                                                   ///< The struct to init for ByHost allocation,
-                                                   ///< the initialized struct on return.
-} AMD_INTERFACE_PARAMS;
-
-#define FUNC_0    0   // bit-placed for PCI address creation
-#define FUNC_1    1
-#define FUNC_2    2
-#define FUNC_3    3
-#define FUNC_4    4
-#define FUNC_5    5
-#define FUNC_6    6
-#define FUNC_7    7
-
-/// AGESA Binary module header structure
-typedef struct {
-  IN  UINT32  Signature;                          ///< Binary Signature
-  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
-  IN  CHAR8   Version[12];                        ///< 12 characters version
-  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
-  IN  UINT32  EntryPointAddress;                  ///< Entry address
-  IN  UINT32  ImageBase;                          ///< Image base
-  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
-  IN  UINT32  ImageSize;                          ///< Size
-  IN  UINT16  Checksum;                           ///< Checksum
-  IN  UINT8   ImageType;                          ///< Type
-  IN  UINT8   V_Reserved;                         ///< Reserved
-} AMD_IMAGE_HEADER;
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
-  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
-  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
-  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
-  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
-  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
-} AMD_MODULE_HEADER;
-
-// AMD_CODE_HEADER Signatures.
-#define AGESA_CODE_SIGNATURE  {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
-#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
-#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
-
-/// AGESA_CODE_SIGNATURE
-typedef struct {
-  IN  CHAR8   Signature[8];                       ///< code header Signature
-  IN  CHAR8   ComponentName[8];                   ///< 8 character name of the code module
-  IN  CHAR8   Version[12];                        ///< 12 character version string
-  IN  CHAR8   TerminatorNull;                     ///< null terminated string
-  IN  CHAR8   VerReserved[7];                     ///< reserved space
-} AMD_CODE_HEADER;
-
-/// Extended PCI address format
-typedef struct {
-  IN OUT  UINT32      Register:12;                ///< Register offset
-  IN OUT  UINT32      Function:3;                 ///< Function number
-  IN OUT  UINT32      Device:5;                   ///< Device number
-  IN OUT  UINT32      Bus:8;                      ///< Bus number
-  IN OUT  UINT32      Segment:4;                  ///< Segment
-} EXT_PCI_ADDR;
-
-/// Union type for PCI address
-typedef union _PCI_ADDR {
-  IN  UINT32          AddressValue;               ///< Formal address
-  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
-} PCI_ADDR;
-
-//   SBDFO - Segment Bus Device Function Offset
-//   31:28   Segment (4-bits)
-//   27:20   Bus     (8-bits)
-//   19:15   Device  (5-bits)
-//   14:12   Function(3-bits)
-//   11:00   Offset  (12-bits)
-
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
-                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct {
-  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
-  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
-  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
-  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
-} CPUID_DATA;
-
-/// HT frequency for external callbacks
-typedef enum {
-  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
-  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
-  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
-  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
-  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
-  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
-  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
-  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
-  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
-  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
-  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
-  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
-  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
-  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
-  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
-  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
-  HT_FREQUENCY_MAX                                ///< Limit check.
-} HT_FREQUENCIES;
-// The minimum HT3 frequency
-#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
-
-#ifndef BIT0
-  #define BIT0        0x0000000000000001ull
-#endif
-#ifndef BIT1
-  #define BIT1        0x0000000000000002ull
-#endif
-#ifndef BIT2
-  #define BIT2        0x0000000000000004ull
-#endif
-#ifndef BIT3
-  #define BIT3        0x0000000000000008ull
-#endif
-#ifndef BIT4
-  #define BIT4        0x0000000000000010ull
-#endif
-#ifndef BIT5
-  #define BIT5        0x0000000000000020ull
-#endif
-#ifndef BIT6
-  #define BIT6        0x0000000000000040ull
-#endif
-#ifndef BIT7
-  #define BIT7        0x0000000000000080ull
-#endif
-#ifndef BIT8
-  #define BIT8        0x0000000000000100ull
-#endif
-#ifndef BIT9
-  #define BIT9        0x0000000000000200ull
-#endif
-#ifndef BIT10
-  #define BIT10       0x0000000000000400ull
-#endif
-#ifndef BIT11
-  #define BIT11       0x0000000000000800ull
-#endif
-#ifndef BIT12
-  #define BIT12       0x0000000000001000ull
-#endif
-#ifndef BIT13
-  #define BIT13       0x0000000000002000ull
-#endif
-#ifndef BIT14
-  #define BIT14       0x0000000000004000ull
-#endif
-#ifndef BIT15
-  #define BIT15       0x0000000000008000ull
-#endif
-#ifndef BIT16
-  #define BIT16       0x0000000000010000ull
-#endif
-#ifndef BIT17
-  #define BIT17       0x0000000000020000ull
-#endif
-#ifndef BIT18
-  #define BIT18       0x0000000000040000ull
-#endif
-#ifndef BIT19
-  #define BIT19       0x0000000000080000ull
-#endif
-#ifndef BIT20
-  #define BIT20       0x0000000000100000ull
-#endif
-#ifndef BIT21
-  #define BIT21       0x0000000000200000ull
-#endif
-#ifndef BIT22
-  #define BIT22       0x0000000000400000ull
-#endif
-#ifndef BIT23
-  #define BIT23       0x0000000000800000ull
-#endif
-#ifndef BIT24
-  #define BIT24       0x0000000001000000ull
-#endif
-#ifndef BIT25
-  #define BIT25       0x0000000002000000ull
-#endif
-#ifndef BIT26
-  #define BIT26       0x0000000004000000ull
-#endif
-#ifndef BIT27
-  #define BIT27       0x0000000008000000ull
-#endif
-#ifndef BIT28
-  #define BIT28       0x0000000010000000ull
-#endif
-#ifndef BIT29
-  #define BIT29       0x0000000020000000ull
-#endif
-#ifndef BIT30
-  #define BIT30       0x0000000040000000ull
-#endif
-#ifndef BIT31
-  #define BIT31       0x0000000080000000ull
-#endif
-#ifndef BIT32
-  #define BIT32       0x0000000100000000ull
-#endif
-#ifndef BIT33
-  #define BIT33       0x0000000200000000ull
-#endif
-#ifndef BIT34
-  #define BIT34       0x0000000400000000ull
-#endif
-#ifndef BIT35
-  #define BIT35       0x0000000800000000ull
-#endif
-#ifndef BIT36
-  #define BIT36       0x0000001000000000ull
-#endif
-#ifndef BIT37
-  #define BIT37       0x0000002000000000ull
-#endif
-#ifndef BIT38
-  #define BIT38       0x0000004000000000ull
-#endif
-#ifndef BIT39
-  #define BIT39       0x0000008000000000ull
-#endif
-#ifndef BIT40
-  #define BIT40       0x0000010000000000ull
-#endif
-#ifndef BIT41
-  #define BIT41       0x0000020000000000ull
-#endif
-#ifndef BIT42
-  #define BIT42       0x0000040000000000ull
-#endif
-#ifndef BIT43
-  #define BIT43       0x0000080000000000ull
-#endif
-#ifndef BIT44
-  #define BIT44       0x0000100000000000ull
-#endif
-#ifndef BIT45
-  #define BIT45       0x0000200000000000ull
-#endif
-#ifndef BIT46
-  #define BIT46       0x0000400000000000ull
-#endif
-#ifndef BIT47
-  #define BIT47       0x0000800000000000ull
-#endif
-#ifndef BIT48
-  #define BIT48       0x0001000000000000ull
-#endif
-#ifndef BIT49
-  #define BIT49       0x0002000000000000ull
-#endif
-#ifndef BIT50
-  #define BIT50       0x0004000000000000ull
-#endif
-#ifndef BIT51
-  #define BIT51       0x0008000000000000ull
-#endif
-#ifndef BIT52
-  #define BIT52       0x0010000000000000ull
-#endif
-#ifndef BIT53
-  #define BIT53       0x0020000000000000ull
-#endif
-#ifndef BIT54
-  #define BIT54       0x0040000000000000ull
-#endif
-#ifndef BIT55
-  #define BIT55       0x0080000000000000ull
-#endif
-#ifndef BIT56
-  #define BIT56       0x0100000000000000ull
-#endif
-#ifndef BIT57
-  #define BIT57       0x0200000000000000ull
-#endif
-#ifndef BIT58
-  #define BIT58       0x0400000000000000ull
-#endif
-#ifndef BIT59
-  #define BIT59       0x0800000000000000ull
-#endif
-#ifndef BIT60
-  #define BIT60       0x1000000000000000ull
-#endif
-#ifndef BIT61
-  #define BIT61       0x2000000000000000ull
-#endif
-#ifndef BIT62
-  #define BIT62       0x4000000000000000ull
-#endif
-#ifndef BIT63
-  #define BIT63       0x8000000000000000ull
-#endif
-
-#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/Dispatcher.h b/src/vendorcode/amd/agesa/Dispatcher.h
deleted file mode 100644
index fd6aaa8..0000000
--- a/src/vendorcode/amd/agesa/Dispatcher.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Pushhigh Interface
- *
- * Contains interface to Pushhigh entry
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Legacy
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _DISPATCHER_H_
-#define _DISPATCHER_H_
-
-// AGESA function prototypes
-AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
-AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
-
-#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/Include/AdvancedApi.h
deleted file mode 100644
index 573650a..0000000
--- a/src/vendorcode/amd/agesa/Include/AdvancedApi.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Advanced API Interface for HT, Memory and CPU
- *
- * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
- * would be required by the basic interface implementations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Include
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-
-#ifndef _ADVANCED_API_H_
-#define _ADVANCED_API_H_
-
-/*----------------------------------------------------------------------------
- *                           HT FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * A constructor for the HyperTransport input structure.
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in]   StdHeader       Opaque handle to standard config header
- * @param[in]   AmdHtInterface  HT Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS      Constructors are not allowed to fail
-*/
-AGESA_STATUS
-AmdHtInterfaceConstructor (
-  IN       AMD_CONFIG_PARAMS    *StdHeader,
-  IN       AMD_HT_INTERFACE     *AmdHtInterface
-  );
-
-/**
- * The top level external interface for Hypertransport Initialization.
- *
- * Create our initial internal state, initialize the coherent fabric,
- * initialize the non-coherent chains, and perform any required fabric tuning or
- * optimization.
- *
- * @param[in]   StdHeader              Opaque handle to standard config header
- * @param[in]   PlatformConfiguration  The platform configuration options.
- * @param[in]   AmdHtInterface         HT Interface structure.
- *
- * @retval      AGESA_SUCCESS     Only information events logged.
- * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
- * @retval      AGESA_WARNING     Example: expected capability not found
- * @retval      AGESA_ERROR       logged events indicating some devices may not be available
- * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
- *
- */
-AGESA_STATUS
-AmdHtInitialize (
-  IN       AMD_CONFIG_PARAMS      *StdHeader,
-  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
-  IN       AMD_HT_INTERFACE       *AmdHtInterface
-  );
-
-/*----------------------------------------------------------------------------
- *                        HT Recovery   FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * A constructor for the HyperTransport input structure.
- *
- */
-AGESA_STATUS
-AmdHtResetConstructor (
-  IN       AMD_CONFIG_PARAMS         *StdHeader,
-  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
-  );
-
-/**
- * Initialize HT at Reset for both Normal and Recovery.
- *
- */
-AGESA_STATUS
-AmdHtInitReset (
-  IN       AMD_CONFIG_PARAMS        *StdHeader,
-  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
-  );
-
-/**
- * Initialize the Node and Socket maps for an AP Core.
- *
- */
-AGESA_STATUS
-AmdHtInitRecovery (
-  IN       AMD_CONFIG_PARAMS           *StdHeader
-  );
-
-///----------------------------------------------------------------------------
-///                          MEMORY FUNCTIONS PROTOTYPE
-///
-///----------------------------------------------------------------------------
-
-AGESA_STATUS
-AmdMemRecovery (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-AGESA_STATUS
-AmdMemAuto (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-VOID
-AmdMemInitDataStructDef (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
-  );
-
-VOID
-memDefRet (
-  VOID
-  );
-
-BOOLEAN
-memDefTrue (
-  VOID
-  );
-
-BOOLEAN
-memDefFalse (
-  VOID
-  );
-#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/Include/BrazosInstall.h
deleted file mode 100644
index 6753965..0000000
--- a/src/vendorcode/amd/agesa/Include/BrazosInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Brazos platform solution
- *
- * This file generates the defaults tables for the "Brazos" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 40817 $   @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "BrazosPI"
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
-
-
-// The Brazos solution is defined to be family 0x14 in the FT1 socket.
-#define INSTALL_FT1_SOCKET_SUPPORT      TRUE
-#define INSTALL_FAMILY_14_SUPPORT       TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE              (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/CommonReturns.h b/src/vendorcode/amd/agesa/Include/CommonReturns.h
deleted file mode 100644
index 9912edc..0000000
--- a/src/vendorcode/amd/agesa/Include/CommonReturns.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Common Return routines.
- *
- * Routines which do nothing, returning a result (preferably some version of zero) which
- * is consistent with "do nothing" or "default".  Useful for function pointer tables.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Common
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _COMMON_RETURNS_H_
-#define _COMMON_RETURNS_H_
-
-
-/**
-* Return True
-*
-* @retval True    Default case, no special action
-*/
-BOOLEAN
-CommonReturnTrue (void);
-
-/**
-* Return False.
-*
-* @retval FALSE    Default case, no special action
-*/
-BOOLEAN
-CommonReturnFalse (void);
-
-/**
- * Return (UINT8)zero.
- *
- *
- * @retval zero    None, or only case zero.
- */
-UINT8
-CommonReturnZero8 (void);
-
-/**
- * Return (UINT32)zero.
- *
- *
- * @retval zero    None, or only case zero.
- */
-UINT32
-CommonReturnZero32 (void);
-
-/**
- * Return (UINT64)zero.
- *
- *
- * @retval zero    None, or only case zero.
- */
-UINT64
-CommonReturnZero64 (void);
-
-/**
- * Return NULL
- *
- * @retval NULL    pointer to nothing
- */
-VOID *
-CommonReturnNULL (void);
-
-/**
-* Return AGESA_SUCCESS.
-*
-* @retval AGESA_SUCCESS Success.
-*/
-AGESA_STATUS
-CommonReturnAgesaSuccess (void);
-
-/**
- * Do Nothing.
- *
- */
-VOID
-CommonVoid (void);
-
-/**
- * ASSERT if this routine is called.
- *
- */
-VOID
-CommonAssert (void);
-
-#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/Include/DanNiInstall.h
deleted file mode 100644
index c56f90c..0000000
--- a/src/vendorcode/amd/agesa/Include/DanNiInstall.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Danube + Nile platform solution
- *
- * This file generates the defaults tables for the "DanNi" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "DanNiPI "
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets.
-#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
-#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-
-#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_S1G4_SOCKET_SUPPORT
-    #define INSTALL_S1G4_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_ASB2_SOCKET_SUPPORT
-    #define INSTALL_ASB2_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0x10)
-#define DFLT_SCRUB_L3_RATE              (0x10)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/Include/DanubeInstall.h
deleted file mode 100644
index f2c91c4..0000000
--- a/src/vendorcode/amd/agesa/Include/DanubeInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Danube platform solution
- *
- * This file generates the defaults tables for the "Danube" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "DanNiPI "
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Danube solution is defined to be family 0x10 in the S1g4 socket.
-#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0x10)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/Include/DevTestInstall.h
deleted file mode 100644
index 9874551..0000000
--- a/src/vendorcode/amd/agesa/Include/DevTestInstall.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a DevTest platform solution
- *
- * This file generates the defaults tables for the "DevTest" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "DevTest "
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'D', 'e', 'v', 'T', 'e', 's', 't', ' '}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
-
-
-// The DevTest solution is defined to be everything that AGESA supports.
-#define INSTALL_C32_SOCKET_SUPPORT       TRUE
-#define INSTALL_G34_SOCKET_SUPPORT       TRUE
-#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
-#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
-#define INSTALL_FS1_SOCKET_SUPPORT       TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT       TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT       TRUE
-#define INSTALL_AM3_SOCKET_SUPPORT       TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-#define INSTALL_FAMILY_12_SUPPORT        TRUE
-#define INSTALL_FAMILY_14_SUPPORT        TRUE
-#define INSTALL_FAMILY_15_SUPPORT        TRUE
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0xFF)
-#define DFLT_SCRUB_L2_RATE              (0x10)
-#define DFLT_SCRUB_L3_RATE              (0x10)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DragonInstall.h b/src/vendorcode/amd/agesa/Include/DragonInstall.h
deleted file mode 100644
index ee45b72..0000000
--- a/src/vendorcode/amd/agesa/Include/DragonInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Dragon platform solution
- *
- * This file generates the defaults tables for the "Dragon" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "DragonPI"
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
-
-
-// The Danube solution is defined to be family 0x10 in the AM3 socket.
-#define INSTALL_AM3_SOCKET_SUPPORT       TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/Filecode.h b/src/vendorcode/amd/agesa/Include/Filecode.h
deleted file mode 100644
index 9ba1b29..0000000
--- a/src/vendorcode/amd/agesa/Include/Filecode.h
+++ /dev/null
@@ -1,849 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Collectively assign unique filecodes for assert and debug to each source file.
- *
- * Publish values for decorated filenames, which can be used for
- * ASSERT and debug support using a preprocessor define like:
- * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
- * This file serves as a reference for debugging to associate the code and filename.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Include
- * @e \$Revision: 40742 $   @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _FILECODE_H_
-#define _FILECODE_H_
-
-#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
-
-/// For debug use in any Platform's options C file.
-/// Can be reused for platforms and image builds, since only one options file can be built.
-#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
-
-
-#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE                          (0xA001)
-#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE                 (0xA002)
-#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE                 (0xA003)
-#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE                              (0xA004)
-#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE                                (0xA005)
-#define PROC_GNB_GFX_GFXGMCINIT_FILECODE                                 (0xA006)
-#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE                           (0xA010)
-#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE                           (0xA011)
-#define PROC_GNB_GFX_GFXINITATPOST_FILECODE                              (0xA012)
-#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE                 (0xA013)
-#define PROC_GNB_GFX_GFXLIB_FILECODE                                     (0xA014)
-#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE                             (0xA015)
-#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE                              (0xA016)
-#define PROC_GNB_GNBINITATEARLY_FILECODE                                 (0xA017)
-#define PROC_GNB_GNBINITATENV_FILECODE                                   (0xA020)
-#define PROC_GNB_GNBINITATLATE_FILECODE                                  (0xA021)
-#define PROC_GNB_GNBINITATMID_FILECODE                                   (0xA022)
-#define PROC_GNB_GNBINITATPOST_FILECODE                                  (0xA023)
-#define PROC_GNB_GNBINITATRESET_FILECODE                                 (0xA024)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE                    (0xA025)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE              (0xA026)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE                (0xA027)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE               (0xA028)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE              (0xA029)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE                 (0xA02A)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE              (0xA030)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE            (0xA031)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE      (0xA032)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE      (0xA033)
-#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE          (0xA034)
-#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE                 (0xA035)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE           (0xA036)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE            (0xA037)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE          (0xA038)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE          (0xA039)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE              (0xA03A)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE     (0xA03B)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE   (0xA03C)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE       (0xA03D)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE       (0xA03E)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE        (0xA03F)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE      (0xA041)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE         (0xA043)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE            (0xA044)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE   (0xA045)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE             (0xA046)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE  (0xA047)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE        (0xA048)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE     (0xA049)
-#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE         (0xA04A)
-#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE      (0xA04B)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE                  (0xA04C)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE                   (0xA04D)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE                        (0xA04E)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE              (0xA04F)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE                  (0xA050)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE                   (0xA051)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE                        (0xA052)
-#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE                         (0xA053)
-#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE                           (0xA054)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE                    (0xA055)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE                    (0xA056)
-#define PROC_GNB_NB_NBCONFIGDATA_FILECODE                                (0xA060)
-#define PROC_GNB_NB_NBINIT_FILECODE                                      (0xA061)
-#define PROC_GNB_NB_NBINITATEARLY_FILECODE                               (0xA062)
-#define PROC_GNB_NB_NBINITATENV_FILECODE                                 (0xA063)
-#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE                            (0xA070)
-#define PROC_GNB_NB_NBINITATPOST_FILECODE                                (0xA071)
-#define PROC_GNB_NB_NBINITATRESET_FILECODE                               (0xA072)
-#define PROC_GNB_NB_NBPOWERMGMT_FILECODE                                 (0xA073)
-#define PROC_GNB_NB_NBSMULIB_FILECODE                                    (0xA074)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE                   (0xA075)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE          (0xA076)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE        (0xA077)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE            (0xA078)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE            (0xA079)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE        (0xA07A)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE                   (0xA07D)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE          (0xA07E)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE        (0xA07F)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE            (0xA080)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE            (0xA081)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE        (0xA082)
-#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE                     (0xA083)
-#define PROC_GNB_PCIE_PCIEINIT_FILECODE                                  (0xA084)
-#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE                       (0xA085)
-#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE                             (0xA086)
-#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE                        (0xA087)
-#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE                            (0xA088)
-#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE                              (0xA089)
-#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE                               (0xA08A)
-#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE                              (0xA08B)
-#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE                          (0xA08C)
-#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE              (0xA08D)
-#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE              (0xA08E)
-#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE             (0xA08F)
-
-#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                           (0xAE01)
-#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                        (0xAE02)
-
-// FCH
-#define PROC_COMMON_AMDFCH_FILECODE                                      (0xB000)
-#define PROC_FCH_AZALIA_AZALIA_FILECODE                                  (0xB001)
-#define PROC_FCH_AZALIA_AZALIARESET_FILECODE                             (0xB002)
-#define PROC_FCH_COMMON_ACPILIB_FILECODE                                 (0xB010)
-#define PROC_FCH_COMMON_AMDSBLIB_FILECODE                                (0xB011)
-#define PROC_FCH_COMMON_FCHCOMMON_FILECODE                               (0xB012)
-#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE                            (0xB013)
-#define PROC_FCH_COMMON_MEMLIB_FILECODE                                  (0xB014)
-#define PROC_FCH_COMMON_PCILIB_FILECODE                                  (0xB015)
-#define PROC_FCH_COMMON_SBPELIB_FILECODE                                 (0xB016)
-#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE                        (0xB020)
-#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE                   (0xB021)
-#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE                  (0xB030)
-#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE             (0xB031)
-#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE                        (0xB032)
-#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE                   (0xB033)
-#define PROC_FCH_IDE_IDE_FILECODE                                        (0xB040)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE                        (0xB050)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE                     (0xB051)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE                   (0xB052)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE                       (0xB053)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE                  (0xB054)
-#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE                         (0xB060)
-#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE                           (0xB061)
-#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE                         (0xB062)
-#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE                           (0xB063)
-#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE                          (0xB064)
-#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE                           (0xB065)
-#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE                            (0xB066)
-#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE                      (0xB067)
-#define PROC_FCH_IR_IR_FILECODE                                          (0xB070)
-#define PROC_FCH_PCIB_PCIB_FILECODE                                      (0xB080)
-#define PROC_FCH_PCIB_PCIBRESET_FILECODE                                 (0xB081)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE                        (0xB090)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE                   (0xB091)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE                       (0xB092)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE                     (0xB093)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE                    (0xB094)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE                  (0xB095)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE                      (0xB096)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE                 (0xB097)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE                      (0xB0A0)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE                   (0xB0A1)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE                  (0xB0A2)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE               (0xB0A3)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE                      (0xB0A4)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE                   (0xB0A5)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE                      (0xB0A6)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE                   (0xB0A7)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE                (0xB0A8)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE                   (0xB0A9)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE                 (0xB0AA)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE                     (0xB0B0)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE                (0xB0B1)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE                     (0xB0B2)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE                (0xB0B3)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE                      (0xB0B4)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE                 (0xB0B5)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE                     (0xB0B6)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE                (0xB0B7)
-#define PROC_FCH_SD_SD_FILECODE                                          (0xB0C0)
-#define PROC_FCH_SPI_LPC_FILECODE                                        (0xB0D0)
-#define PROC_FCH_SPI_LPCRESET_FILECODE                                   (0xB0D1)
-#define PROC_FCH_SPI_SPI_FILECODE                                        (0xB0D2)
-#define PROC_FCH_SPI_SPIRESET_FILECODE                                   (0xB0D3)
-
-#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE                              (0xB200)
-#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE                            (0xB210)
-#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE                            (0xB211)
-#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE                            (0xB212)
-#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE                            (0xB213)
-#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE                            (0xB214)
-#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE                              (0xB220)
-#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE                     (0xB221)
-#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE                       (0xB222)
-#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE                (0xB230)
-#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE                          (0xB240)
-#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE              (0xB250)
-#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE                 (0xB251)
-#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE                 (0xB252)
-#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE                              (0xB260)
-#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE                               (0xB261)
-#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE                               (0xB262)
-#define UEFI_PEI_SMBUS_SMBUS_FILECODE                                    (0xB270)
-#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE                              (0xB280)
-#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE                                (0xB281)
-#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE                                (0xB282)
-#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE                             (0xB283)
-#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE                               (0xB284)
-#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE                      (0xB285)
-#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE                        (0xB286)
-#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE                                 (0xB287)
-#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE                                 (0xB288)
-#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE                               (0xB2A0)
-#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE                     (0xB290)
-#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE         (0xB291)
-#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE               (0xB292)
-#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE         (0xB293)
-#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE             (0xB294)
-#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295)
-#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE         (0xB296)
-#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE                 (0xB297)
-#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE                 (0xB298)
-#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE               (0xB299)
-
-#define LIB_AMDLIB_FILECODE                                              (0xC001)
-
-#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
-#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
-#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
-
-#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE            (0xC120)
-
-#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE                (0xC140)
-#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE      (0xC141)
-#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE                (0xC142)
-#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE                               (0xC162)
-
-#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
-#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
-#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
-#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
-#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
-#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
-#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
-#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
-#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
-#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
-#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
-
-#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
-#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
-#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
-#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
-#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
-
-#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
-#define PROC_CPU_CPUBRANDID_FILECODE                                     (0xC402)
-#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
-#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
-#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
-#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
-#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
-#define PROC_CPU_CPUINITEARLYTABLE_FILECODE                              (0xC409)
-#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
-#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
-#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
-#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
-#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
-
-#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
-#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
-#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
-#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
-#define PROC_CPU_S3_FILECODE                                             (0xC460)
-
-// Family 10h
-#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE              (0xC801)
-#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE                      (0xC802)
-#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE                (0xC803)
-#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE             (0xC804)
-#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE                          (0xC805)
-#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE                    (0xC806)
-#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE              (0xC807)
-#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE                  (0xC808)
-#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE                    (0xC809)
-#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE                    (0xC80A)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE                   (0xC80B)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE        (0xC80C)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE                   (0xC80D)
-#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE              (0xC80E)
-#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE                    (0xC80F)
-#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE           (0xC810)
-#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE                       (0xC811)
-#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE                          (0xC812)
-#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE             (0xC813)
-#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE                  (0xC820)
-#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE             (0xC821)
-#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE              (0xC822)
-#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE                  (0xC823)
-#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE                 (0xC824)
-#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE                  (0xC825)
-#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE          (0xC826)
-#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE                        (0xC827)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE              (0xC830)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE                  (0xC831)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE                  (0xC832)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE              (0xC833)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE              (0xC834)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE            (0xC835)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE           (0xC836)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE       (0xC837)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE  (0xC838)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE             (0xC839)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE      (0xC83A)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE             (0xC83B)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE      (0xC83C)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE           (0xC83D)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE       (0xC83E)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE  (0xC83F)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE             (0xC840)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE      (0xC841)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE             (0xC842)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE      (0xC843)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE           (0xC844)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE       (0xC845)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE  (0xC846)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE             (0xC847)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE      (0xC848)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE             (0xC849)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE              (0xC850)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE            (0xC851)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE               (0xC852)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE           (0xC853)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE        (0xC854)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE       (0xC855)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE  (0xC856)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE             (0xC857)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE      (0xC858)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE             (0xC859)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE              (0xC860)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE              (0xC861)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE              (0xC862)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE            (0xC863)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE      (0xC864)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE           (0xC865)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE       (0xC866)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE  (0xC867)
-
-// Family 12h
-#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE              (0xC901)
-#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE                      (0xC902)
-#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE                (0xC903)
-#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE                          (0xC904)
-#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE                    (0xC905)
-#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE            (0xC906)
-#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE                    (0xC907)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE                   (0xC908)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE        (0xC909)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE                   (0xC90A)
-#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE              (0xC90B)
-#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE                    (0xC90C)
-#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE           (0xC90D)
-#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE                       (0xC90E)
-#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE                         (0xC90F)
-#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE                             (0xC910)
-#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE                        (0xC911)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE            (0xC921)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE       (0xC922)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE           (0xC923)
-#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE             (0xC924)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE               (0xC925)
-
-// Family 14h
-#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE              (0xCA01)
-#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE                      (0xCA02)
-#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE                (0xCA03)
-#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE                          (0xCA04)
-#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE                    (0xCA05)
-#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE                    (0xCA06)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE                   (0xCA07)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE        (0xCA08)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE                   (0xCA09)
-#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE              (0xCA0A)
-#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE                    (0xCA0B)
-#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE           (0xCA0C)
-#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0xCA0D)
-#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE                         (0xCA0E)
-#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE                        (0xCA0F)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA21)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA22)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA23)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE             (0xCA24)
-#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA25)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE               (0xCA26)
-
-// Family 15h
-#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE              (0xCB01)
-#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE                      (0xCB02)
-#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE                (0xCB03)
-#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE             (0xCB04)
-#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE               (0xCB05)
-#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE                          (0xCB06)
-#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE              (0xCB07)
-#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE                  (0xCB08)
-#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE                    (0xCB09)
-#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE                 (0xCB0A)
-#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE                    (0xCB0B)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE                   (0xCB0C)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE        (0xCB0D)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE                   (0xCB0E)
-#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE              (0xCB0F)
-#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE                    (0xCB10)
-#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE           (0xCB11)
-#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE                       (0xCB12)
-#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE                  (0xCB13)
-#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE             (0xCB14)
-#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE              (0xCB15)
-#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE                         (0xCB16)
-#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE                             (0xCB17)
-#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE                  (0xCB18)
-#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE                    (0xCB19)
-#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE             (0xCB1A)
-#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE                        (0xCB1B)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE                   (0xCB30)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE                (0xCB31)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE            (0xCB32)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE       (0xCB33)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE                  (0xCB34)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE             (0xCB35)
-#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE           (0xCB36)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE                  (0xCB37)
-
-
-
-#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
-#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
-#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
-#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
-#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE                            (0xDC30)
-#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
-#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
-#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
-#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
-#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
-#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
-#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE                               (0xDC80)
-#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE                               (0xDC81)
-#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC82)
-#define PROC_CPU_FEATURE_CPUCPB_FILECODE                                 (0xDC83)
-#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE                        (0xDC84)
-#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE                            (0xDC85)
-#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
-#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
-#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
-#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
-
-#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE                           (0xDE01)
-
-#define PROC_HT_FEATURES_HTFEATSETS_FILECODE                             (0xE001)
-#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE                 (0xE002)
-#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE                          (0xE003)
-#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE                      (0xE004)
-#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE                     (0xE005)
-#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE                          (0xE006)
-#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE                         (0xE007)
-#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE              (0xE008)
-#define PROC_HT_FEATURES_HTIDS_FILECODE                                  (0xE009)
-#define PROC_HT_HTFEAT_FILECODE                                          (0xE021)
-#define PROC_HT_HTINTERFACE_FILECODE                                     (0xE022)
-#define PROC_HT_HTINTERFACECOHERENT_FILECODE                             (0xE023)
-#define PROC_HT_HTINTERFACEGENERAL_FILECODE                              (0xE024)
-#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE                          (0xE025)
-#define PROC_HT_HTMAIN_FILECODE                                          (0xE026)
-#define PROC_HT_HTNOTIFY_FILECODE                                        (0xE027)
-#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE                                 (0xE028)
-#define PROC_HT_HTNB_FILECODE                                            (0xE081)
-#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE                           (0xE082)
-#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE                        (0xE083)
-#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE                       (0xE084)
-#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE                          (0xE085)
-#define PROC_HT_FAM10_HTNBFAM10_FILECODE                                 (0xE0C1)
-#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE                         (0xE0C2)
-#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE                      (0xE0C3)
-#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE                     (0xE0C4)
-#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE                           (0xE0C5)
-#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE                        (0xE0C6)
-#define PROC_HT_FAM12_HTNBFAM12_FILECODE                                 (0xE101)
-#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE                        (0xE102)
-#define PROC_HT_FAM14_HTNBFAM14_FILECODE                                 (0xE141)
-#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE                        (0xE142)
-#define PROC_HT_FAM15_HTNBFAM15_FILECODE                                 (0xE181)
-#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE                         (0xE182)
-#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE                      (0xE183)
-#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE                     (0xE184)
-#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE                           (0xE185)
-#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE                        (0xE186)
-
-#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE                         (0xE302)
-#define PROC_RECOVERY_HT_HTINITRESET_FILECODE                            (0xE301)
-
-#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
-#define PROC_IDS_CONTROL_IDSLIB_FILECODE                                 (0xE802)
-#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
-#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
-#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE                   (0xE805)
-#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE                 (0xE806)
-#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE                 (0xE807)
-#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE                 (0xE808)
-#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE                 (0xE809)
-#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE                   (0xE80A)
-#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE                   (0xE80B)
-#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE                   (0xE80C)
-
-#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE                              (0xE80D)
-#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE                            (0xE80E)
-
-///0xE820 ~ 0xE840 is reserved for ids extend module
-
-#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
-#define PROC_MEM_ARDK_DR_MARDR2_FILECODE                             (0xF002)
-#define PROC_MEM_ARDK_DR_MARDR3_FILECODE                             (0xF003)
-#define PROC_MEM_ARDK_HY_MARHY3_FILECODE                             (0xF004)
-#define PROC_MEM_ARDK_LN_MASLN3_FILECODE                             (0xF005)
-#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE                             (0xF006)
-#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE                             (0xF007)
-#define PROC_MEM_ARDK_LN_MAULN3_FILECODE                             (0xF008)
-#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE                             (0xF009)
-#define PROC_MEM_ARDK_DA_MASDA2_FILECODE                             (0xF00A)
-#define PROC_MEM_ARDK_DA_MASDA3_FILECODE                             (0xF00B)
-#define PROC_MEM_ARDK_NI_MASNI3_FILECODE                             (0xF00C)
-#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE                          (0xF00D)
-#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE                          (0xF00E)
-#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE                             (0xF00F)
-#define PROC_MEM_ARDK_ON_MASON3_FILECODE                             (0xF010)
-#define PROC_MEM_ARDK_ON_MAUON3_FILECODE                             (0xF011)
-#define PROC_MEM_ARDK_PH_MASPH3_FILECODE                             (0xF012)
-#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE                             (0xF013)
-#define PROC_MEM_ARDK_OR_MAROR3_FILECODE                             (0xF014)
-#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE                             (0xF017)
-#define PROC_MEM_ARDK_RB_MASRB3_FILECODE                             (0xF018)
-#define PROC_MEM_ARDK_RB_MAURB3_FILECODE                             (0xF019)
-
-#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
-#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
-#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
-#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
-#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
-#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
-#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE                     (0xF089)
-#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
-#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
-#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE                         (0xF08C)
-#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
-#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE                         (0xF08E)
-#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
-#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
-#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
-#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
-
-#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
-#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
-#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
-#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
-#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
-#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
-#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE                           (0xF107)
-#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE                           (0xF108)
-#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE                           (0xF109)
-#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE                           (0xF10A)
-#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
-#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
-#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
-#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
-#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
-#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
-#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE                           (0xF111)
-#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
-#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
-#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE                         (0xF114)
-#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
-#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
-#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
-#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
-#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE                           (0xF119)
-#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE                           (0xF11A)
-#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE                           (0xF11B)
-
-#define PROC_MEM_NB_DR_MNDR_FILECODE                                 (0XF213)
-#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE                             (0XF214)
-#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE                         (0XF216)
-#define PROC_MEM_NB_DR_MNMCTDR_FILECODE                              (0XF217)
-#define PROC_MEM_NB_DR_MNDCTDR_FILECODE                              (0XF218)
-#define PROC_MEM_NB_DR_MNOTDR_FILECODE                               (0XF219)
-#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE                         (0XF21A)
-#define PROC_MEM_NB_DR_MNPROTODR_FILECODE                            (0XF21C)
-#define PROC_MEM_NB_DR_MNS3DR_FILECODE                               (0XF21D)
-#define PROC_MEM_NB_DR_MNREGDR_FILECODE                              (0XF21E)
-#define PROC_MEM_NB_RB_MNRB_FILECODE                                 (0XF220)
-#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE                             (0XF221)
-#define PROC_MEM_NB_RB_MNS3RB_FILECODE                               (0XF222)
-#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE                         (0XF223)
-#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE                             (0XF233)
-#define PROC_MEM_NB_HY_MNHY_FILECODE                                 (0XF235)
-#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE                         (0XF236)
-#define PROC_MEM_NB_HY_MNMCTHY_FILECODE                              (0XF237)
-#define PROC_MEM_NB_HY_MNDCTHY_FILECODE                              (0XF238)
-#define PROC_MEM_NB_HY_MNOTHY_FILECODE                               (0XF239)
-#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE                         (0XF23A)
-#define PROC_MEM_NB_HY_MNPHYHY_FILECODE                              (0XF23B)
-#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE                            (0XF23C)
-#define PROC_MEM_NB_HY_MNS3HY_FILECODE                               (0XF23D)
-#define PROC_MEM_NB_HY_MNREGHY_FILECODE                              (0XF23E)
-#define PROC_MEM_NB_ON_MNON_FILECODE                                 (0xF240)
-#define PROC_MEM_NB_ON_MNREGON_FILECODE                              (0xF241)
-#define PROC_MEM_NB_ON_MNDCTON_FILECODE                              (0xF242)
-#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE                         (0xF244)
-#define PROC_MEM_NB_ON_MNMCTON_FILECODE                              (0xF245)
-#define PROC_MEM_NB_ON_MNOTON_FILECODE                               (0xF246)
-#define PROC_MEM_NB_ON_MNPHYON_FILECODE                              (0xF247)
-#define PROC_MEM_NB_ON_MNS3ON_FILECODE                               (0xF248)
-#define PROC_MEM_NB_ON_MNFLOWON_FILECODE                             (0xF249)
-#define PROC_MEM_NB_ON_MNPROTOON_FILECODE                            (0xF24A)
-#define PROC_MEM_NB_LN_MNDCTLN_FILECODE                              (0XF252)
-#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE                             (0XF253)
-#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE                         (0XF254)
-#define PROC_MEM_NB_LN_MNMCTLN_FILECODE                              (0XF255)
-#define PROC_MEM_NB_LN_MNOTLN_FILECODE                               (0XF256)
-#define PROC_MEM_NB_LN_MNPHYLN_FILECODE                              (0XF257)
-#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE                            (0XF258)
-#define PROC_MEM_NB_LN_MNLN_FILECODE                                 (0XF259)
-#define PROC_MEM_NB_LN_MNS3LN_FILECODE                               (0XF25A)
-#define PROC_MEM_NB_LN_MNREGLN_FILECODE                              (0XF25B)
-#define PROC_MEM_NB_DA_MNDA_FILECODE                                 (0XF260)
-#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE                             (0XF261)
-#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE                         (0XF263)
-#define PROC_MEM_NB_DA_MNMCTDA_FILECODE                              (0XF264)
-#define PROC_MEM_NB_DA_MNDCTDA_FILECODE                              (0XF265)
-#define PROC_MEM_NB_DA_MNOTDA_FILECODE                               (0XF266)
-#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE                         (0XF267)
-#define PROC_MEM_NB_DA_MNPROTODA_FILECODE                            (0XF269)
-#define PROC_MEM_NB_DA_MNS3DA_FILECODE                               (0XF26A)
-#define PROC_MEM_NB_DA_MNREGDA_FILECODE                              (0XF26B)
-#define PROC_MEM_NB_C32_MNC32_FILECODE                               (0XF26C)
-#define PROC_MEM_NB_C32_MNDCTC32_FILECODE                            (0XF26D)
-#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE                           (0XF26E)
-#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE                       (0XF26F)
-#define PROC_MEM_NB_C32_MNMCTC32_FILECODE                            (0XF270)
-#define PROC_MEM_NB_C32_MNOTC32_FILECODE                             (0XF271)
-#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE                       (0XF272)
-#define PROC_MEM_NB_C32_MNPHYC32_FILECODE                            (0XF273)
-#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE                          (0XF274)
-#define PROC_MEM_NB_C32_MNS3C32_FILECODE                             (0XF275)
-#define PROC_MEM_NB_C32_MNREGC32_FILECODE                            (0XF277)
-#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
-#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
-#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
-#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
-#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
-#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
-#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
-#define PROC_MEM_NB_MNTRAIN2_FILECODE                                (0XF283)
-#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
-#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
-#define PROC_MEM_NB_NI_MNNI_FILECODE                                 (0XF286)
-#define PROC_MEM_NB_NI_MNS3NI_FILECODE                               (0XF287)
-#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE                             (0XF288)
-#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE                             (0XF289)
-#define PROC_MEM_NB_PH_MNPH_FILECODE                                 (0XF28A)
-#define PROC_MEM_NB_PH_MNS3PH_FILECODE                               (0XF28B)
-#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE                         (0XF28C)
-#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE                             (0XF290)
-#define PROC_MEM_NB_OR_MNOR_FILECODE                                 (0XF291)
-#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE                         (0XF292)
-#define PROC_MEM_NB_OR_MNMCTOR_FILECODE                              (0XF293)
-#define PROC_MEM_NB_OR_MNDCTOR_FILECODE                              (0XF294)
-#define PROC_MEM_NB_OR_MNOTOR_FILECODE                               (0XF295)
-#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE                         (0XF296)
-#define PROC_MEM_NB_OR_MNPHYOR_FILECODE                              (0XF297)
-#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE                            (0XF298)
-#define PROC_MEM_NB_OR_MNS3OR_FILECODE                               (0XF299)
-#define PROC_MEM_NB_OR_MNREGOR_FILECODE                              (0XF29A)
-
-#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
-#define PROC_MEM_PS_DR_MPRDR3_FILECODE                               (0XF402)
-#define PROC_MEM_PS_HY_MPRHY3_FILECODE                               (0XF403)
-#define PROC_MEM_PS_LN_MPRLN3_FILECODE                               (0XF404)
-#define PROC_MEM_PS_DR_MPSDR3_FILECODE                               (0XF405)
-#define PROC_MEM_PS_HY_MPSHY3_FILECODE                               (0XF406)
-#define PROC_MEM_PS_LN_MPSLN3_FILECODE                               (0XF407)
-#define PROC_MEM_PS_DR_MPUDR3_FILECODE                               (0XF408)
-#define PROC_MEM_PS_HY_MPUHY3_FILECODE                               (0XF409)
-#define PROC_MEM_PS_LN_MPULN3_FILECODE                               (0XF40A)
-#define PROC_MEM_PS_DA_MPUDA3_FILECODE                               (0XF40B)
-#define PROC_MEM_PS_DA_MPSDA2_FILECODE                               (0XF40C)
-#define PROC_MEM_PS_DA_MPSDA3_FILECODE                               (0XF40D)
-#define PROC_MEM_PS_DR_MPRDR2_FILECODE                               (0XF40E)
-#define PROC_MEM_PS_DR_MPUDR2_FILECODE                               (0XF40F)
-#define PROC_MEM_PS_C32_MPRC32_3_FILECODE                            (0XF410)
-#define PROC_MEM_PS_C32_MPUC32_3_FILECODE                            (0XF411)
-#define PROC_MEM_PS_NI_MPSNI3_FILECODE                               (0XF412)
-#define PROC_MEM_PS_NI_MPUNI3_FILECODE                               (0XF413)
-#define PROC_MEM_PS_ON_MPSON3_FILECODE                               (0XF414)
-#define PROC_MEM_PS_ON_MPUON3_FILECODE                               (0XF415)
-#define PROC_MEM_PS_PH_MPSPH3_FILECODE                               (0XF416)
-#define PROC_MEM_PS_PH_MPUPH3_FILECODE                               (0XF417)
-#define PROC_MEM_PS_RB_MPSRB3_FILECODE                               (0XF418)
-#define PROC_MEM_PS_RB_MPURB3_FILECODE                               (0XF419)
-#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE                          (0XF41A)
-#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE                          (0XF41B)
-#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE                          (0XF41C)
-#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE                          (0XF41D)
-#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE                          (0XF41E)
-#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE                          (0XF41F)
-#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE                          (0XF420)
-#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE                          (0XF421)
-#define PROC_MEM_PS_MPRTT_FILECODE                                   (0XF422)
-#define PROC_MEM_PS_MPMAXFREQ_FILECODE                               (0XF423)
-#define PROC_MEM_PS_MPODTPAT_FILECODE                                (0XF424)
-#define PROC_MEM_PS_MPSAO_FILECODE                                   (0XF425)
-#define PROC_MEM_PS_MPMR0_FILECODE                                   (0XF426)
-#define PROC_MEM_PS_MPRC2IBT_FILECODE                                (0XF427)
-#define PROC_MEM_PS_MPRC10OPSPD_FILECODE                             (0XF428)
-#define PROC_MEM_PS_MPLRIBT_FILECODE                                 (0XF429)
-#define PROC_MEM_PS_MPLRNPR_FILECODE                                 (0XF42A)
-#define PROC_MEM_PS_MPLRNLR_FILECODE                                 (0XF42B)
-#define PROC_MEM_PS_OR_MPOR3_FILECODE                                (0XF42C)
-
-#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
-#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
-#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
-#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
-#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
-#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
-#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
-#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
-#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
-#define PROC_MEM_TECH_DDR2_MT2_FILECODE                              (0XF541)
-#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE                            (0XF543)
-#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE                           (0XF544)
-#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
-#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
-#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
-#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
-#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
-#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
-#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
-#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE                        (0XF589)
-
-#define PROC_RECOVERY_MEM_MRDEF_FILECODE                             (0XF801)
-#define PROC_RECOVERY_MEM_MRINIT_FILECODE                            (0XF802)
-#define PROC_RECOVERY_MEM_MRM_FILECODE                               (0XF803)
-#define PROC_RECOVERY_MEM_MRUC_FILECODE                              (0XF804)
-#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE                       (0XF812)
-#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE                    (0XF813)
-#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE                    (0XF821)
-#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE                       (0XF822)
-#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE                    (0XF823)
-#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE                  (0XF825)
-#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE                    (0XF831)
-#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE                    (0XF832)
-#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE                       (0XF833)
-#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE                       (0XF842)
-#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE                    (0XF843)
-#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE                       (0XF845)
-#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE                     (0XF851)
-#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE                  (0XF852)
-#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE                (0XF853)
-#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE                    (0xF861)
-#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE                    (0xF862)
-#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE                       (0xF863)
-#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE                       (0xF871)
-#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE                       (0xF881)
-#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE                      (0XF8C1)
-#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE                      (0XF8C2)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE                    (0XF8C3)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE                 (0XF8C4)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE                 (0XF8C5)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE                 (0XF8C6)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE                 (0XF8C7)
-#define PROC_RECOVERY_MEM_NB_MRN_FILECODE                            (0XF8C8)
-#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE                         (0XF8C9)
-#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE                         (0XF8CA)
-#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE                      (0XF8CB)
-#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE                      (0XF8CC)
-#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE                    (0XF8CD)
-#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE                       (0XF8CE)
-#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE                    (0XF8CF)
-#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE                  (0XF8D0)
-#define PROC_RECOVERY_MEM_PS_MRP_FILECODE                            (0XF8E0)
-#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE                         (0XF8E1)
-#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE                      (0XF8E2)
-#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE                         (0XF8E3)
-#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE                         (0XF8E4)
-#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE                      (0XF8E5)
-#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE                   (0XF8E6)
-#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE                       (0XF8E7)
-#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE                       (0XF8E8)
-#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE                       (0XF8E9)
-#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE                      (0XF8EA)
-#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE                (0XF8EB)
-#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE                (0XF8EC)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE                (0XF8ED)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE                (0XF8EE)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE                (0XF8EF)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE                (0XF8F0)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE                (0XF8F1)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE                (0XF8F2)
-
-#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/Include/GeneralServices.h b/src/vendorcode/amd/agesa/Include/GeneralServices.h
deleted file mode 100644
index 14ba10e..0000000
--- a/src/vendorcode/amd/agesa/Include/GeneralServices.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * General Services
- *
- * Provides Services similar to the external General Services API, except
- * suited to use within AGESA components.  Socket, Core and PCI identification.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Common
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _GENERAL_SERVICES_H_
-#define _GENERAL_SERVICES_H_
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define NUMBER_OF_EVENT_DATA_PARAMS 4
-
-/**
- * AMD Device id for MMIO check.
- */
-#define AMD_DEV_VEN_ID 0x1022
-#define AMD_DEV_VEN_ID_ADDRESS 0
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * An AGESA Event Log entry.
- */
-typedef struct {
-  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
-  UINT32   EventInfo;        ///< Uniquely identifies the event.
-  UINT32   DataParam1;       ///< Event specific additional data
-  UINT32   DataParam2;       ///< Event specific additional data
-  UINT32   DataParam3;       ///< Event specific additional data
-  UINT32   DataParam4;       ///< Event specific additional data
-} AGESA_EVENT;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Get a specified Core's APIC ID.
- *
- * @param[in]    StdHeader    Header for library and services.
- * @param[in]    Socket       The Core's Socket.
- * @param[in]    Core         The Core id.
- * @param[out]   ApicAddress  The Core's APIC ID.
- * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval       TRUE         The core is present, APIC Id valid
- * @retval       FALSE        The core is not present, APIC Id not valid.
- */
-BOOLEAN
-GetApicId (
-  IN       AMD_CONFIG_PARAMS *StdHeader,
-  IN       UINT32            Socket,
-  IN       UINT32            Core,
-     OUT   UINT8             *ApicAddress,
-     OUT   AGESA_STATUS      *AgesaStatus
-);
-
-/**
- * Get Processor Module's PCI Config Space address.
- *
- * @param[in]    StdHeader    Header for library and services.
- * @param[in]    Socket       The Core's Socket.
- * @param[in]    Module       The Module in that Processor
- * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
- * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval       TRUE         The core is present, PCI Address valid
- * @retval       FALSE        The core is not present, PCI Address not valid.
- */
-BOOLEAN
-GetPciAddress (
-  IN       AMD_CONFIG_PARAMS *StdHeader,
-  IN       UINT32            Socket,
-  IN       UINT32            Module,
-     OUT   PCI_ADDR          *PciAddress,
-     OUT   AGESA_STATUS      *AgesaStatus
-);
-
-/**
- * "Who am I" for the current running core.
- *
- * @param[in]    StdHeader    Header for library and services.
- * @param[out]   Socket       The current Core's Socket
- * @param[out]   Module       The current Core's Processor Module
- * @param[out]   Core         The current Core's core id.
- * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- */
-VOID
-IdentifyCore (
-  IN       AMD_CONFIG_PARAMS *StdHeader,
-     OUT   UINT32            *Socket,
-     OUT   UINT32            *Module,
-     OUT   UINT32            *Core,
-     OUT   AGESA_STATUS      *AgesaStatus
-);
-
-/**
- *  A boolean function determine executed CPU is BSP core.
- */
-BOOLEAN
-IsBsp (
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
-     OUT   AGESA_STATUS      *AgesaStatus
-  );
-
-/**
- * This function logs AGESA events into the event log.
- */
-VOID
-PutEventLog (
-  IN       AGESA_STATUS EventClass,
-  IN       UINT32 EventInfo,
-  IN       UINT32 DataParam1,
-  IN       UINT32 DataParam2,
-  IN       UINT32 DataParam3,
-  IN       UINT32 DataParam4,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/**
- * This function gets event logs from the circular buffer.
- */
-AGESA_STATUS
-GetEventLog (
-     OUT   AGESA_EVENT *EventRecord,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/**
- * This function gets event logs from the circular buffer without flushing the entry.
- */
-BOOLEAN
-PeekEventLog (
-     OUT   AGESA_EVENT *EventRecord,
-  IN       UINT16 Index,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This routine programs the registers necessary to get the PCI MMIO mechanism
- * up and functioning.
- */
-VOID
-InitializePciMmio (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-#endif  // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/Include/GnbInterface.h b/src/vendorcode/amd/agesa/Include/GnbInterface.h
deleted file mode 100644
index 761cf3a..0000000
--- a/src/vendorcode/amd/agesa/Include/GnbInterface.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB API definition.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:     AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBINTERFACE_H_
-#define _GNBINTERFACE_H_
-
-AGESA_STATUS
-GnbInitAtReset (
-  IN      AMD_CONFIG_PARAMS       *StdHeader
-  );
-
-AGESA_STATUS
-GnbInitAtEarly (
-  IN OUT  AMD_EARLY_PARAMS        *EarlyParamsPtr
-  );
-
-AGESA_STATUS
-GnbInitAtPost (
-  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
-  );
-
-VOID
-GnbInitDataStructAtEnvDef (
-  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
-  IN      AMD_ENV_PARAMS          *EnvParamsPtr
-  );
-
-AGESA_STATUS
-GnbInitAtEnv (
-  IN       AMD_ENV_PARAMS          *EnvParamsPtr
-  );
-
-AGESA_STATUS
-GnbInitAtMid (
-  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
-  );
-
-AGESA_STATUS
-GnbInitAtLate (
-  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
-  );
-
-AGESA_STATUS
-GnbInitAtPostAfterDram (
-  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
-  );
-
-AGESA_STATUS
-AmdGnbRecovery (
-  IN       AMD_CONFIG_PARAMS        *StdHeader
-  );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
deleted file mode 100644
index 0b3ff08..0000000
--- a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- *
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  GNB
- * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Reset Stub
- *
- *
- *
- * @param[in] StdHeader     Standard configuration header
- * @retval    AGESA_STATUS  Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtReset (
-  IN      AMD_CONFIG_PARAMS       *StdHeader
-  )
-{
-
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Early Stub
- *
- *
- *
- * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
- * @retval        AGESA_STATUS      Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtEarly (
-  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
-  )
-{
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Default constructor of GNB configuration at Env
- *
- *
- *
- * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
- * @param[in] EnvParamsPtr        Pointer to env configuration params.
- */
-VOID
-GnbInitDataStructAtEnvDef (
-  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
-  IN      AMD_ENV_PARAMS          *EnvParamsPtr
-  )
-{
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Env
- *
- *
- *
- * @param[in] EnvParamsPtr        Pointer to env configuration params.
-* @retval     AGESA_STATUS        Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtEnv (
-  IN       AMD_ENV_PARAMS          *EnvParamsPtr
-  )
-{
-
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post
- *
- *
- *
- * @param[in,out] PostParamsPtr    Pointer to Post configuration params.
- * @retval        AGESA_STATUS     Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtPost (
-  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
-  )
-{
-
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Mid post
- *
- *
- *
- * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
- * @retval        AGESA_STATUS    Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtMid (
-  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
-  )
-{
-
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Late post
- *
- *
- *
- * @param[in,out] LateParamsPtr    Pointer to late configuration params.
- * @retval        AGESA_STATUS     Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtLate (
-  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
-  )
-{
-
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * AmdGnbRecovery
- *
- *
- *
- * @param[in] StdHeader     Standard configuration header
- * @retval    AGESA_STATUS  Always succeeds
- */
-AGESA_STATUS
-AmdGnbRecovery (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  return  AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post after DRAM init
- *
- *
- *
- * @param[in]     PostParamsPtr Pointer to post configuration parameters
- * @retval                      Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtPostAfterDram (
-  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
-  )
-{
-  return  AGESA_SUCCESS;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Include/Ids.h b/src/vendorcode/amd/agesa/Include/Ids.h
deleted file mode 100644
index cbd0b13..0000000
--- a/src/vendorcode/amd/agesa/Include/Ids.h
+++ /dev/null
@@ -1,927 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS Routines
- *
- * Contains AMD AGESA Integrated Debug Macros
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  IDS
- * @e \$Revision: 38634 $   @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-  /* Macros to aid debugging */
-  /* These definitions expand to zero (0) bytes of code when disabled */
-
-#ifndef _IDS_H_
-#define _IDS_H_
-
-#undef FALSE
-#undef TRUE
-#define FALSE 0
-#define TRUE  1
-// Proto type for optionsids.h
-typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
-#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
-#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
-
-#define IDS_STRINGIZE(a) #a ///< for define stringize macro
-/**
- *  IDS Option Hook Points
- *
- *  These are the values to indicate hook point in AGESA for IDS Options.
- *
- */
-typedef enum {                        //vv- for debug reference only
-  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
-                                          ///<   IDS Object is initialized.
-                                          ///<   Override CPU Core Leveling Mode.
-                                          ///<   Set P-State in Post
-  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
-  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
-                                          ///< It will be used to control the following tables.
-                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
-                                          ///<   ACPI SRAT Table
-                                          ///<   ACPI SLIT Table
-                                          ///<   ACPI WHEA Table
-                                          ///<   DMI Table
-  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
-  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
-  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
-  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
-                                          ///<   Control Interleaving and DRAM memory hole
-                                          ///<   Override the setting of ECC Control
-                                          ///<   Override the setting of Online Spare Rank
-  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
-  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
-  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
-  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
-  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
-  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
-  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
-  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
-  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
-  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
-  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
-  IDS_BEFORE_WARM_RESET ,             ///< 12 Override PCI or MSR Registers Before Warm Reset
-  IDS_BEFORE_MEM_INIT,                ///< 13 Override PCI or MSR Registers Before Memory Init
-  IDS_BEFORE_PCI_INIT,                ///< 14 Override PCI or MSR Registers Before PCI Init
-  IDS_BEFORE_OS,                      ///< 15 Override PCI or MSR Registers Before booting to OS
-  IDS_UCODE,                          ///< 16 Enable or Disable microcode patching
-  IDS_BEFORE_AP_EARLY_HALT,           ///< 17 Option Hook Point before AP early halt
-
-  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
-  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
-
-  // All the above timing point is used by BVM, their value should never be changed
-  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
-  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
-  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
-                                          ///< Dram Controller, Drive Strength and DQS Timing
-  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
-  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
-  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
-  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
-  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
-  IDS_ECC,                            ///< 48 override ECC parameter
-  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
-  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
-  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
-  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
-  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
-  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
-  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
-  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
-  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
-  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
-  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
-  IDS_PHY_DLL_STANDBY_CTRL,           ///< 54 Enable/Disable Phy DLL standby feature
-  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
-  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
-  IDS_MEM_IGNORE_ERROR,               ///< 57 Ignore error and do not do fatal exit in memory
-  IDS_GNB_SMU_SERVICE_CONFIG,         ///< 58 Config GNB SMU service
-  IDS_GNB_ORBDYNAMIC_WAKE,            ///< 59 config GNB dynamic wake
-  IDS_GNB_PLATFORMCFG_OVERRIDE,       ///< 5a override ids gnb platform config
-  IDS_GNB_LCLK_DPM_EN,                ///< 5b override GNB LCLK DPM configuration
-  IDS_GNB_LCLK_DEEP_SLEEP,            ///< 5c override GNB LCLK DPM deep sleep
-  IDS_GNB_CLOCK_GATING,               ///< 5d Override GNB Clock gating config
-  IDS_NB_PSTATE_DIDVID,               ///< 5e Override NB P-state settings
-  IDS_CPB_CTRL,                       ///< 5f Config the Core peformance boost feature
-  IDS_HTC_CTRL,                       ///< 60 Hook for Hardware Thermal Control
-  IDS_CC6_WORKAROUND,                 ///< 61 Hook for skip CC6 work around
-  IDS_MEM_MR0,                        ///< 62 Hook for override Memory Mr0 register
-  IDS_REG_TABLE,                      ///< 63 Hook for add IDS register table to the loop
-  IDS_NBBUFFERALLOCATIONATEARLY,      ///< 64 Hook for override North bridge bufer allocation
-  IDS_BEFORE_S3_SPECIAL,              ///< 65 Hook to bypass S3 special functions
-  IDS_SET_PCI_REGISTER_ENTRY,         ///< 66 Hook to SetRegisterForPciEntry
-  IDS_ERRATUM463_WORKAROUND,          ///< 67 Hook to Erratum 463 workaround
-  IDS_BEFORE_MEMCLR,                  ///< 68 Hook before set Memclr bit
-  IDS_OVERRIDE_IO_CSTATE,             ///< 69 Hook for override io C-state setting
-  IDS_NBPSDIS_OVERRIDE,               ///< 6a Hook for override NB pstate disable setting
-  IDS_NBPS_REG_OVERRIDE,              ///< 6b Hook for override Memory NBps reg
-  IDS_LOW_POWER_PSTATE,               ///< 6c Hook for disalbe Low power_Pstates feature
-  IDS_CST_CREATE,                     ///< 6d Hook for create _CST
-  IDS_CST_SIZE,                       ///< 6e Hook for get _CST size
-  IDS_ENFORCE_VDDIO,                  ///< 6f Hook to override VDDIO
-  IDS_SKIP_PERFORMANCE_OPT,           ///< 70 Hook to skip performance optimization
-  IDS_INIT_MEM_REG_TABLE,             ///< 71 Hook for init memory register table
-  IDS_SKIP_FUSED_MAX_RATE             ///< 72 Hook to skip fused max rate cap
-} AGESA_IDS_OPTION;
-
-#include "OptionsIds.h"
-#include "Filecode.h"
-
-/* Initialize IDS controls */
-#ifndef IDSOPT_IDS_ENABLED
-  #define IDSOPT_IDS_ENABLED        FALSE
-#endif
-
-#ifndef IDSOPT_CONTROL_ENABLED
-  #define IDSOPT_CONTROL_ENABLED    FALSE
-#endif
-
-#ifndef IDSOPT_TRACING_ENABLED
-  #define IDSOPT_TRACING_ENABLED    FALSE
-#endif
-
-#ifndef IDSOPT_TRACE_USER_OPTIONS
-  #define IDSOPT_TRACE_USER_OPTIONS TRUE
-#endif
-
-#ifndef IDSOPT_PERF_ANALYSIS
-  #define IDSOPT_PERF_ANALYSIS      FALSE
-#endif
-
-#ifndef IDSOPT_HEAP_CHECKING
-  #define IDSOPT_HEAP_CHECKING           FALSE
-#endif
-
-#ifndef IDSOPT_ASSERT_ENABLED
-  #define IDSOPT_ASSERT_ENABLED         FALSE
-#endif
-
-#ifndef IDSOPT_ERROR_TRAP_ENABLED
-  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
-#endif
-
-#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
-  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
-#endif
-
-#ifndef IDSOPT_DEBUG_CODE_ENABLED
-  #define IDSOPT_DEBUG_CODE_ENABLED   FALSE
-#endif
-
-#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
-  #define IDSOPT_C_OPTIMIZATION_DISABLED   FALSE
-#endif
-
-#if IDSOPT_IDS_ENABLED == FALSE
-  #undef  IDSOPT_CONTROL_ENABLED
-  #undef  IDSOPT_TRACING_ENABLED
-  #undef  IDSOPT_PERF_ANALYSIS
-  #undef  IDSOPT_HEAP_CHECKING
-  #undef  IDSOPT_ASSERT_ENABLED
-  #undef  IDSOPT_ERROR_TRAP_ENABLED
-  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
-  #undef  IDSOPT_DEBUG_CODE_ENABLED
-  #undef  IDSOPT_TRACE_USER_OPTIONS
-
-  #define IDSOPT_CONTROL_ENABLED    FALSE
-  #define IDSOPT_TRACING_ENABLED    FALSE
-  #define IDSOPT_PERF_ANALYSIS      FALSE
-  #define IDSOPT_HEAP_CHECKING      FALSE
-  #define IDSOPT_ASSERT_ENABLED     FALSE
-  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
-  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
-  #define IDSOPT_DEBUG_CODE_ENABLED FALSE
-  #define IDSOPT_TRACE_USER_OPTIONS FALSE
-#endif
-
-/**
- *  Make a Progress Report to the User.
- *
- *  This Macro is always enabled. The default action is to write the TestPoint value
- *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
- *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
- *  in OptionsIds.h in their build tip.
- *
- *  @param[in]      TestPoint       The value for display indicating progress
- *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
- *
- **/
-
-#define AGESA_TESTPOINT(TestPoint, StdHeader)
-
-#ifndef IDS_DEBUG_PORT
-  #define IDS_DEBUG_PORT  0x80
-#endif
-
-/**
- * @def STOP_HERE
- *  (macro) - Causes program to halt. This is @b only for use during active debugging .
- *
- *  Causes the program to halt and display the file number of the source of the
- *  halt (displayed in decimal).
- *
- **/
-#if IDSOPT_IDS_ENABLED == TRUE
-  #ifdef STOP_CODE
-    #undef STOP_CODE
-  #endif
-  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
-                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
-                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
-  #define STOP_HERE
-#else
-  #define STOP_HERE
-#endif
-
-/**
- * @def ASSERT
- *  Test an assertion that the given statement is True.
- *
- *  The statement is evaluated to a boolean value. If the statement is True,
- *  then no action is taken (no error). If the statement is False, a error stop
- *  is generated to halt the program. Used for testing for fatal errors that
- *  must be resolved before production. This is used to do parameter checks,
- *  bounds checking, range checks and 'sanity' checks.
- *
- * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
- *
- **/
-#ifndef ASSERT
-  #if IDSOPT_ASSERT_ENABLED == TRUE
-    #ifdef STOP_CODE
-      #undef STOP_CODE
-    #endif
-    #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
-                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
-                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
-
-    #define ASSERT(conditional)
-  #else
-    #define ASSERT(conditional)
-  #endif
-#endif
-
-#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
-  #undef  IDSOPT_ERROR_TRAP_ENABLED
-  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
-  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
-#else
-  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
-#endif
-/**
- * @def DEBUG_CODE
- * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
- *
- */
-#ifndef DEBUG_CODE
-  #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
-    #define  DEBUG_CODE(Code)
-  #else
-    #define  DEBUG_CODE(Code)
-  #endif
-#endif
-
-/**
- * @def IDS_ERROR_TRAP
- * Trap AGESA Error events with stop code display.
- *
- * Works similarly to use of "ASSERT (FALSE);"
- *
- */
-#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
-  #ifdef STOP_CODE
-    #undef STOP_CODE
-  #endif
-  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
-                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
-                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
-
-  #define IDS_ERROR_TRAP
-#else
-  #define IDS_ERROR_TRAP
-#endif
-
-///give the extended Macro default value
-#ifndef __IDS_EXTENDED__
-  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
-  #define IDS_INITIAL_F10_PM_STEP
-  #define IDS_INITIAL_F12_PM_STEP
-  #define IDS_INITIAL_F14_PM_STEP
-  #define IDS_INITIAL_F15_PM_STEP
-  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
-  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
-  #define IDS_EXTENDED_HEAP_SIZE 0
-  #define IDS_EXT_INCLUDE_F10(file)
-  #define IDS_EXT_INCLUDE_F12(file)
-  #define IDS_EXT_INCLUDE_F14(file)
-  #define IDS_EXT_INCLUDE_F15(file)
-  #define IDS_EXT_INCLUDE(file)
-#endif
-
-#ifndef IDS_NUM_NV_ITEM
-  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
-#endif
-
-#if IDSOPT_CONTROL_ENABLED == TRUE
-  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
-
-  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
-#else
-  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
-
-  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
-#endif
-
-/**
- *  Macro to add a *skip* hook for IDS options
- *
- *  The default minimal action is to do nothing and there is no any code to increase.
- *  For debug environments, IDS dispatcher function will be called to perform
- *  the detailed action and to skip AGESA code if necessary.
- *
- * @param[in]       IdsOption       IDS Option ID for this hook point
- * @param[in, out]  DataPtr         Data Pointer to override
- * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
- *
- *
- **/
-
-#if IDSOPT_CONTROL_ENABLED == TRUE
-  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
-#else
-  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
-#endif
-
-/**
- *  Macro to add a heap manager routine
- *
- *  when memory is allocated the heap manager actually allocates two extra dwords of data,
- *  one dword buffer before the actual memory, and one dword afterwards.
- *  a complete heap walk and check to be performed at any time.
- *  it would ASSERT if the heap is corrupt
- *
- * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
- *
- *
- **/
-
-// Heap debug feature
-#define SENTINEL_BEFORE_VALUE 0x64616548    // "Head"
-#define SENTINEL_AFTER_VALUE  0x6C696154    // "Tail"
-#if IDSOPT_IDS_ENABLED == TRUE
-  #if IDSOPT_HEAP_CHECKING == TRUE
-    #define SIZE_OF_SENTINEL  0
-    #define NUM_OF_SENTINEL   0
-    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
-    #define SET_SENTINEL_AFTER(NodePtr)
-    #define Heap_Check(stdheader)
-  #else
-    #define SIZE_OF_SENTINEL  0
-    #define NUM_OF_SENTINEL   0
-    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
-    #define SET_SENTINEL_AFTER(NodePtr)
-    #define Heap_Check(stdheader)
-  #endif
-#else
-  #define SIZE_OF_SENTINEL    0
-  #define NUM_OF_SENTINEL     0
-  #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
-  #define SET_SENTINEL_AFTER(NodePtr)
-  #define Heap_Check(stdheader)
-#endif
-
-
- //Note a is from 0 to 63
-#define DEBUG_PRINT_SHIFT(a)   ((UINT64)1 << a)
-//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
-//Memory Masks
-#define MEM_SETREG                                  DEBUG_PRINT_SHIFT (0)
-#define MEM_GETREG                                  DEBUG_PRINT_SHIFT (1)
-#define MEM_FLOW                                    DEBUG_PRINT_SHIFT (2)
-#define MEM_STATUS                                  DEBUG_PRINT_SHIFT (3)
-#define MEMORY_TRACE_RSV1                           DEBUG_PRINT_SHIFT (4)
-#define MEMORY_TRACE_RSV2                           DEBUG_PRINT_SHIFT (5)
-#define MEMORY_TRACE_RSV3                           DEBUG_PRINT_SHIFT (6)
-#define MEMORY_TRACE_RSV4                           DEBUG_PRINT_SHIFT (7)
-#define MEMORY_TRACE_RSV5                           DEBUG_PRINT_SHIFT (8)
-#define MEMORY_TRACE_RSV6                           DEBUG_PRINT_SHIFT (9)
-
-
-
-//CPU Masks
-#define CPU_TRACE                                   DEBUG_PRINT_SHIFT (10)
-#define CPU_TRACE_RSV1                              DEBUG_PRINT_SHIFT (11)
-#define CPU_TRACE_RSV2                              DEBUG_PRINT_SHIFT (12)
-#define CPU_TRACE_RSV3                              DEBUG_PRINT_SHIFT (13)
-#define CPU_TRACE_RSV4                              DEBUG_PRINT_SHIFT (14)
-#define CPU_TRACE_RSV5                              DEBUG_PRINT_SHIFT (15)
-#define CPU_TRACE_RSV6                              DEBUG_PRINT_SHIFT (16)
-#define CPU_TRACE_RSV7                              DEBUG_PRINT_SHIFT (17)
-#define CPU_TRACE_RSV8                              DEBUG_PRINT_SHIFT (18)
-#define CPU_TRACE_RSV9                              DEBUG_PRINT_SHIFT (19)
-
-//GNB Masks
-#define GNB_TRACE                                   DEBUG_PRINT_SHIFT (20)
-#define PCIE_MISC                                   DEBUG_PRINT_SHIFT (21)
-#define PCIE_PORTREG_TRACE                          DEBUG_PRINT_SHIFT (22)
-#define PCIE_HOSTREG_TRACE                          DEBUG_PRINT_SHIFT (23)
-#define GNB_TRACE_RSV2                              DEBUG_PRINT_SHIFT (24)
-#define NB_MISC                                     DEBUG_PRINT_SHIFT (25)
-#define GNB_TRACE_RSV3                              DEBUG_PRINT_SHIFT (26)
-#define GFX_MISC                                    DEBUG_PRINT_SHIFT (27)
-#define NB_SMUREG_TRACE                             DEBUG_PRINT_SHIFT (28)
-#define GNB_TRACE_RSV1                              DEBUG_PRINT_SHIFT (29)
-
-//HT Masks
-#define HT_TRACE                                    DEBUG_PRINT_SHIFT (30)
-#define HT_TRACE_RSV1                               DEBUG_PRINT_SHIFT (31)
-#define HT_TRACE_RSV2                               DEBUG_PRINT_SHIFT (32)
-#define HT_TRACE_RSV3                               DEBUG_PRINT_SHIFT (33)
-#define HT_TRACE_RSV4                               DEBUG_PRINT_SHIFT (34)
-#define HT_TRACE_RSV5                               DEBUG_PRINT_SHIFT (35)
-#define HT_TRACE_RSV6                               DEBUG_PRINT_SHIFT (36)
-#define HT_TRACE_RSV7                               DEBUG_PRINT_SHIFT (37)
-#define HT_TRACE_RSV8                               DEBUG_PRINT_SHIFT (38)
-#define HT_TRACE_RSV9                               DEBUG_PRINT_SHIFT (39)
-
-//FCH Masks
-#define FCH_TRACE                                    DEBUG_PRINT_SHIFT (40)
-#define FCH_TRACE_RSV1                               DEBUG_PRINT_SHIFT (41)
-#define FCH_TRACE_RSV2                               DEBUG_PRINT_SHIFT (42)
-#define FCH_TRACE_RSV3                               DEBUG_PRINT_SHIFT (43)
-#define FCH_TRACE_RSV4                               DEBUG_PRINT_SHIFT (44)
-#define FCH_TRACE_RSV5                               DEBUG_PRINT_SHIFT (45)
-#define FCH_TRACE_RSV6                               DEBUG_PRINT_SHIFT (46)
-#define FCH_TRACE_RSV7                               DEBUG_PRINT_SHIFT (47)
-#define FCH_TRACE_RSV8                               DEBUG_PRINT_SHIFT (48)
-#define FCH_TRACE_RSV9                               DEBUG_PRINT_SHIFT (49)
-
-//Other Masks
-#define MAIN_FLOW                                    DEBUG_PRINT_SHIFT (50)
-#define EVENT_LOG                                    DEBUG_PRINT_SHIFT (51)
-#define PERFORMANCE_ANALYSE                          DEBUG_PRINT_SHIFT (52)
-
-//Ids Masks
-#define IDS_TRACE                                    DEBUG_PRINT_SHIFT (53)
-#define IDS_REG                                      DEBUG_PRINT_SHIFT (54)
-#define IDS_TRACE_RSV2                               DEBUG_PRINT_SHIFT (55)
-#define IDS_TRACE_RSV3                               DEBUG_PRINT_SHIFT (56)
-
-//S3
-#define S3_TRACE                                     DEBUG_PRINT_SHIFT (57)
-
-
-//Reserved
-#define TRACE_RSV1                                   DEBUG_PRINT_SHIFT (58)
-#define TRACE_RSV2                                   DEBUG_PRINT_SHIFT (59)
-#define TRACE_RSV3                                   DEBUG_PRINT_SHIFT (60)
-#define TRACE_RSV4                                   DEBUG_PRINT_SHIFT (61)
-#define TRACE_RSV5                                   DEBUG_PRINT_SHIFT (62)
-#define TRACE_RSV6                                   DEBUG_PRINT_SHIFT (63)
-
-#define GNB_TRACE_DEFAULT   0
-
-#define GNB_TRACE_REG       0
-
-#define GNB_TRACE_ALL       0
-
-#define CPU_TRACE_ALL       0
-
-#define MEMORY_TRACE_ALL    0
-
-#define HT_TRACE_ALL        0
-
-#define FCH_TRACE_ALL       0
-
-#define IDS_TRACE_ALL       0
-
-#define OTHER_TRACE_ALL     0
-
-#define TRACE_MASK_ALL (0ull)
-#ifndef IDS_DEBUG_PRINT_MASK
-  #define IDS_DEBUG_PRINT_MASK 0
-#endif
-
-
-/**
- *  Macro to add HDT OUT
- *
- *  The default minimal action is to do nothing and there is no any code to increase.
- *  For debug environments, the debug information can be displayed in HDT or other
- *  devices.
- *
- **/
-#if IDSOPT_IDS_ENABLED == TRUE
-  #if IDSOPT_TRACING_ENABLED == TRUE
-    #define IDS_HDT_CONSOLE_INIT(x)
-    #define IDS_HDT_CONSOLE_EXIT(x)
-    #define IDS_HDT_CONSOLE_S3_EXIT(x)
-    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
-
-    #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
-      #ifdef __GNUC__
-        #define IDS_HDT_CONSOLE(f, s, ...)
-      #else
-        #define IDS_HDT_CONSOLE(f, s, ...)
-      #endif
-    #else
-      #pragma warning(disable: 4127)
-      #ifdef __GNUC__
-        #define IDS_HDT_CONSOLE(f, s, ...)
-      #else
-        #define IDS_HDT_CONSOLE(f, s, ...)
-      #endif
-    #endif
-
-    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
-    #define IDS_HDT_CONSOLE_ASSERT(x)
-    #define IDS_FUNCLIST_ADDR                   NULL
-    #define IDS_FUNCLIST_EXTERN()
-    #define IDS_TIMEOUT_CTL(t)
-    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
-    #define CONSOLE(s, ...)
-  #else
-    #define IDS_HDT_CONSOLE_INIT(x)
-    #define IDS_HDT_CONSOLE_EXIT(x)
-    #define IDS_HDT_CONSOLE_S3_EXIT(x)
-    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
-    #define IDS_HDT_CONSOLE(f, s, ...)
-    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
-    #define IDS_HDT_CONSOLE_ASSERT(x)
-    #define IDS_FUNCLIST_ADDR                 NULL
-    #define IDS_FUNCLIST_EXTERN()
-    #define IDS_TIMEOUT_CTL(t)
-    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
-    #define CONSOLE(s, ...)
-  #endif
-#else
-  #define IDS_HDT_CONSOLE_INIT(x)
-  #define IDS_HDT_CONSOLE_EXIT(x)
-  #define IDS_HDT_CONSOLE_S3_EXIT(x)
-  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
-  #define IDS_HDT_CONSOLE(f, s, ...)
-  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
-  #define IDS_HDT_CONSOLE_ASSERT(x)
-  #define IDS_FUNCLIST_ADDR                   NULL
-  #define IDS_FUNCLIST_EXTERN()
-  #define IDS_TIMEOUT_CTL(t)
-  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
-  #define CONSOLE(s, ...)
-#endif
-
-#define IDS_TRACE_SHOW_BLD_OPT_CFG  IDSOPT_TRACE_USER_OPTIONS
-
-#if IDSOPT_PERF_ANALYSIS == TRUE
-  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
-  #define IDS_PERF_ANALYSE(StdHeader)
-  #define IDS_PERF_TIME_MEASURE(StdHeader)
-#else
-  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
-  #define IDS_PERF_ANALYSE(StdHeader)
-  #define IDS_PERF_TIME_MEASURE(StdHeader)
-#endif
-
-///For IDS feat use
-#define IDS_FAMILY_ALL  0x0ull
-#define IDS_BSP_ONLY    TRUE
-#define IDS_ALL_CORES   FALSE
-
-#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_CONTROL_IDSLIB_FILECODE
-
-#define IDS_CALLOUT_INIT      0x00       ///< The function data of IDS callout function of initialization.
-
-#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE      0x00       ///< The function data of IDS callout function of GNB pp fuse table.
-#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG      0x00       ///< The function data of IDS callout function of GNB integrated table.
-#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG      0x00       ///< The function data of IDS callout function of GNB NB power gate config.
-#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG      0x00       ///< The function data of IDS callout function of GNB PCIE power gateconfig.
-#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG      0x00       ///< The function data of IDS callout function of GNB pcie platform config.
-#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG           0x00       ///< The function data of IDS callout function of GNB pcie PHY config.
-#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE           0x00       ///< The function data of IDS callout function of GNB GMM register override
-
-/// Function entry for HDT script to call
-typedef struct _SCRIPT_FUNCTION {
-  UINT32  FuncAddr;       ///< Function address in ROM
-  CHAR8   FuncName[40];   ///< Function name
-} SCRIPT_FUNCTION;
-
-/// Data Structure for Mem ECC parameter override
-typedef struct {
-  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
-  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
-  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
-  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
-  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
-  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
-  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
-} ECC_OVERRIDE_STRUCT;
-
-
-
-
-/**
- *  AGESA Test Points
- *
- *  These are the values displayed to the user to indicate progress through boot.
- *  These can be used in a debug environment to stop the debugger at a specific
- *  test point:
- *  For SimNow!, this command
- *      bi 81 w vb 49
- *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
- *
- */
-typedef enum {
-  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
-
-  // Memory test points
-  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
-  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
-  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
-  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
-  TpProcMemSPDChecking,               ///< 05 ..
-  TpProcMemModeChecking,              ///< 06 ..
-  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
-  TpProcMemSpdTiming,                 ///< 08 ..
-  TpProcMemDramMapping,               ///< 09 ..
-  TpProcMemPlatformSpecificConfig,    ///< 0A ..
-  TPProcMemPhyCompensation,           ///< 0B ..
-  TpProcMemStartDcts,                 ///< 0C ..
-  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
-  TpProcMemPhyFenceTraining,          ///< 0E ..
-  TpProcMemSynchronizeDcts,           ///< 0F ..
-  TpProcMemSystemMemoryMapping,       ///< 10 ..
-  TpProcMemMtrrConfiguration,         ///< 11 ..
-  TpProcMemDramTraining,              ///< 12 ..
-  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
-  TpProcMemWriteLevelizationTraining, ///< 14 ..
-  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
-  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
-  TpProcMemWlDimmConfig,              ///< 17 .. Target DIMM configured
-  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
-  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
-  TpProcMemReceiverEnableTraining,    ///< 1A ..
-  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
-  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
-  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
-  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
-  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
-  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
-  TpProcMemReceiveDqsTraining,        ///< 21 ..
-  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
-  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
-  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
-  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
-  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
-  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
-  TpProcMemRcvDqsResults,             ///< 28 .. Update results
-  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
-  TpProcMemTransmitDqsTraining,       ///< 2A ..
-  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
-  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
-  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
-  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
-  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
-  TpProcMemTxDqResults,               ///< 30 .. Update results
-  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
-  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
-  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
-  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
-  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
-  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
-  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
-  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
-  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
-  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
-  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
-  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
-  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
-  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
-  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
-  TpProcMemBeforeAgesaHookBeforeDramInit,     ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
-  TpProcMemAfterAgesaHookBeforeDramInit,      ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
-  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
-  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
-  TpProcMemBeforeAgesaHookBeforeExitSelfRef,     ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
-  TpProcMemAfterAgesaHookBeforeExitSelfRef,      ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
-  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
-  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
-  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
-  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
-  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
-  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
-  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
-  TpProcMemMemClr,                    ///< 4D .. Before MemClr
-  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
-  TpProcMemDmi,                       ///< 4F .. Before DMI
-  TpProcMemEnd,                       ///< 50 .. End of memory code
-
-  // CPU test points
-  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
-  TpProcCpuEntryPstate,               ///< 52 .. Entry point GenerateSsdt
-  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
-  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
-  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
-  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
-  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
-  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
-  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
-  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
-  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
-  TpProcCpuBeforePMFeatureInit,       ///< 5C .. BeforePM feature dispatch point
-  TpProcCpuPowerMgmtInit,             ///< 5D .. Power Management table processing
-  TpProcCpuEarlyFeatureInit,          ///< 5E .. Early feature dispatch point
-  TpProcCpuCoreLeveling,              ///< 5F .. Core Leveling
-  TpProcCpuApMtrrSync,                ///< 60 .. AP MTRR sync up
-  TpProcCpuPostFeatureInit,           ///< 61 .. POST feature dispatch point
-  TpProcCpuFeatureLeveling,           ///< 62 .. CPU Feature Leveling
-  TpProcCpuBeforeAllocateWheaBuffer,  ///< 63 .. Before the WHEA init code calls out to allocate a buffer
-  TpProcCpuAfterAllocateWheaBuffer,   ///< 64 .. After the WHEA init code calls out to allocate a buffer
-  TpProcCpuBeforeAllocateSratBuffer,  ///< 65 .. Before the SRAT init code calls out to allocate a buffer
-  TpProcCpuAfterAllocateSratBuffer,   ///< 66 .. After the SRAT init code calls out to allocate a buffer
-  TpProcCpuBeforeLocateSsdtBuffer,    ///< 67 .. Before the P-state init code calls out to locate a buffer
-  TpProcCpuAfterLocateSsdtBuffer,     ///< 68 .. After the P-state init code calls out to locate a buffer
-  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 69 .. Before the P-state init code calls out to allocate a buffer
-  TpProcCpuAfterAllocateSsdtBuffer,   ///< 6A .. After the P-state init code calls out to allocate a buffer
-
-  // HT test points
-  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
-  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
-  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
-  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
-  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
-  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
-  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
-  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
-  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
-  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
-  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
-  TpProcHtDone,                       ///< 7C .. HT Init complete
-  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
-  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
-
-  StartNbTestPoints = 0x90,           ///< 90 Entry used for range testing for @b NorthBridge related TPs
-  TpNbxxx,                            ///< 91 .
-  EndNbTestPoints,                    ///< 92 End of TP range for NB
-
-  StartSbTestPoints = 0xB0,           ///< B0 Entry used for range testing for @b SouthBridge related TPs
-  TpSbxxx,                            ///< B1 .
-  EndSbTestPoints,                    ///< B2 End of TP range for SB
-
-  // Interface test points
-  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
-  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
-  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
-  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
-  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
-  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
-  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
-  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
-  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
-  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
-  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
-  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
-  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
-  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
-  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
-  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
-  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
-  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
-  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
-  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
-  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
-  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
-  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
-  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
-  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
-  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
-  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
-  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
-  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
-  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
-  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
-  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
-  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
-  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
-  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
-  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
-  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
-  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
-  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
-  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
-  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
-  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
-  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
-  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
-  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
-  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
-  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
-  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
-  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
-  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
-  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
-  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
-  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
-  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
-  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
-  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
-  TpPerfUnit,                              ///< F8 .. The Unit of performance measure.
-  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
-} AGESA_TP;
-
-///Ids Feat description
-typedef enum {
-  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
-  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
-  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
-  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
-  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
-  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
-  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
-  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
-  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
-  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
-  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
-  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
-  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
-  IDS_FEAT_GNB_PLATFORMCFG,                 ///< Feat for override GNB platform config
-  IDS_FEAT_CPB_CTRL,             ///< Feat for Config the Core peformance boost feature
-  IDS_FEAT_HTC_CTRL,            ///< Feat for Hardware Thermal Control
-  IDS_FEAT_MEMORY_MAPPING,              ///< Feat for Memory Mapping
-  IDS_FEAT_POWER_POLICY,              ///< Feat for Power Policy
-  IDS_FEAT_END = 0xFF                      ///< End of Common feat
-} IDS_FEAT;
-
-typedef IDS_STATUS IDS_COMMON_FUNC (
-  IN OUT   VOID *DataPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
-  IN       IDS_NV_ITEM *IdsNvPtr
-  );
-
-typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
-
-/// Data Structure of IDS Feature block
-typedef  struct _IDS_FEAT_STRUCT {
-  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
-  BOOLEAN IsBsp;          ///< swith for Bsp check
-  AGESA_IDS_OPTION IdsOption;   ///< IDS option
-  UINT64 CpuFamily;      ///<
-  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
-} IDS_FEAT_STRUCT;
-
-
-/// Data Structure of IDS option
-typedef  struct _IDS_OPTION_STRUCT {
-  AGESA_IDS_OPTION idsoption;   ///< IDS option
-  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
-} IDS_OPTION_STRUCT;
-
-/// Data Structure of IDS option table
-typedef struct _IDS_OPTION_STRUCT_TBL {
-  UINT8 version;      ///<Version of IDS option table
-  UINT16 size;        ///<Size of IDS option table
-  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
-} IDS_OPTION_STRUCT_TBL;
-
-#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/Include/IdsHt.h b/src/vendorcode/amd/agesa/Include/IdsHt.h
deleted file mode 100644
index 02be40b..0000000
--- a/src/vendorcode/amd/agesa/Include/IdsHt.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS HyperTransport Definitions
- *
- * Contains AMD AGESA Integrated Debug HT related items.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  IDS
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _IDS_HT_H_
-#define _IDS_HT_H_
-
-// Frequency equates for call backs which take an actual frequency setting
-#define HT_FREQUENCY_200M            0
-#define HT_FREQUENCY_400M            2
-#define HT_FREQUENCY_600M            4
-#define HT_FREQUENCY_800M            5
-#define HT_FREQUENCY_1000M           6
-#define HT_FREQUENCY_1200M           7
-#define HT_FREQUENCY_1400M           8
-#define HT_FREQUENCY_1600M           9
-#define HT_FREQUENCY_1800M           10
-#define HT_FREQUENCY_2000M           11
-#define HT_FREQUENCY_2200M           12
-#define HT_FREQUENCY_2400M           13
-#define HT_FREQUENCY_2600M           14
-#define HT_FREQUENCY_2800M           17
-#define HT_FREQUENCY_3000M           18
-#define HT_FREQUENCY_3200M           19
-#define HT_FREQUENCY_3600M           20
-
-/**
- * HT IDS: HT Link Port Override params.
- *
- * Provide an absolute override of HT Link Port settings.  No checking is done that
- * the settings obey limits or capabilities, this responsibility rests with the user.
- *
- * Rules for values of structure items:
- * - Socket
- *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
- *   - HT_LIST_MATCH_ANY == Match Any Socket
- *   - 0 .. 7 == The matching socket
- * - Link
- *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
- *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
- *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
- * - Frequency
- *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
- *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
- * - Widthin
- *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
- *   - 2, 4, 8, 16, 32 == The width value to use
- * - Widthout
- *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
- *   - 2, 4, 8, 16, 32 == The width value to use
- */
-typedef struct {
-  // Match Fields
-  UINT8       Socket;      ///< The Socket which this port is on.
-  UINT8       Link;        ///< The port for this package link on that socket.
-  // Override fields
-  UINT8       Frequency;   ///< Absolutely override the port's frequency.
-  UINT8       WidthIn;     ///< Absolutely override the port's width.
-  UINT8       WidthOut;    ///< Absolutely override the port's width.
-} HTIDS_PORT_OVERRIDE;
-
-/**
- * A list of port overrides to search.
- */
-typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
-VOID
-HtIdsGetPortOverride (
-  IN       BOOLEAN                    IsSourcePort,
-  IN OUT   PORT_DESCRIPTOR            *Port0,
-  IN OUT   PORT_DESCRIPTOR            *Port1,
-  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
-  IN       STATE_DATA                 *State
-  );
-
-typedef
-VOID
-F_HtIdsGetPortOverride (
-  IN       BOOLEAN                    IsSourcePort,
-  IN OUT   PORT_DESCRIPTOR            *Port0,
-  IN OUT   PORT_DESCRIPTOR            *Port1,
-  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
-  IN       STATE_DATA                 *State
-  );
-typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
-#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/Include/LynxInstall.h b/src/vendorcode/amd/agesa/Include/LynxInstall.h
deleted file mode 100644
index 02338f9..0000000
--- a/src/vendorcode/amd/agesa/Include/LynxInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Lynx platform solution
- *
- * This file generates the defaults tables for the "Lynx" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37651 $   @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "LlanoPI "
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Lynx solution is defined to be family 0x12 in the FM1 socket.
-#define INSTALL_FM1_SOCKET_SUPPORT       TRUE
-#define INSTALL_FAMILY_12_SUPPORT        TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
deleted file mode 100644
index 881f32b..0000000
--- a/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Maranello platform solution
- *
- * This file generates the defaults tables for the "Maranello" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                    // This is the delivery package title, "MarG34PI"
-                    // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-
-                    // This is the release version number of the AGESA component
-                    // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-
-// The Maranello solution is defined to be families 0x10 and 0x15 in the G34 socket.
-#define INSTALL_G34_SOCKET_SUPPORT       TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-#define INSTALL_FAMILY_15_SUPPORT        TRUE
-
-#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
-  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
-    #undef INSTALL_FAMILY_10_SUPPORT
-    #define INSTALL_FAMILY_10_SUPPORT     FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
-  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
-    #undef INSTALL_FAMILY_15_SUPPORT
-    #define INSTALL_FAMILY_15_SUPPORT     FALSE
-  #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0xFF)
-#define DFLT_SCRUB_L2_RATE              (0x10)
-#define DFLT_SCRUB_L3_RATE              (0x10)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/NileInstall.h b/src/vendorcode/amd/agesa/Include/NileInstall.h
deleted file mode 100644
index dac582e..0000000
--- a/src/vendorcode/amd/agesa/Include/NileInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Nile platform solution
- *
- * This file generates the defaults tables for the "Nile" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-                  // This is the delivery package title, "DanNiPI "
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Nile solution is defined to be family 0x10 in the ASB2 socket.
-#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
-#define INSTALL_FAMILY_10_SUPPORT        TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/Include/OptionC6Install.h
deleted file mode 100644
index a7cc69f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionC6Install.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: C6 C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37456 $   @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_C6_STATE_INSTALL_H_
-#define _OPTION_C6_STATE_INSTALL_H_
-
-#include "cpuC6State.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_C6_STATE_FEAT
-#define F12_C6_STATE_SUPPORT
-#define F14_C6_STATE_SUPPORT
-#define F15_C6_STATE_SUPPORT
-
-#if OPTION_C6_STATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    #ifdef OPTION_FAMILY12H
-      #if OPTION_FAMILY12H == TRUE
-        #if OPTION_FAMILY12H_LN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
-          #undef F12_C6_STATE_SUPPORT
-          #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
-
-          #if OPTION_EARLY_SAMPLES == TRUE
-            extern F_F12_ES_C6_INIT F12C6A0Workaround;
-
-            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
-            {
-              F12C6A0Workaround
-            };
-          #else
-            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
-            {
-              (PF_F12_ES_C6_INIT) CommonVoid
-            };
-          #endif
-
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        #if OPTION_FAMILY14H_ON == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F14C6Support;
-          #undef F14_C6_STATE_SUPPORT
-          #define F14_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14C6Support},
-
-          #if OPTION_EARLY_SAMPLES == TRUE
-            extern F_F14_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
-            extern F_F14_ES_C6_INIT F14C6A0Workaround;
-
-            CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
-            {
-              F14IsC6DisabledEarlySample,
-              F14C6A0Workaround
-            };
-          #else
-            CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
-            {
-              (PF_F14_ES_IS_C6_SUPPORTED) CommonVoid,
-              (PF_F14_ES_C6_INIT) CommonVoid
-            };
-          #endif
-
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_OR == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F15C6Support;
-          #undef F15_C6_STATE_SUPPORT
-          #define F15_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15C6Support},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
-{
-  F12_C6_STATE_SUPPORT
-  F14_C6_STATE_SUPPORT
-  F15_C6_STATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
-{
-  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &C6FamilyServiceArray[0]
-};
-
-#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h
deleted file mode 100644
index 45f8498..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Core Performance Boost
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPB_INSTALL_H_
-#define _OPTION_CPB_INSTALL_H_
-
-#include "cpuCpb.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPB_FEAT
-#define F10_CPB_SUPPORT
-#define F12_CPB_SUPPORT
-#define F15_CPB_SUPPORT
-
-#if OPTION_CPB == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    // Family 10h
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_PH == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
-          #undef F10_CPB_SUPPORT
-          #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
-        #endif
-      #endif
-    #endif
-
-    // Family 12h
-    #ifdef OPTION_FAMILY12H
-      #if OPTION_FAMILY12H == TRUE
-        #if OPTION_FAMILY12H_LN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
-          #undef F12_CPB_SUPPORT
-          #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
-        #endif
-      #endif
-    #endif
-
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_OR == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F15CpbSupport;
-          #undef F15_CPB_SUPPORT
-          #define F15_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15CpbSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
-{
-  F10_CPB_SUPPORT
-  F12_CPB_SUPPORT
-  F15_CPB_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
-{
-  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpbFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h
deleted file mode 100644
index 87aea08..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Cache Flush On Halt
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-
-#include "cpuPostInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-#define F10_BL_CPU_CFOH_SUPPORT
-#define F10_DA_CPU_CFOH_SUPPORT
-#define F10_CPU_CFOH_SUPPORT
-#define F15_OR_CPU_CFOH_SUPPORT
-
-#if OPTION_CPU_CFOH == TRUE
-  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
-        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
-        #if OPTION_FAMILY10H_BL == TRUE
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
-          #undef F10_BL_CPU_CFOH_SUPPORT
-          #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
-        #endif
-
-        #if OPTION_FAMILY10H_DA == TRUE
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
-          #undef F10_DA_CPU_CFOH_SUPPORT
-          #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
-        #endif
-
-        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
-          #undef F10_CPU_CFOH_SUPPORT
-          #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
-        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
-        #if OPTION_FAMILY15H_OR == TRUE
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15CacheFlushOnHalt;
-          #undef F15_OR_CPU_CFOH_SUPPORT
-          #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15CacheFlushOnHalt},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
-{
-  F10_BL_CPU_CFOH_SUPPORT
-  F10_DA_CPU_CFOH_SUPPORT
-  F10_CPU_CFOH_SUPPORT
-  F15_OR_CPU_CFOH_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
-{
-  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CacheFlushOnHaltFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h
deleted file mode 100644
index b49bef1..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Core Leveling
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
-#define _OPTION_CPU_CORELEVELING_INSTALL_H_
-
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CORE_LEVELING_FEAT
-#define F10_REVE_CPU_CORELEVELING_SUPPORT
-#define F10_REVD_CPU_CORELEVELING_SUPPORT
-#define F10_REVC_CPU_CORELEVELING_SUPPORT
-#define F15_CPU_CORELEVELING_SUPPORT
-
-#if OPTION_CPU_CORELEVLING == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
-    // Family 10h
-    #if OPTION_FAMILY10H == TRUE
-      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
-      #undef OPTION_CPU_CORE_LEVELING_FEAT
-      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_HY == TRUE
-          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
-          #undef F10_REVD_CPU_CORELEVELING_SUPPORT
-          #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
-        #endif
-
-        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
-          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
-          #undef F10_REVC_CPU_CORELEVELING_SUPPORT
-          #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
-        #endif
-
-        #if (OPTION_FAMILY10H_PH == TRUE)
-          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
-          #undef F10_REVE_CPU_CORELEVELING_SUPPORT
-          #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
-        #endif
-      #endif
-    #endif
-    // Family 15h
-    #if OPTION_FAMILY15H == TRUE
-      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
-      #undef OPTION_CPU_CORE_LEVELING_FEAT
-      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-
-      extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15CoreLeveling;
-      #undef F15_CPU_CORELEVELING_SUPPORT
-      #define F15_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15, &F15CoreLeveling},
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
-{
-  F10_REVE_CPU_CORELEVELING_SUPPORT
-  F10_REVD_CPU_CORELEVELING_SUPPORT
-  F10_REVC_CPU_CORELEVELING_SUPPORT
-  F15_CPU_CORELEVELING_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
-{
-  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CoreLevelingFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h
deleted file mode 100644
index 44c1796..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of all appropriate CPU family specific support.
- *
- * This file generates the defaults tables for all family specific
- * combinations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37640 $   @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-/*  Default all CPU Specific Service members to off.  They
-    will be enabled as needed by cross referencing families
-    with entry points in the family / model install files.  */
-#define GET_PSTATE_POWER            FALSE
-#define GET_PSTATE_FREQ             FALSE
-#define DISABLE_PSTATE              FALSE
-#define TRANSITION_PSTATE           FALSE
-#define PROC_IDD_MAX                FALSE
-#define GET_TSC_RATE                FALSE
-#define PSTATE_TRANSITION_LATENCY   FALSE
-#define GET_PSTATE_REGISTER_INFO    FALSE
-#define GET_PSTATE_MAX_STATE        FALSE
-#define SET_PSTATE_LEVELING_REG     FALSE
-#define GET_NB_FREQ                 FALSE
-#define IS_NBCOF_INIT_NEEDED        FALSE
-#define AP_INITIAL_LAUNCH           FALSE
-#define GET_AP_MAILBOX_FROM_HW      FALSE
-#define SET_AP_CORE_NUMBER          FALSE
-#define GET_AP_CORE_NUMBER          FALSE
-#define TRANSFER_AP_CORE_NUMBER     FALSE
-#define ID_POSITION_INITIAL_APICID  FALSE
-#define SAVE_FEATURES               FALSE
-#define WRITE_FEATURES              FALSE
-#define SET_DOWN_CORE_REG           FALSE
-#define SET_WARM_RESET_FLAG         FALSE
-#define GET_WARM_RESET_FLAG         FALSE
-#define USES_REGISTER_TABLES        FALSE
-#define BASE_FAMILY_PCI             FALSE
-#define MODEL_SPECIFIC_PCI          FALSE
-#define BASE_FAMILY_MSR             FALSE
-#define MODEL_SPECIFIC_MSR          FALSE
-#define BRAND_STRING1               FALSE
-#define BRAND_STRING2               FALSE
-#define BASE_FAMILY_HT_PCI          FALSE
-#define MODEL_SPECIFIC_HT_PCI       FALSE
-#define BASE_FAMILY_WORKAROUNDS     FALSE
-#define GET_PATCHES                 FALSE
-#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
-#define GET_CACHE_INFO              FALSE
-#define GET_SYSTEM_PM_TABLE         FALSE
-#define GET_WHEA_INIT               FALSE
-#define GET_CFOH_REG                FALSE
-#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
-#define IS_NB_PSTATE_ENABLED        FALSE
-
-/*
- * Pull in family specific services based on entry point
- */
-#if AGESA_ENTRY_INIT_RESET == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef GET_AP_MAILBOX_FROM_HW
-  #define GET_AP_MAILBOX_FROM_HW      TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef TRANSFER_AP_CORE_NUMBER
-  #define TRANSFER_AP_CORE_NUMBER     TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RECOVERY == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-  #undef GET_PATCHES
-  #define GET_PATCHES                 TRUE
-  #undef GET_PATCHES_EQUIVALENCE_TABLE
-  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef DISABLE_PSTATE
-  #define DISABLE_PSTATE              TRUE
-  #undef PROC_IDD_MAX
-  #define PROC_IDD_MAX                TRUE
-  #undef GET_TSC_RATE
-  #define GET_TSC_RATE                TRUE
-  #undef GET_NB_FREQ
-  #define GET_NB_FREQ                 TRUE
-  #undef IS_NBCOF_INIT_NEEDED
-  #define IS_NBCOF_INIT_NEEDED        TRUE
-  #undef AP_INITIAL_LAUNCH
-  #define AP_INITIAL_LAUNCH           TRUE
-  #undef GET_AP_MAILBOX_FROM_HW
-  #define GET_AP_MAILBOX_FROM_HW      TRUE
-  #undef SET_AP_CORE_NUMBER
-  #define SET_AP_CORE_NUMBER          TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef TRANSFER_AP_CORE_NUMBER
-  #define TRANSFER_AP_CORE_NUMBER     TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef SET_DOWN_CORE_REG
-  #define SET_DOWN_CORE_REG           TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-  #undef BRAND_STRING1
-  #define BRAND_STRING1               TRUE
-  #undef BRAND_STRING2
-  #define BRAND_STRING2               TRUE
-  #undef BASE_FAMILY_HT_PCI
-  #define BASE_FAMILY_HT_PCI          TRUE
-  #undef MODEL_SPECIFIC_HT_PCI
-  #define MODEL_SPECIFIC_HT_PCI       TRUE
-  #undef BASE_FAMILY_WORKAROUNDS
-  #define BASE_FAMILY_WORKAROUNDS     TRUE
-  #undef GET_PATCHES
-  #define GET_PATCHES                 TRUE
-  #undef GET_PATCHES_EQUIVALENCE_TABLE
-  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
-  #undef GET_SYSTEM_PM_TABLE
-  #define GET_SYSTEM_PM_TABLE         TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_POST == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef GET_PSTATE_POWER
-  #define GET_PSTATE_POWER            TRUE
-  #undef GET_PSTATE_FREQ
-  #define GET_PSTATE_FREQ             TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef PROC_IDD_MAX
-  #define PROC_IDD_MAX                TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef GET_PSTATE_REGISTER_INFO
-  #define GET_PSTATE_REGISTER_INFO    TRUE
-  #undef GET_PSTATE_MAX_STATE
-  #define GET_PSTATE_MAX_STATE        TRUE
-  #undef SET_PSTATE_LEVELING_REG
-  #define SET_PSTATE_LEVELING_REG     TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef SAVE_FEATURES
-  #define SAVE_FEATURES               TRUE
-  #undef WRITE_FEATURES
-  #define WRITE_FEATURES              TRUE
-  #undef GET_CFOH_REG
-  #define GET_CFOH_REG                TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_ENV == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_MID == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef GET_PSTATE_FREQ
-  #define GET_PSTATE_FREQ             TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef PSTATE_TRANSITION_LATENCY
-  #define PSTATE_TRANSITION_LATENCY   TRUE
-  #undef GET_WHEA_INIT
-  #define GET_WHEA_INIT               TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef GET_TSC_RATE
-  #define GET_TSC_RATE                TRUE
-  #undef BRAND_STRING1
-  #define BRAND_STRING1               TRUE
-  #undef BRAND_STRING2
-  #define BRAND_STRING2               TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_S3SAVE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RESUME == TRUE
-  #undef GET_CFOH_REG
-  #define GET_CFOH_REG                TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-#endif
-
-/*
- * Initialize PCI MMIO mask to 0
- */
-#define FAMILY_MMIO_BASE_MASK (0ull)
-
-
-/*
- * Initialize all families to disabled
- */
-#define OPT_F10_TABLE
-#define OPT_F12_TABLE
-#define OPT_F14_TABLE
-#define OPT_F15_TABLE
-
-#define OPT_F10_ID_TABLE
-#define OPT_F12_ID_TABLE
-#define OPT_F14_ID_TABLE
-#define OPT_F15_ID_TABLE
-
-
-/*
- * Install family specific support
- */
-#if (OPTION_FAMILY10H == TRUE)
-  #include  "OptionFamily10hInstall.h"
-#endif
-
-#if (OPTION_FAMILY12H == TRUE)
-  #include  "OptionFamily12hInstall.h"
-#endif
-
-#if (OPTION_FAMILY14H == TRUE)
-  #include  "OptionFamily14hInstall.h"
-#endif
-
-#if (OPTION_FAMILY15H == TRUE)
-  #include  "OptionFamily15hInstall.h"
-#endif
-
-
-/*
- * Process PCI MMIO mask
- */
-
-// If size is 0, but base is not, break the build.
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
-  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-#endif
-
-// If base is 0, but size is not, break the build.
-#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
-  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-#endif
-
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
-  // Both are non-zero, begin further processing.
-
-  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
-  #if (CFG_PCI_MMIO_BASE < 0x800000)
-    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-  #endif
-
-  // Break the build if the address is too high for the enabled families.
-  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
-    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
-  #endif
-
-  // If the size parameter is not valid, break the build.
-  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
-    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
-      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-    #endif
-  #endif
-
-  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
-  // If the base is not aligned according to size, break the build.
-  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
-    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
-  #endif
-  #undef PCI_MMIO_ALIGNMENT
-#endif
-
-/*
- * Process sockets / modules
- */
-#ifndef ADVCFG_PLATFORM_SOCKETS
-  #error BLDOPT Set Family supported sockets.
-#endif
-#ifndef ADVCFG_PLATFORM_MODULES
-  #error BLDOPT Set Family supported modules.
-#endif
-
-CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
-{
-  ADVCFG_PLATFORM_SOCKETS,
-  ADVCFG_PLATFORM_MODULES
-};
-
-/*
- * Instantiate global data needed for processor identification
- */
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
-{
-  OPT_F10_TABLE
-  OPT_F12_TABLE
-  OPT_F14_TABLE
-  OPT_F15_TABLE
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
-{
-  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpuSupportedFamiliesArray[0]
-};
-
-
-CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
-{
-  OPT_F10_ID_TABLE
-  OPT_F12_ID_TABLE
-  OPT_F14_ID_TABLE
-  OPT_F15_ID_TABLE
-};
-
-CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
-{
-  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
-  CpuSupportedFamilyIdArray
-};
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h
deleted file mode 100644
index 63cd55e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of multiple CPU features.
- *
- * Aggregates enabled CPU features into a list for the dispatcher to process.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37157 $   @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
-#define _OPTION_CPU_FEATURES_INSTALL_H_
-
-#include "OptionHwC1eInstall.h"
-#include "OptionMsgBasedC1eInstall.h"
-#include "OptionSwC1eInstall.h"
-#include "OptionHtAssistInstall.h"
-#include "OptionCpuCoreLevelingInstall.h"
-#include "OptionIoCstateInstall.h"
-#include "OptionC6Install.h"
-#include "OptionCpbInstall.h"
-#include "OptionCpuCacheFlushOnHaltInstall.h"
-#include "OptionLowPwrPstateInstall.h"
-#include "OptionPreserveMailboxInstall.h"
-
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
-{
-  OPTION_HW_C1E_FEAT
-  OPTION_MSG_BASED_C1E_FEAT
-  OPTION_SW_C1E_FEAT
-  OPTION_HT_ASSIST_FEAT
-  OPTION_CPU_CORE_LEVELING_FEAT
-  OPTION_IO_CSTATE_FEAT
-  OPTION_C6_STATE_FEAT
-  OPTION_CPB_FEAT
-  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
-  OPTION_PRESERVE_MAILBOX_FEAT
-  NULL
-};
-
-
-#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionDmi.h b/src/vendorcode/amd/agesa/Include/OptionDmi.h
deleted file mode 100644
index 216e871..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionDmi.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD DMI option API.
- *
- * Contains structures and values used to control the DMI option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_DMI_H_
-#define _OPTION_DMI_H_
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_DMI_FEATURE (
-  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
-  IN OUT   DMI_INFO             **DmiPtr
-  );
-
-typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
-  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
-  );
-
-#define DMI_STRUCT_VERSION  0x01
-
-/// DMI option configuration. Determine the item of structure when compiling.
-typedef struct  {
-  UINT16              OptDmiVersion;      ///< Dmi version.
-  OPTION_DMI_FEATURE  *DmiFeature;        ///< Feature main routine, otherwise dummy.
-  OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
-  UINT16              NumEntries;         ///< Number of entry.
-  VOID                *((*FamilyList)[]); ///< Family service.
-} OPTION_DMI_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif  // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h
deleted file mode 100644
index 87f27e7..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: DMI
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_DMI_INSTALL_H_
-#define _OPTION_DMI_INSTALL_H_
-
-#include "cpuLateInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_DMI
-    #error  BLDOPT: Option not defined: "OPTION_DMI"
-  #endif
-  #if OPTION_DMI == TRUE
-    OPTION_DMI_FEATURE          GetDmiInfoMain;
-    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
-    #define USER_DMI_OPTION     &GetDmiInfoMain
-    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
-
-    // This additional check keeps AP launch routines from being unnecessarily included
-    // in single socket systems.
-    #if OPTION_MULTISOCKET == TRUE
-      #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-      #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
-      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
-    #else
-      #define CPU_DMI_AP_GET_TYPE4_TYPE7
-    #endif
-
-    // Family 10
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
-        #define FAM10_DMI_SUPPORT FAM10_ENABLED,
-        #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
-      #else
-        #define FAM10_DMI_SUPPORT
-        #define FAM10_DMI_TABLE
-      #endif
-    #else
-      #define FAM10_DMI_SUPPORT
-      #define FAM10_DMI_TABLE
-    #endif
-
-    // Family 12
-    #ifdef OPTION_FAMILY12H
-      #if OPTION_FAMILY12H == TRUE
-        extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
-        #define FAM12_DMI_SUPPORT FAM12_ENABLED,
-        #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
-      #else
-        #define FAM12_DMI_SUPPORT
-        #define FAM12_DMI_TABLE
-      #endif
-    #else
-      #define FAM12_DMI_SUPPORT
-      #define FAM12_DMI_TABLE
-    #endif
-
-    // Family 14
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
-        #define FAM14_DMI_SUPPORT FAM14_ENABLED,
-        #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
-      #else
-        #define FAM14_DMI_SUPPORT
-        #define FAM14_DMI_TABLE
-      #endif
-    #else
-      #define FAM14_DMI_SUPPORT
-      #define FAM14_DMI_TABLE
-    #endif
-
-    // Family 15
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern PROC_FAMILY_TABLE ProcFamily15DmiTable;
-        #define FAM15_DMI_SUPPORT FAM15_ENABLED,
-        #define FAM15_DMI_TABLE &ProcFamily15DmiTable,
-      #else
-        #define FAM15_DMI_SUPPORT
-        #define FAM15_DMI_TABLE
-      #endif
-    #else
-      #define FAM15_DMI_SUPPORT
-      #define FAM15_DMI_TABLE
-    #endif
-
-  #else
-    OPTION_DMI_FEATURE          GetDmiInfoStub;
-    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
-    #define USER_DMI_OPTION     GetDmiInfoStub
-    #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
-    #define FAM10_DMI_SUPPORT
-    #define FAM10_DMI_TABLE
-    #define FAM12_DMI_SUPPORT
-    #define FAM12_DMI_TABLE
-    #define FAM14_DMI_SUPPORT
-    #define FAM14_DMI_TABLE
-    #define FAM15_DMI_SUPPORT
-    #define FAM15_DMI_TABLE
-    #define CPU_DMI_AP_GET_TYPE4_TYPE7
-  #endif
-#else
-  OPTION_DMI_FEATURE          GetDmiInfoStub;
-  OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
-  #define USER_DMI_OPTION     GetDmiInfoStub
-  #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
-  #define FAM10_DMI_SUPPORT
-  #define FAM10_DMI_TABLE
-  #define FAM12_DMI_SUPPORT
-  #define FAM12_DMI_TABLE
-  #define FAM14_DMI_SUPPORT
-  #define FAM14_DMI_TABLE
-  #define FAM15_DMI_SUPPORT
-  #define FAM15_DMI_TABLE
-  #define CPU_DMI_AP_GET_TYPE4_TYPE7
-#endif
-
-/// DMI supported families enum
-typedef enum {
-  FAM10_DMI_SUPPORT                   ///< Conditionally define F10 support
-  FAM12_DMI_SUPPORT                   ///< Conditionally define F12 support
-  FAM14_DMI_SUPPORT                   ///< Conditionally define F14 support
-  FAM15_DMI_SUPPORT                   ///< Conditionally define F15 support
-  NUM_DMI_FAMILIES                    ///< Number of installed families
-} AGESA_DMI_SUPPORTED_FAM;
-
-/*  Declare the Family List. An array of pointers to tables that each describe a family  */
-CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
-  FAM10_DMI_TABLE
-  FAM12_DMI_TABLE
-  FAM14_DMI_TABLE
-  FAM15_DMI_TABLE
-  NULL
-};
-
-/*  Declare the instance of the DMI option configuration structure  */
-CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
-  DMI_STRUCT_VERSION,
-  USER_DMI_OPTION,
-  USER_DMI_RELEASE_BUFFER,
-  NUM_DMI_FAMILIES,
-  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
-};
-
-#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h
deleted file mode 100644
index 4b4347f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h
+++ /dev/null
@@ -1,1996 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 10h support
- *
- * This file generates the defaults tables for family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37150 $   @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_10H_INSTALL_H_
-#define _OPTION_FAMILY_10H_INSTALL_H_
-
-/*
- * Common Family 10h routines
- */
-extern F_CPU_DISABLE_PSTATE F10DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
-extern F_CPU_GET_TSC_RATE F10GetTscRate;
-extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
-extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
-extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
-extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
-extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SAVE_FEATURES F10SaveFeatures;
-extern F_CPU_WRITE_FEATURES F10WriteFeatures;
-extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
-extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
-extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
-extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
-extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
-extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
-extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
-
-
-/*
- * Install family 10h model 5 support
- */
-#ifdef OPTION_FAMILY10H_BL
-  #if OPTION_FAMILY10H_BL == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
-    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
-    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F10PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10SingleLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10RevCPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10BlPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F10MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10RevCMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10BlMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10RevCHtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10BlHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F10WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F10DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F10TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F10CommonRevCGetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F10GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10CommonRevCGetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F10CommonRevCGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F10LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F10CommonRevCGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F10GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F10SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F10GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F10TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F10CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        F10SaveFeatures,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        F10WriteFeatures,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F10SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F10GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF10BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF10BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF10BlMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF10BlMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF10CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF10SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF10WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F10GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F10CommonRevCIsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F10GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F10BlRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      NULL,
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF10EarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define BL_SOCKETS 1
-    #define BL_MODULES 1
-    #define BL_RECOVERY_SOCKETS 1
-    #define BL_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
-    #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES BL_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < BL_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES BL_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F10_BL_UCODE_C6
-      #define F10_BL_UCODE_C8
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
-          #undef F10_BL_UCODE_C6
-          #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
-        #endif
-        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
-          #undef F10_BL_UCODE_C8
-          #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
-      {
-        F10_BL_UCODE_C6
-        F10_BL_UCODE_C8
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
-  #else
-    #define OPT_F10_BL_CPU
-    #define OPT_F10_BL_ID
-  #endif
-#else
-  #define OPT_F10_BL_CPU
-  #define OPT_F10_BL_ID
-#endif
-
-/*
- * Install family 10h model 6 support
- */
-#ifdef OPTION_FAMILY10H_DA
-  #if OPTION_FAMILY10H_DA == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
-    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
-    extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
-    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F10PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10SingleLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10RevCPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10DaPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F10MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10RevCMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10DaMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10RevCHtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10DaHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F10WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F10DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F10TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F10CommonRevCGetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F10GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10CommonRevCGetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F10CommonRevCGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F10LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F10CommonRevCGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F10GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F10SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F10GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F10TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F10CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        F10SaveFeatures,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        F10WriteFeatures,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F10SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F10GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF10BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF10BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF10DaMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF10DaMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF10CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF10SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF10WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F10GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F10CommonRevCIsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F10GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F10DaRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      NULL,
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF10EarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define DA_SOCKETS 1
-    #define DA_MODULES 1
-    #define DA_RECOVERY_SOCKETS 1
-    #define DA_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
-    #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES DA_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < DA_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES DA_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F10_DA_UCODE_C7
-      #define F10_DA_UCODE_C8
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
-          #undef F10_DA_UCODE_C7
-          #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
-        #endif
-        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
-          #undef F10_DA_UCODE_C8
-          #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
-      {
-        F10_DA_UCODE_C7
-        F10_DA_UCODE_C8
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
-  #else
-    #define OPT_F10_DA_CPU
-    #define OPT_F10_DA_ID
-  #endif
-#else
-  #define OPT_F10_DA_CPU
-  #define OPT_F10_DA_ID
-#endif
-
-/*
- * Install family 10h models 8 & 9 support
- */
-#ifdef OPTION_FAMILY10H_HY
-  #if OPTION_FAMILY10H_HY == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
-    extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
-    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevDGetNumberOfCoresForBrandstring;
-    extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F10PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10MultiLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10HyPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F10MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10HyMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HyHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F10WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {TokenPciRegister, SetRegisterForTokenPciEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F10DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F10TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F10CommonRevDGetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F10GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10CommonRevDGetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F10CommonRevDGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F10LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F10CommonRevDGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F10GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F10SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F10GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F10TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F10CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        F10SaveFeatures,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        F10WriteFeatures,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F10SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F10GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF10BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF10BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF10HyMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF10HyMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF10CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF10SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF10WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F10GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F10GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F10HyRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      #if MODEL_SPECIFIC_HT_PCI == TRUE
-        (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
-      #else
-        NULL,
-      #endif
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_C32_SOCKET_SUPPORT == TRUE
-          GetF10HyEarlyInitOnCoreTable
-        #else
-          GetF10EarlyInitOnCoreTable
-        #endif
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define HY_SOCKETS 8
-    #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
-      #define HY_MODULES 2
-    #else
-      #define HY_MODULES 1
-    #endif
-    #define HY_RECOVERY_SOCKETS 1
-    #define HY_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
-    #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES HY_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < HY_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES HY_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F10_HY_UCODE_C4
-      #define F10_HY_UCODE_C5
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_C32_SOCKET_SUPPORT == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
-          #undef F10_HY_UCODE_C5
-          #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
-        #endif
-        #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
-          #undef F10_HY_UCODE_C4
-          #define F10_HY_UCODE_C4 &CpuF10MicrocodePatch010000c4,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
-      {
-        F10_HY_UCODE_C4
-        F10_HY_UCODE_C5
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
-  #else
-    #define OPT_F10_HY_CPU
-    #define OPT_F10_HY_ID
-  #endif
-#else
-  #define OPT_F10_HY_CPU
-  #define OPT_F10_HY_ID
-#endif
-
-/*
- * Install family 10h model 10 support
- */
-#ifdef OPTION_FAMILY10H_PH
-  #if OPTION_FAMILY10H_PH == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
-    extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevEGetNumberOfCoresForBrandstring;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F10PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10SingleLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10RevEPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F10MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10RevEMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10RevEHtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10PhHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F10WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F10DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F10TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F10CommonRevEGetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F10GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10CommonRevEGetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F10CommonRevEGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F10LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F10CommonRevEGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F10GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F10SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F10GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F10TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F10CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        F10SaveFeatures,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        F10WriteFeatures,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F10SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F10GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF10BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF10BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF10PhMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF10PhMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF10CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF10SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF10WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F10GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F10GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F10PhRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      NULL,
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF10EarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define PH_SOCKETS 1
-    #define PH_MODULES 1
-    #define PH_RECOVERY_SOCKETS 1
-    #define PH_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
-    #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES PH_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < PH_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES PH_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F10_PH_UCODE_BF
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
-          #undef F10_PH_UCODE_BF
-          #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
-      {
-        F10_PH_UCODE_BF
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
-  #else
-    #define OPT_F10_PH_CPU
-    #define OPT_F10_PH_ID
-  #endif
-#else
-  #define OPT_F10_PH_CPU
-  #define OPT_F10_PH_ID
-#endif
-
-
-/*
- * Install family 10h model 4 support
- */
-#ifdef OPTION_FAMILY10H_RB
-  #if OPTION_FAMILY10H_RB == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
-    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
-    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F10PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10MultiLinkPciRegisterTable,
-          &F10SingleLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10RevCPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F10RbPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F10MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10RevCMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F10RbMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10RevCHtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F10RbHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F10WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {TokenPciRegister, SetRegisterForTokenPciEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F10DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F10TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F10CommonRevCGetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F10GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F10CommonRevCGetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F10CommonRevCGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F10LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F10CommonRevCGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F10GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F10SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F10GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F10TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F10CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        F10SaveFeatures,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        F10WriteFeatures,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F10SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F10GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF10BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF10BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF10RbMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF10RbMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF10CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF10SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF10WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F10GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F10CommonRevCIsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F10SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F10GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F10RbRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      NULL,
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF10EarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define RB_SOCKETS 8
-    #define RB_MODULES 1
-    #define RB_RECOVERY_SOCKETS 1
-    #define RB_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
-    #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES RB_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < RB_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES RB_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F10_RB_UCODE_85
-      #define F10_RB_UCODE_C6
-      #define F10_RB_UCODE_C8
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
-          #undef F10_RB_UCODE_85
-          #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
-          #undef F10_RB_UCODE_C6
-          #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
-          #undef F10_RB_UCODE_C8
-          #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
-      {
-        F10_RB_UCODE_85
-        F10_RB_UCODE_C6
-        F10_RB_UCODE_C8
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
-  #else
-    #define OPT_F10_RB_CPU
-    #define OPT_F10_RB_ID
-  #endif
-#else
-  #define OPT_F10_RB_CPU
-  #define OPT_F10_RB_ID
-#endif
-
-
-/*
- * Install unknown family 10h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
-  {
-    #if BASE_FAMILY_PCI == TRUE
-      &F10PciRegisterTable,
-    #endif
-    #if BASE_FAMILY_MSR == TRUE
-      &F10MsrRegisterTable,
-    #endif
-    #if BASE_FAMILY_HT_PCI == TRUE
-      &F10HtPhyRegisterTable,
-    #endif
-    #if OPTION_MULTISOCKET == TRUE
-      #if MODEL_SPECIFIC_PCI == TRUE
-        &F10MultiLinkPciRegisterTable,
-      #endif
-    #endif
-    #if OPTION_MULTISOCKET == FALSE
-      #if MODEL_SPECIFIC_PCI == TRUE
-        &F10SingleLinkPciRegisterTable,
-      #endif
-    #endif
-    #if BASE_FAMILY_WORKAROUNDS == TRUE
-      &F10WorkaroundsTable,
-    #endif
-    // the end.
-    NULL
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-    {HtPhyRegister, SetRegisterForHtPhyEntry},
-    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-    {HtHostPciRegister, SetRegisterForHtHostEntry},
-    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
-    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
-{
-  0,
-  #if DISABLE_PSTATE == TRUE
-    F10DisablePstate,
-  #else
-    (PF_CPU_DISABLE_PSTATE) CommonAssert,
-  #endif
-  #if TRANSITION_PSTATE == TRUE
-    F10TransitionPstate,
-  #else
-    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-  #endif
-  #if PROC_IDD_MAX == TRUE
-    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
-  #else
-    (PF_CPU_GET_IDD_MAX) CommonAssert,
-  #endif
-  #if GET_TSC_RATE == TRUE
-    F10GetTscRate,
-  #else
-    (PF_CPU_GET_TSC_RATE) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F10GetCurrentNbFrequency,
-  #else
-    (PF_CPU_GET_NB_FREQ) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
-  #else
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-  #endif
-  #if IS_NBCOF_INIT_NEEDED == TRUE
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
-  #else
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-  #endif
-  #if AP_INITIAL_LAUNCH == TRUE
-    F10LaunchApCore,
-  #else
-    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-  #endif
-  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
-  #else
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-  #endif
-  #if GET_AP_MAILBOX_FROM_HW == TRUE
-    F10GetApMailboxFromHardware,
-  #else
-    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-  #endif
-  #if SET_AP_CORE_NUMBER == TRUE
-    F10SetApCoreNumber,
-  #else
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if GET_AP_CORE_NUMBER == TRUE
-    F10GetApCoreNumber,
-  #else
-    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if TRANSFER_AP_CORE_NUMBER == TRUE
-    F10TransferApCoreNumber,
-  #else
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if ID_POSITION_INITIAL_APICID == TRUE
-    F10CpuAmdCoreIdPositionInInitialApicId,
-  #else
-    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-  #endif
-  #if SAVE_FEATURES == TRUE
-    F10SaveFeatures,
-  #else
-    (PF_CPU_SAVE_FEATURES) CommonAssert,
-  #endif
-  #if WRITE_FEATURES == TRUE
-    F10WriteFeatures,
-  #else
-    (PF_CPU_WRITE_FEATURES) CommonAssert,
-  #endif
-  #if SET_WARM_RESET_FLAG == TRUE
-    F10SetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if GET_WARM_RESET_FLAG == TRUE
-    F10GetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if BRAND_STRING1 == TRUE
-    GetF10BrandIdString1,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if BRAND_STRING2 == TRUE
-    GetF10BrandIdString2,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_CACHE_INFO == TRUE
-    GetF10CacheInfo,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_SYSTEM_PM_TABLE == TRUE
-    GetF10SysPmTable,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_WHEA_INIT == TRUE
-    GetF10WheaInitData,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-    F10GetPlatformTypeSpecificInfo,
-  #else
-    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-  #endif
-  #if IS_NB_PSTATE_ENABLED == TRUE
-    (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
-  #else
-    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    F10NextLinkHasHtPhyFeats,
-  #else
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    F10SetHtPhyRegister,
-  #else
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #endif
-  #if BASE_FAMILY_PCI == TRUE
-    F10GetNextHtLinkFeatures,
-  #else
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (REGISTER_TABLE **) F10UnknownRegisterTables,
-  #else
-    NULL,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
-  #else
-    NULL,
-  #endif
-  NULL,
-  NULL,
-  InitCacheDisabled,
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-    GetF10EarlyInitOnCoreTable
-  #else
-    (PF_GET_EARLY_INIT_TABLE) CommonVoid
-  #endif
-};
-
-// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
-  #undef  FAMILY_MMIO_BASE_MASK
-  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
-#endif
-
-#undef OPT_F10_ID_TABLE
-#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
-#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
-
-#undef OPT_F10_TABLE
-#define OPT_F10_TABLE   OPT_F10_BL_CPU  OPT_F10_DA_CPU  OPT_F10_HY_CPU  OPT_F10_PH_CPU  OPT_F10_RB_CPU  OPT_F10_UNKNOWN_CPU
-
-#if OPTION_G34_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
-  #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
-  #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
-#else
-  #define F10_G34_BRANDSTRING1
-  #define F10_G34_BRANDSTRING2
-#endif
-#if OPTION_C32_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
-  #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
-  #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
-#else
-  #define F10_C32_BRANDSTRING1
-  #define F10_C32_BRANDSTRING2
-#endif
-#if OPTION_S1G3_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
-  #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
-  #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
-#else
-  #define F10_S1G3_BRANDSTRING1
-  #define F10_S1G3_BRANDSTRING2
-#endif
-#if OPTION_S1G4_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
-  #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
-  #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
-#else
-  #define F10_S1G4_BRANDSTRING1
-  #define F10_S1G4_BRANDSTRING2
-#endif
-#if OPTION_ASB2_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
-  #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
-  #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
-#else
-  #define F10_ASB2_BRANDSTRING1
-  #define F10_ASB2_BRANDSTRING2
-#endif
-#if OPTION_AM3_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
-  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
-  #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
-  #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
-#else
-  #define F10_AM3_BRANDSTRING1
-  #define F10_AM3_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
-  {
-    F10_G34_BRANDSTRING1
-    F10_C32_BRANDSTRING1
-    F10_S1G3_BRANDSTRING1
-    F10_S1G4_BRANDSTRING1
-    F10_ASB2_BRANDSTRING1
-    F10_AM3_BRANDSTRING1
-  };
-
-  CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
-  {
-    F10_G34_BRANDSTRING2
-    F10_C32_BRANDSTRING2
-    F10_S1G3_BRANDSTRING2
-    F10_S1G4_BRANDSTRING2
-    F10_ASB2_BRANDSTRING2
-    F10_AM3_BRANDSTRING2
-  };
-
-  CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
-{
-  OPT_F10_BL_ID
-  OPT_F10_DA_ID
-  OPT_F10_HY_ID
-  OPT_F10_PH_ID
-  OPT_F10_RB_ID
-};
-
-#endif  // _OPTION_FAMILY_10H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h b/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h
deleted file mode 100644
index e475a18..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family 12h 'early sample' support
- *
- * This file defines the required structures for family 12h pre-production processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37456 $   @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
-#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-/**
- *  Return the appropriate values of certain NB P-state related registers.
- *
- *  @param[in,out] FCRxFE00_6000           The value of FCRxFE006000.
- *  @param[in,out] FCRxFE00_6002           The value of FCRxFE006002.
- *  @param[in,out] FCRxFE00_7006           The value of FCRxFE007006.
- *  @param[in,out] FCRxFE00_7009           The value of FCRxFE007009.
- *  @param[in]     MainPll                 The main PLL frequency.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_NB_PSTATE_INIT (
-  IN OUT   VOID *FCRxFE00_6000,
-  IN OUT   VOID *FCRxFE00_6002,
-  IN OUT   VOID *FCRxFE00_7006,
-  IN OUT   VOID *FCRxFE00_7009,
-  IN       UINT32 MainPll,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
-
-/**
- *  Return the appropriate value of a certain NB P-state related register.
- *
- *  @param[in,out] FCRxFE00_6000           The value of FCRxFE006000.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_POWER_PLANE_INIT (
-  IN OUT   VOID *FCRxFE00_6000,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
-
-/**
- *  Implements an early sample workaround required for C6
- *
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_C6_INIT (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
-
-
-/// Hook points in the core functionality necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
-  PF_F12_ES_POWER_PLANE_INIT     F12PowerPlaneInitHook;     ///< Allows for override of a certain processor register value during power plane init
-  PF_F12_ES_NB_PSTATE_INIT       F12NbPstateInitHook;       ///< Allows for override of certain processor register values for proper NB P-state init
-} F12_ES_CORE_SUPPORT;
-
-/// Hook points in the C6 feature necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
-  PF_F12_ES_C6_INIT            F12InitializeC6;        ///< Hook for erratum 453 workaround
-} F12_ES_C6_SUPPORT;
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-
-#endif  // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h
deleted file mode 100644
index 63e8b27..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h
+++ /dev/null
@@ -1,665 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 12h support
- *
- * This file generates the defaults tables for family 12h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37456 $   @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_12H_INSTALL_H_
-#define _OPTION_FAMILY_12H_INSTALL_H_
-
-
-#include "OptionFamily12hEarlySample.h"
-
-/*
- * Common Family 12h routines
- */
-extern F_CPU_DISABLE_PSTATE F12DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F12TransitionPstate;
-extern F_CPU_GET_TSC_RATE F12GetTscRate;
-extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency;
-extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo;
-extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate;
-extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore;
-extern F_CPU_GET_IDD_MAX F12GetProcIddMax;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware;
-extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister;
-extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo;
-extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable;
-extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F12GetNumberOfCoresForBrandstring;
-extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
-#if OPTION_EARLY_SAMPLES == TRUE
-  extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable;
-#endif
-
-/*
- * Install family 12h model 0 support
- */
-
-#ifdef OPTION_FAMILY12H_LN
-  #if OPTION_FAMILY12H_LN == TRUE
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F12PciRegisterTable,
-        #endif
-        #if BASE_FAMILY_PCI == TRUE
-          &F12PerCorePciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F12MsrRegisterTable,
-          #if OPTION_EARLY_SAMPLES == TRUE
-            &F12EarlySampleMsrRegisterTable,
-          #endif
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F12DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F12TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F12GetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F12GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F12GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F12GetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F12GetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F12LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F12GetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F12GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F12GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F12CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        (PF_CPU_SAVE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        (PF_CPU_WRITE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F12SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F12GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF12BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF12BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF12LnMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF12LnMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF12CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF12SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF12WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F12GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F12IsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_SET_HT_PHY_REGISTER) CommonVoid,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F12LnRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      #if MODEL_SPECIFIC_HT_PCI == TRUE
-        NULL,
-      #else
-        NULL,
-      #endif
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetCommonEarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define LN_SOCKETS 1
-    #define LN_MODULES 1
-    #define LN_RECOVERY_SOCKETS 1
-    #define LN_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev;
-    #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES LN_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < LN_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES LN_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F12_LN_UCODE_02
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_EARLY_SAMPLES == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002;
-          #undef F12_LN_UCODE_02
-          #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] =
-      {
-        F12_LN_UCODE_02
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #if OPTION_EARLY_SAMPLES == TRUE
-      extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook;
-      extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook;
-
-      CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          F12PowerPlaneInitEarlySampleHook,
-        #else
-          (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-          F12NbPstateInitEarlySampleHook
-        #else
-          (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #else
-      CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          (PF_F12_ES_POWER_PLANE_INIT) CommonVoid,
-        #else
-          (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-          (PF_F12_ES_NB_PSTATE_INIT) CommonVoid
-        #else
-          (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #endif
-
-    #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices},
-  #else  //  OPTION_FAMILY12H_LN == TRUE
-    #define OPT_F12_LN_CPU
-    #define OPT_F12_LN_ID
-  #endif  //  OPTION_FAMILY12H_LN == TRUE
-#else  //  defined (OPTION_FAMILY12H_LN)
-  #define OPT_F12_LN_CPU
-  #define OPT_F12_LN_ID
-#endif  //  defined (OPTION_FAMILY12H_LN)
-
-
-/*
- * Install unknown family 12h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] =
-  {
-    #if BASE_FAMILY_PCI == TRUE
-      &F12PciRegisterTable,
-    #endif
-    #if BASE_FAMILY_PCI == TRUE
-      &F12PerCorePciRegisterTable,
-    #endif
-    #if BASE_FAMILY_MSR == TRUE
-      &F12MsrRegisterTable,
-    #endif
-    // the end.
-    NULL
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-    {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices =
-{
-  0,
-  #if DISABLE_PSTATE == TRUE
-    F12DisablePstate,
-  #else
-    (PF_CPU_DISABLE_PSTATE) CommonAssert,
-  #endif
-  #if TRANSITION_PSTATE == TRUE
-    F12TransitionPstate,
-  #else
-    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-  #endif
-  #if PROC_IDD_MAX == TRUE
-    F12GetProcIddMax,
-  #else
-    (PF_CPU_GET_IDD_MAX) CommonAssert,
-  #endif
-  #if GET_TSC_RATE == TRUE
-    F12GetTscRate,
-  #else
-    (PF_CPU_GET_TSC_RATE) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F12GetCurrentNbFrequency,
-  #else
-    (PF_CPU_GET_NB_FREQ) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F12GetNbPstateInfo,
-  #else
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-  #endif
-  #if IS_NBCOF_INIT_NEEDED == TRUE
-    F12GetNbCofVidUpdate,
-  #else
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-  #endif
-  #if AP_INITIAL_LAUNCH == TRUE
-    F12LaunchApCore,
-  #else
-    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-  #endif
-  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-    F12GetNumberOfCoresForBrandstring,
-  #else
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-  #endif
-  #if GET_AP_MAILBOX_FROM_HW == TRUE
-    F12GetApMailboxFromHardware,
-  #else
-    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-  #endif
-  #if SET_AP_CORE_NUMBER == TRUE
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if GET_AP_CORE_NUMBER == TRUE
-    F12GetApCoreNumber,
-  #else
-    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if TRANSFER_AP_CORE_NUMBER == TRUE
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if ID_POSITION_INITIAL_APICID == TRUE
-    F12CpuAmdCoreIdPositionInInitialApicId,
-  #else
-    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-  #endif
-  #if SAVE_FEATURES == TRUE
-    (PF_CPU_SAVE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_SAVE_FEATURES) CommonAssert,
-  #endif
-  #if WRITE_FEATURES == TRUE
-    (PF_CPU_WRITE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_WRITE_FEATURES) CommonAssert,
-  #endif
-  #if SET_WARM_RESET_FLAG == TRUE
-    F12SetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if GET_WARM_RESET_FLAG == TRUE
-    F12GetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if BRAND_STRING1 == TRUE
-    GetF12BrandIdString1,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if BRAND_STRING2 == TRUE
-    GetF12BrandIdString2,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_CACHE_INFO == TRUE
-    GetF12CacheInfo,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_SYSTEM_PM_TABLE == TRUE
-    GetF12SysPmTable,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_WHEA_INIT == TRUE
-    GetF12WheaInitData,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-    F12GetPlatformTypeSpecificInfo,
-  #else
-    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-  #endif
-  #if IS_NB_PSTATE_ENABLED == TRUE
-    F12IsNbPstateEnabled,
-  #else
-    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-  #else
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #else
-    (PF_SET_HT_PHY_REGISTER) CommonAssert,
-  #endif
-  #if BASE_FAMILY_PCI == TRUE
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #else
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (REGISTER_TABLE **) F12UnknownRegisterTables,
-  #else
-    NULL,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors,
-  #else
-    NULL,
-  #endif
-  #if MODEL_SPECIFIC_HT_PCI == TRUE
-    NULL,
-  #else
-    NULL,
-  #endif
-  NULL,
-  InitCacheDisabled,
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-    GetCommonEarlyInitOnCoreTable
-  #else
-    (PF_GET_EARLY_INIT_TABLE) CommonVoid
-  #endif
-};
-
- // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
-  #undef  FAMILY_MMIO_BASE_MASK
-  #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-#endif
-
-#undef OPT_F12_ID_TABLE
-#define OPT_F12_ID_TABLE {0x12, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))},
-#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices},
-
-#undef OPT_F12_TABLE
-#define OPT_F12_TABLE   OPT_F12_LN_CPU  OPT_F12_UNKNOWN_CPU
-
-#if OPTION_FS1_SOCKET_SUPPORT == TRUE
-  #define F12_FS1_BRANDSTRING1 NULL,
-  #define F12_FS1_BRANDSTRING2 NULL,
-#else
-  #define F12_FS1_BRANDSTRING1
-  #define F12_FS1_BRANDSTRING2
-#endif
-#if OPTION_FM1_SOCKET_SUPPORT == TRUE
-  #define F12_FM1_BRANDSTRING1 NULL,
-  #define F12_FM1_BRANDSTRING2 NULL,
-#else
-  #define F12_FM1_BRANDSTRING1
-  #define F12_FM1_BRANDSTRING2
-#endif
-#if OPTION_FP1_SOCKET_SUPPORT == TRUE
-  #define F12_FP1_BRANDSTRING1 NULL,
-  #define F12_FP1_BRANDSTRING2 NULL,
-#else
-  #define F12_FP1_BRANDSTRING1
-  #define F12_FP1_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
-  {
-    F12_FS1_BRANDSTRING1
-    F12_FM1_BRANDSTRING1
-    F12_FP1_BRANDSTRING1
-  };
-
-  CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
-  {
-    F12_FS1_BRANDSTRING2
-    F12_FM1_BRANDSTRING2
-    F12_FP1_BRANDSTRING2
-  };
-
-  CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] =
-{
-  OPT_F12_LN_ID
-};
-
-#endif  // _OPTION_FAMILY_12H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h b/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h
deleted file mode 100644
index ef042bd..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family 14h 'early sample' support
- *
- * This file defines the required structures for family 14h pre-production processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37018 $   @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
-#define _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-/**
- *  Return the correct early init table pointer.
- *
- *  @param[in,out] Table                   The early init table pointer.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_GET_EARLY_INIT_TABLE (
-  IN OUT   CONST VOID **Table,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F14_ES_GET_EARLY_INIT_TABLE *PF_F14_ES_GET_EARLY_INIT_TABLE;
-
-/**
- *  Return the appropriate values of certain NB P-state related registers.
- *
- *  @param[in,out] FCRxFE00_6000           The value of FCRxFE006000.
- *  @param[in,out] FCRxFE00_6002           The value of FCRxFE006002.
- *  @param[in,out] FCRxFE00_7006           The value of FCRxFE007006.
- *  @param[in,out] FCRxFE00_7009           The value of FCRxFE007009.
- *  @param[in]     MainPll                 The main PLL frequency.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_NB_PSTATE_INIT (
-  IN OUT   VOID *FCRxFE00_6000,
-  IN OUT   VOID *FCRxFE00_6002,
-  IN OUT   VOID *FCRxFE00_7006,
-  IN OUT   VOID *FCRxFE00_7009,
-  IN       UINT32 MainPll,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F14_ES_NB_PSTATE_INIT *PF_F14_ES_NB_PSTATE_INIT;
-
-/**
- *  Return the appropriate value of a certain NB P-state related register.
- *
- *  @param[in,out] FCRxFE00_6000           The value of FCRxFE006000.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_POWER_PLANE_INIT (
-  IN OUT   VOID *FCRxFE00_6000,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F14_ES_POWER_PLANE_INIT *PF_F14_ES_POWER_PLANE_INIT;
-
-/**
- *  Returns whether or not the processor should enable the C6 feature.
- *
- *  @param[in,out] IsEnabled               Whether or not to enable C6
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_IS_C6_SUPPORTED (
-  IN OUT   BOOLEAN *IsEnabled,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F14_ES_IS_C6_SUPPORTED *PF_F14_ES_IS_C6_SUPPORTED;
-
-/**
- *  Implements an early sample workaround required for C6
- *
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_C6_INIT (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/// Reference to a Method.
-typedef F_F14_ES_C6_INIT *PF_F14_ES_C6_INIT;
-
-
-/// Hook points in the core functionality necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
-  PF_F14_ES_GET_EARLY_INIT_TABLE F14GetEarlyInitTableHook;  ///< Early init table pointer override
-  PF_F14_ES_POWER_PLANE_INIT     F14PowerPlaneInitHook;     ///< Allows for override of a certain processor register value during power plane init
-  PF_F14_ES_NB_PSTATE_INIT       F14NbPstateInitHook;       ///< Allows for override of certain processor register values for proper NB P-state init
-} F14_ES_CORE_SUPPORT;
-
-/// Hook points in the C6 feature necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
-  PF_F14_ES_IS_C6_SUPPORTED    F14IsC6SupportedHook;   ///< C6 enablement override
-  PF_F14_ES_C6_INIT            F14InitializeC6;        ///< Hook for erratum 453 workaround
-} F14_ES_C6_SUPPORT;
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-
-#endif  // _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
deleted file mode 100644
index 38a287d..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
+++ /dev/null
@@ -1,661 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 14h support
- *
- * This file generates the default tables for family 14h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37854 $   @e \$Date: 2010-09-14 06:35:39 +0800 (Tue, 14 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_14H_INSTALL_H_
-#define _OPTION_FAMILY_14H_INSTALL_H_
-
-
-#include "OptionFamily14hEarlySample.h"
-
-/*
- * Common Family 14h routines
- */
-extern F_CPU_DISABLE_PSTATE F14DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
-extern F_CPU_GET_TSC_RATE F14GetTscRate;
-extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
-extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
-extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
-extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
-extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
-extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
-extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
-extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F14GetNumberOfCoresForBrandstring;
-extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
-#if OPTION_EARLY_SAMPLES == TRUE
-  extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
-#endif
-
-
-/*
- * Install family 14h model 0 support
- */
-#ifdef OPTION_FAMILY14H_ON
-  #if OPTION_FAMILY14H_ON == TRUE
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F14PciRegisterTable,
-        #endif
-        #if BASE_FAMILY_PCI == TRUE
-          &F14PerCorePciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F14MsrRegisterTable,
-          #if OPTION_EARLY_SAMPLES == TRUE
-            &F14EarlySampleMsrRegisterTable,
-          #endif
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F14DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F14TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F14GetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F14GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F14GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F14GetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F14GetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F14LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F14GetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F14GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F14GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F14CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        (PF_CPU_SAVE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        (PF_CPU_WRITE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F14SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F14GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF14BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF14BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF14OnMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF14OnMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF14CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF14SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF14WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F14GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F14IsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_SET_HT_PHY_REGISTER) CommonVoid,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F14OnRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      #if MODEL_SPECIFIC_HT_PCI == TRUE
-        NULL,
-      #else
-        NULL,
-      #endif
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF14OnEarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define ON_SOCKETS 1
-    #define ON_MODULES 1
-    #define ON_RECOVERY_SOCKETS 1
-    #define ON_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
-    #define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES ON_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < ON_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES ON_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F14_ON_UCODE_0B
-      #define F14_ON_UCODE_1A
-      #define F14_ON_UCODE_25
-
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_EARLY_SAMPLES == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
-          #undef F14_ON_UCODE_0B
-          #define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
-
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
-          #undef F14_ON_UCODE_1A
-          #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
-        #endif
-        extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
-        #undef F14_ON_UCODE_25
-        #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
-      {
-        F14_ON_UCODE_0B
-        F14_ON_UCODE_1A
-        F14_ON_UCODE_25
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #if OPTION_EARLY_SAMPLES == TRUE
-      extern F_F14_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
-      extern F_F14_ES_NB_PSTATE_INIT F14NbPstateInitEarlySampleHook;
-      extern F_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitEarlySampleHook;
-
-      CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          GetF14OnEarlySampleEarlyInitTable,
-          F14PowerPlaneInitEarlySampleHook,
-        #else
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-          F14NbPstateInitEarlySampleHook
-        #else
-          (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #else
-      CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonVoid,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonVoid,
-        #else
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-          (PF_F14_ES_NB_PSTATE_INIT) CommonVoid
-        #else
-          (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #endif
-
-    #define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
-  #else  //  OPTION_FAMILY14H_ON == TRUE
-    #define OPT_F14_ON_CPU
-    #define OPT_F14_ON_ID
-  #endif  //  OPTION_FAMILY14H_ON == TRUE
-#else  //  defined (OPTION_FAMILY14H_ON)
-  #define OPT_F14_ON_CPU
-  #define OPT_F14_ON_ID
-#endif  //  defined (OPTION_FAMILY14H_ON)
-
-/*
- * Install unknown family 14h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST REGISTER_TABLE ROMDATA *F14UnknownRegisterTables[] =
-  {
-    #if BASE_FAMILY_PCI == TRUE
-      &F14PciRegisterTable,
-    #endif
-    #if BASE_FAMILY_PCI == TRUE
-      &F14PerCorePciRegisterTable,
-    #endif
-    #if BASE_FAMILY_MSR == TRUE
-      &F14MsrRegisterTable,
-    #endif
-    // the end.
-    NULL
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
-{
-  0,
-  #if DISABLE_PSTATE == TRUE
-    F14DisablePstate,
-  #else
-    (PF_CPU_DISABLE_PSTATE) CommonAssert,
-  #endif
-  #if TRANSITION_PSTATE == TRUE
-    F14TransitionPstate,
-  #else
-    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-  #endif
-  #if PROC_IDD_MAX == TRUE
-    (PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
-  #else
-    (PF_CPU_GET_IDD_MAX) CommonAssert,
-  #endif
-  #if GET_TSC_RATE == TRUE
-    F14GetTscRate,
-  #else
-    (PF_CPU_GET_TSC_RATE) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F14GetCurrentNbFrequency,
-  #else
-    (PF_CPU_GET_NB_FREQ) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F14GetNbPstateInfo,
-  #else
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-  #endif
-  #if IS_NBCOF_INIT_NEEDED == TRUE
-    F14GetNbCofVidUpdate,
-  #else
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-  #endif
-  #if AP_INITIAL_LAUNCH == TRUE
-    F14LaunchApCore,
-  #else
-    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-  #endif
-  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-    F14GetNumberOfCoresForBrandstring,
-  #else
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-  #endif
-  #if GET_AP_MAILBOX_FROM_HW == TRUE
-    F14GetApMailboxFromHardware,
-  #else
-    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-  #endif
-  #if SET_AP_CORE_NUMBER == TRUE
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if GET_AP_CORE_NUMBER == TRUE
-    F14GetApCoreNumber,
-  #else
-    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if TRANSFER_AP_CORE_NUMBER == TRUE
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if ID_POSITION_INITIAL_APICID == TRUE
-    F14CpuAmdCoreIdPositionInInitialApicId,
-  #else
-    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-  #endif
-  #if SAVE_FEATURES == TRUE
-    (PF_CPU_SAVE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_SAVE_FEATURES) CommonAssert,
-  #endif
-  #if WRITE_FEATURES == TRUE
-    (PF_CPU_WRITE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_WRITE_FEATURES) CommonAssert,
-  #endif
-  #if SET_WARM_RESET_FLAG == TRUE
-    F14SetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if GET_WARM_RESET_FLAG == TRUE
-    F14GetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if BRAND_STRING1 == TRUE
-    GetF14BrandIdString1,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if BRAND_STRING2 == TRUE
-    GetF14BrandIdString2,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_CACHE_INFO == TRUE
-    GetF14CacheInfo,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_SYSTEM_PM_TABLE == TRUE
-    GetF14SysPmTable,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_WHEA_INIT == TRUE
-    GetF14WheaInitData,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-    F14GetPlatformTypeSpecificInfo,
-  #else
-    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-  #endif
-  #if IS_NB_PSTATE_ENABLED == TRUE
-    F14IsNbPstateEnabled,
-  #else
-    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-  #else
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #else
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #endif
-  #if BASE_FAMILY_PCI == TRUE
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #else
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (REGISTER_TABLE **) F14UnknownRegisterTables,
-  #else
-    NULL,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
-  #else
-    NULL,
-  #endif
-  #if MODEL_SPECIFIC_HT_PCI == TRUE
-    NULL,
-  #else
-    NULL,
-  #endif
-  NULL,
-  InitCacheDisabled,
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-    GetF14OnEarlyInitOnCoreTable
-  #else
-    (PF_GET_EARLY_INIT_TABLE) CommonVoid
-  #endif
-};
-
- // Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
-  #undef  FAMILY_MMIO_BASE_MASK
-  #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-#endif
-
-#undef OPT_F14_ID_TABLE
-#define OPT_F14_ID_TABLE {0x14, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
-#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
-
-#undef OPT_F14_TABLE
-#define OPT_F14_TABLE   OPT_F14_ON_CPU  OPT_F14_UNKNOWN_CPU
-
-#if OPTION_FT1_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
-  extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
-  #define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
-  #define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
-#else
-  #define F14_FT1_BRANDSTRING1
-  #define F14_FT1_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString1Tables[] =
-  {
-    F14_FT1_BRANDSTRING1
-  };
-
-  CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString2Tables[] =
-  {
-    F14_FT1_BRANDSTRING2
-  };
-
-  CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
-{
-  OPT_F14_ON_ID
-};
-
-#endif  // _OPTION_FAMILY_14H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
deleted file mode 100644
index b05bfe3..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 15h support
- *
- * This file generates the defaults tables for family 15h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37150 $   @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_15H_INSTALL_H_
-#define _OPTION_FAMILY_15H_INSTALL_H_
-
-/*
- * Pull in family specific services based on entry point
- */
-
-/*
- * Common Family 15h routines
- */
-extern F_GET_EARLY_INIT_TABLE GetF15EarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
-
-/*
- * Install family 15h model 0 support
- */
-#ifdef OPTION_FAMILY15H_OR
-  #if OPTION_FAMILY15H_OR == TRUE
-    extern F_CPU_GET_IDD_MAX F15GetProcIddMax;
-    extern F_CPU_GET_NB_PSTATE_INFO F15GetNbPstateInfo;
-    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
-    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
-    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
-    extern F_CPU_GET_TSC_RATE F15GetTscRate;
-    extern F_CPU_GET_NB_FREQ F15GetCurrentNbFrequency;
-    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
-    extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F15CommonGetNumberOfCoresForBrandstring;
-    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15GetApMailboxFromHardware;
-    extern F_CPU_SET_AP_CORE_NUMBER F15SetApCoreNumber;
-    extern F_CPU_GET_AP_CORE_NUMBER F15GetApCoreNumber;
-    extern F_CPU_TRANSFER_AP_CORE_NUMBER F15TransferApCoreNumber;
-    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
-    extern F_CPU_SAVE_FEATURES F15SaveFeatures;
-    extern F_CPU_WRITE_FEATURES F15WriteFeatures;
-    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
-    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15SysPmTable;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
-    extern F_CPU_SET_CFOH_REG SetF15CacheFlushOnHaltRegister;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-    extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F15GetPlatformTypeSpecificInfo;
-    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
-    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
-    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
-    extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15HtPhyRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15MultiLinkPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15SingleLinkPciRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F15WorkaroundsTable;
-    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
-
-    /**
-     * Core Pair and core pair primary determination table.
-     *
-     * The two fields from the core pair hardware register can be used to determine whether
-     * even number cores are primary or all cores are primary.  It can be extended if it is
-     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
-     * but they are currently not supported by the processor.
-     */
-    CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
-    {
-      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
-      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
-      {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
-      {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
-      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
-      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
-      {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
-      {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
-      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
-    };
-
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F15PciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F15MultiLinkPciRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F15OrPciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F15MsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F15OrMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F15OrSharedMsrRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F15HtPhyRegisterTable,
-        #endif
-        #if MODEL_SPECIFIC_HT_PCI == TRUE
-          &F15OrHtPhyRegisterTable,
-        #endif
-        #if BASE_FAMILY_WORKAROUNDS == TRUE
-          &F15WorkaroundsTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {HtPhyRegister, SetRegisterForHtPhyEntry},
-        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {HtHostPciRegister, SetRegisterForHtHostEntry},
-        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
-        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
-        {TokenPciRegister, SetRegisterForTokenPciEntry},
-        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F15DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F15TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F15GetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F15GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F15GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F15GetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F15CommonGetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F15LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F15CommonGetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F15GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        F15SetApCoreNumber,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F15GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        F15TransferApCoreNumber,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F15CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        // F15SaveFeatures,
-        (PF_CPU_SAVE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        // F15WriteFeatures,
-        (PF_CPU_WRITE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F15SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F15GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF15OrMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF15OrMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF15CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF15SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF15WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F15GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F15IsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F15NextLinkHasHtPhyFeats,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        F15SetHtPhyRegister,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        F15GetNextHtLinkFeatures,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F15OrRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      #if MODEL_SPECIFIC_HT_PCI == TRUE
-        (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
-      #else
-        NULL,
-      #endif
-      (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
-      InitCacheEnabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF15EarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define OR_SOCKETS 8
-    #define OR_MODULES 2
-    #define OR_RECOVERY_SOCKETS 1
-    #define OR_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
-    #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES OR_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < OR_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES OR_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F15_OR_UCODE_09
-
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_EARLY_SAMPLES == TRUE
-          extern  CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009;
-          #undef F15_OR_UCODE_09
-          #define F15_OR_UCODE_09 &CpuF15OrMicrocodePatch06000009,
-        #endif
-      #endif
-
-      CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
-      {
-        F15_OR_UCODE_09
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
-
-  #else  //  OPTION_FAMILY15H_OR == TRUE
-    #define OPT_F15_OR_CPU
-    #define OPT_F15_OR_ID
-  #endif  //  OPTION_FAMILY15H_OR == TRUE
-#else  //  defined (OPTION_FAMILY15H_OR)
-  #define OPT_F15_OR_CPU
-  #define OPT_F15_OR_ID
-#endif  //  defined (OPTION_FAMILY15H_OR)
-
-/*
- * Install unknown family 15h support
- */
-
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
-  {
-    #if BASE_FAMILY_PCI == TRUE
-      &F15PciRegisterTable,
-    #endif
-    #if BASE_FAMILY_MSR == TRUE
-      &F15MsrRegisterTable,
-    #endif
-    #if BASE_FAMILY_HT_PCI == TRUE
-      &F15HtPhyRegisterTable,
-    #endif
-    #if OPTION_MULTISOCKET == TRUE
-      #if MODEL_SPECIFIC_PCI == TRUE
-        &F15MultiLinkPciRegisterTable,
-      #endif
-    #endif
-    #if OPTION_MULTISOCKET == FALSE
-      #if MODEL_SPECIFIC_PCI == TRUE
-        &F15SingleLinkPciRegisterTable,
-      #endif
-    #endif
-    #if BASE_FAMILY_WORKAROUNDS == TRUE
-      &F15WorkaroundsTable,
-    #endif
-    // the end.
-    NULL
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-    {HtPhyRegister, SetRegisterForHtPhyEntry},
-    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
-    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
-    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-    {HtHostPciRegister, SetRegisterForHtHostEntry},
-    {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
-    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
-    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
-    {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
-    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
-{
-  0,
-  #if DISABLE_PSTATE == TRUE
-    F15DisablePstate,
-  #else
-    (PF_CPU_DISABLE_PSTATE) CommonAssert,
-  #endif
-  #if TRANSITION_PSTATE == TRUE
-    F15TransitionPstate,
-  #else
-    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-  #endif
-  #if PROC_IDD_MAX == TRUE
-    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
-  #else
-    (PF_CPU_GET_IDD_MAX) CommonAssert,
-  #endif
-  #if GET_TSC_RATE == TRUE
-    F15GetTscRate,
-  #else
-    (PF_CPU_GET_TSC_RATE) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F15GetCurrentNbFrequency,
-  #else
-    (PF_CPU_GET_NB_FREQ) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F15GetNbPstateInfo,
-  #else
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-  #endif
-  #if IS_NBCOF_INIT_NEEDED == TRUE
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
-  #else
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-  #endif
-  #if AP_INITIAL_LAUNCH == TRUE
-    F15LaunchApCore,
-  #else
-    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-  #endif
-  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonVoid,
-  #else
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-  #endif
-  #if GET_AP_MAILBOX_FROM_HW == TRUE
-    F15GetApMailboxFromHardware,
-  #else
-    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-  #endif
-  #if SET_AP_CORE_NUMBER == TRUE
-    F15SetApCoreNumber,
-  #else
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if GET_AP_CORE_NUMBER == TRUE
-    F15GetApCoreNumber,
-  #else
-    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if TRANSFER_AP_CORE_NUMBER == TRUE
-    F15TransferApCoreNumber,
-  #else
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if ID_POSITION_INITIAL_APICID == TRUE
-    F15CpuAmdCoreIdPositionInInitialApicId,
-  #else
-    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-  #endif
-  #if SAVE_FEATURES == TRUE
-    // F15SaveFeatures,
-    (PF_CPU_SAVE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_SAVE_FEATURES) CommonAssert,
-  #endif
-  #if WRITE_FEATURES == TRUE
-    // F15WriteFeatures,
-    (PF_CPU_WRITE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_WRITE_FEATURES) CommonAssert,
-  #endif
-  #if SET_WARM_RESET_FLAG == TRUE
-    F15SetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if GET_WARM_RESET_FLAG == TRUE
-    F15GetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if BRAND_STRING1 == TRUE
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if BRAND_STRING2 == TRUE
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_CACHE_INFO == TRUE
-    GetF15CacheInfo,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_SYSTEM_PM_TABLE == TRUE
-    GetF15SysPmTable,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_WHEA_INIT == TRUE
-    GetF15WheaInitData,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-    F15GetPlatformTypeSpecificInfo,
-  #else
-    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-  #endif
-  #if IS_NB_PSTATE_ENABLED == TRUE
-    F15IsNbPstateEnabled,
-  #else
-    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    F15NextLinkHasHtPhyFeats,
-  #else
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    F15SetHtPhyRegister,
-  #else
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #endif
-  #if BASE_FAMILY_PCI == TRUE
-    F15GetNextHtLinkFeatures,
-  #else
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (REGISTER_TABLE **) F15UnknownRegisterTables,
-  #else
-    NULL,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
-  #else
-    NULL,
-  #endif
-  NULL,
-  NULL,
-  InitCacheEnabled,
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-    GetF15EarlyInitOnCoreTable
-  #else
-    (PF_GET_EARLY_INIT_TABLE) CommonVoid
-  #endif
-};
-
-// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
-  #undef  FAMILY_MMIO_BASE_MASK
-  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
-#endif
-
-
-#undef OPT_F15_ID_TABLE
-#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
-#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
-
-#undef OPT_F15_TABLE
-#define OPT_F15_TABLE   OPT_F15_OR_CPU  OPT_F15_UNKNOWN_CPU
-
-
-#if OPTION_G34_SOCKET_SUPPORT == TRUE
-  #define F15_G34_BRANDSTRING1 NULL,
-  #define F15_G34_BRANDSTRING2 NULL,
-#else
-  #define F15_G34_BRANDSTRING1
-  #define F15_G34_BRANDSTRING2
-#endif
-#if OPTION_C32_SOCKET_SUPPORT == TRUE
-  #define F15_C32_BRANDSTRING1 NULL,
-  #define F15_C32_BRANDSTRING2 NULL,
-#else
-  #define F15_C32_BRANDSTRING1
-  #define F15_C32_BRANDSTRING2
-#endif
-#if OPTION_AM3_SOCKET_SUPPORT == TRUE
-  #define F15_AM3_BRANDSTRING1 NULL,
-  #define F15_AM3_BRANDSTRING2 NULL,
-#else
-  #define F15_AM3_BRANDSTRING1
-  #define F15_AM3_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
-  {
-    F15_G34_BRANDSTRING1
-    F15_C32_BRANDSTRING1
-    F15_AM3_BRANDSTRING1
-  };
-
-  CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
-  {
-    F15_G34_BRANDSTRING2
-    F15_C32_BRANDSTRING2
-    F15_AM3_BRANDSTRING2
-  };
-
-  CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
-{
-  OPT_F15_OR_ID
-};
-
-#endif  // _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h
deleted file mode 100644
index e7d921e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD GFX Recovery option API.
- *
- * Contains structures and values used to control the GfxRecovery option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GFX_RECOVERY_H_
-#define _OPTION_GFX_RECOVERY_H_
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
-  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
-  );
-
-#define GFX_RECOVERY_STRUCT_VERSION  0x01
-
-/// The Option Configuration of GFX Recovery
-typedef struct  {
-  UINT16              OptGfxRecoveryVersion;       ///< The version number of GFX Recovery
-  OPTION_GFX_RECOVERY_FEATURE  *GfxRecoveryFeature;        ///< The Option Feature of GFX Recovery
-} OPTION_GFX_RECOVERY_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif  // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h
deleted file mode 100644
index d271cd0..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GfxRecovery
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 39275 $   @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
-#define _OPTION_GFX_RECOVERY_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-
-#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGnb.h b/src/vendorcode/amd/agesa/Include/OptionGnb.h
deleted file mode 100644
index 5f3fbd6..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGnb.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD ALIB option API.
- *
- * Contains structures and values used to control the ALIB option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 40151 $   @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GNB_H_
-#define _OPTION_GNB_H_
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-
-typedef AGESA_STATUS OPTION_GNB_FEATURE (
-  IN       AMD_CONFIG_PARAMS    *StdHeader
-  );
-
-/// The Option Configuration of ALIB
-typedef struct {
-  UINT64                Type;                   ///< Type
-  OPTION_GNB_FEATURE    *GnbFeature;            ///< The GNB Feature
-} OPTION_GNB_CONFIGURATION;
-
-/// The Build time options configuration
-typedef struct {
-  BOOLEAN              IgfxModeAsPcieEp;        ///< Itegrated Gfx mode Pcie EP or Legacy
-  BOOLEAN              LclkDeepSleepEn;         ///< Default for LCLK deep sleep
-  BOOLEAN              LclkDpmEn;               ///< Default for LCLK DPM
-  BOOLEAN              GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
-  BOOLEAN              SmuSclkClockGatingEnable;///< Control SMU SCLK gating
-  BOOLEAN              PcieAspmBlackListEnable;       ///< Control Pcie Aspm Black List
-} GNB_BUILD_OPTIONS;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif  // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h
deleted file mode 100644
index d8acee7..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h
+++ /dev/null
@@ -1,449 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GNB
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 40151 $   @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GNB_INSTALL_H_
-#define _OPTION_GNB_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define GNB_TYPE_LN OPTION_FAMILY12H
-#define GNB_TYPE_ON OPTION_FAMILY14H
-#define GNB_TYPE_KR FALSE
-#define GNB_TYPE_TN FALSE
-
-#ifndef CFG_IGFX_AS_PCIE_EP
-  #define CFG_IGFX_AS_PCIE_EP     TRUE
-#endif
-
-#ifndef CFG_LCLK_DEEP_SLEEP_EN
-  #if (GNB_TYPE_ON == TRUE)
-    #define  CFG_LCLK_DEEP_SLEEP_EN   TRUE
-  #else
-    #define  CFG_LCLK_DEEP_SLEEP_EN   FALSE
-  #endif
-#endif
-
-#ifndef CFG_LCLK_DPM_EN
-  #if (GNB_TYPE_ON == TRUE)
-    #define CFG_LCLK_DPM_EN          TRUE
-  #else
-    #define CFG_LCLK_DPM_EN          FALSE
-  #endif
-#endif
-
-#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
-  #define CFG_GMC_POWER_GATE_STUTTER_ONLY     FALSE
-#endif
-
-#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
-  #if (GNB_TYPE_ON == TRUE)
-    #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE   TRUE
-  #else
-    #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE   FALSE
-  #endif
-#endif
-
-#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
-  #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE     TRUE
-#endif
-
-GNB_BUILD_OPTIONS  GnbBuildOptions = {
-  CFG_IGFX_AS_PCIE_EP,
-  CFG_LCLK_DEEP_SLEEP_EN,
-  CFG_LCLK_DPM_EN,
-  CFG_GMC_POWER_GATE_STUTTER_ONLY,
-  CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
-  CFG_PCIE_ASPM_BLACK_LIST_ENABLE
-};
-
-
-
-#if (AGESA_ENTRY_INIT_EARLY == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_EARLY_INIT
-    #define OPTION_NB_EARLY_INIT TRUE
-  #endif
-  #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                NbInitAtEarly;
-    #define OPTION_NBINITATEARLY_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
-  #else
-    #define OPTION_NBINITATEARLY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-// SMU init
-  #ifndef OPTION_SMU
-    #define OPTION_SMU  TRUE
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                F12NbSmuInitFeature;
-    #define OPTION_F12NBSMUINITFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbSmuInitFeature},
-  #else
-    #define OPTION_F12NBSMUINITFEATURE_ENTRY
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                F14NbSmuInitFeature;
-    #define OPTION_F14NBSMUINITFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbSmuInitFeature},
-  #else
-    #define OPTION_F14NBSMUINITFEATURE_ENTRY
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                KRNbSmuInitFeature;
-    #define OPTION_KRNBSMUINITFEATURE_ENTRY          {AMD_FAMILY_KR, KRNbSmuInitFeature},
-  #else
-    #define OPTION_KRNBSMUINITFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_CONFIG_INIT
-    #define OPTION_PCIE_CONFIG_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                  PcieConfigurationInit;
-    #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
-  #else
-    #define OPTION_PCIECONFIGURATIONINIT_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_EARLY_INIT
-    #define OPTION_PCIE_EARLY_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                   PcieInitAtEarly;
-    #define OPTION_PCIEINITATEARLY_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
-  #else
-    #define  OPTION_PCIEINITATEARLY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
-    OPTION_NBINITATEARLY_ENTRY
-    OPTION_F12NBSMUINITFEATURE_ENTRY
-    OPTION_F14NBSMUINITFEATURE_ENTRY
-    OPTION_KRNBSMUINITFEATURE_ENTRY
-    OPTION_PCIECONFIGURATIONINIT_ENTRY
-    OPTION_PCIEINITATEARLY_ENTRY
-    {0, NULL}
-  };
-
-#endif
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_CONFIG_POST_INIT
-    #define OPTION_GFX_CONFIG_POST_INIT TRUE
-  #endif
-  #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                   GfxConfigPostInterface;
-    #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
-  #else
-    #define  OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_POST_INIT
-    #define OPTION_GFX_POST_INIT TRUE
-  #endif
-  #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                   GfxInitAtPost;
-    #define OPTION_GFXINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
-  #else
-   #define  OPTION_GFXINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_POST_INIT
-    #define OPTION_NB_POST_INIT TRUE
-  #endif
-  #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtPost;
-    #define OPTION_NBINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
-  #else
-    #define OPTION_NBINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_POST_INIT
-    #define OPTION_PCIE_POST_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtPost;
-    #define OPTION_PCIEINITATPOST_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
-  #else
-    #define OPTION_PCIEINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
-    OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-    OPTION_GFXINITATPOST_ENTRY
-    {0, NULL}
-  };
-
-  OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
-    OPTION_NBINITATPOST_ENTRY
-    OPTION_PCIEINITATPOST_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_ENV == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_FUSE_TABLE_INIT
-    #define OPTION_FUSE_TABLE_INIT TRUE
-  #endif
-  #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbFuseTableFeature;
-    #define OPTION_NBFUSETABLEFEATURE_ENTRY             {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
-  #else
-    #define OPTION_NBFUSETABLEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_ENV_INIT
-    #define OPTION_NB_ENV_INIT TRUE
-  #endif
-  #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtEnv;
-    #define OPTION_NBINITATENVT_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
-  #else
-    #define OPTION_NBINITATENVT_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_CONFIG_ENV_INIT
-    #define OPTION_GFX_CONFIG_ENV_INIT TRUE
-  #endif
-  #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
-    #define OPTION_GFXCONFIGENVINTERFACE_ENTRY           {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
-  #else
-    #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
-  #endif
-
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_ENV_INIT
-    #define OPTION_GFX_ENV_INIT TRUE
-  #endif
-  #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  GfxInitAtEnvPost;
-    #define OPTION_GFXINITATENVPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
-  #else
-    #define OPTION_GFXINITATENVPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_POWER_GATE
-    #define OPTION_POWER_GATE TRUE
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  F12NbPowerGateFeature;
-    #define OPTION_F12NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbPowerGateFeature},
-  #else
-    #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                  F14NbPowerGateFeature;
-    #define OPTION_F14NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbPowerGateFeature},
-  #else
-    #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                  KRNbPowerGateFeature;
-    #define OPTION_KRNBPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_KR, KRNbPowerGateFeature},
-  #else
-    #define OPTION_KRNBPOWERGATEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_ENV_INIT
-    #define OPTION_PCIE_ENV_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtEnv;
-    #define OPTION_PCIEINITATENV_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
-  #else
-    #define OPTION_PCIEINITATENV_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-
-  OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
-    OPTION_NBFUSETABLEFEATURE_ENTRY
-    OPTION_NBINITATENVT_ENTRY
-    OPTION_PCIEINITATENV_ENTRY
-    OPTION_GFXCONFIGENVINTERFACE_ENTRY
-    OPTION_GFXINITATENVPOST_ENTRY
-    OPTION_F12NBPOWERGATEFEATURE_ENTRY
-    OPTION_F14NBPOWERGATEFEATURE_ENTRY
-    OPTION_KRNBPOWERGATEFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_MID == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTOIN_GNB_CABLESAFE
-    #define OPTOIN_GNB_CABLESAFE TRUE
-  #endif
-  #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  GnbCableSafeEntry;
-    #define OPTION_GNBCABLESAFEENTRY_ENTRY              {AMD_FAMILY_LN, GnbCableSafeEntry},
-  #else
-    #define OPTION_GNBCABLESAFEENTRY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTOIN_NB_LCLK_NCLK_RATIO
-    #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
-  #endif
-  #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                  F14NbLclkNclkRatioFeature;
-    #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY      {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
-  #else
-    #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
-  #endif
-  #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                  KRNbLclkNclkRatioFeature;
-    #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY       {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature},
-  #else
-    #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_LCLK_DPM_INIT
-    #define OPTION_NB_LCLK_DPM_INIT TRUE
-  #endif
-  #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbLclkDpmFeature;
-    #define OPTION_NBLCLKDPMFEATURE_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
-  #else
-    #define OPTION_NBLCLKDPMFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_POWER_GATE
-    #define OPTION_PCIE_POWER_GATE TRUE
-  #endif
-  #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  PciePowerGateFeature;
-    #define OPTION_PCIEPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_LN, PciePowerGateFeature},
-  #else
-    #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_MID_INIT
-    #define OPTION_GFX_MID_INIT TRUE
-  #endif
-  #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  GfxInitAtMidPost;
-    #define OPTION_GFXINITATMIDPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
-  #else
-    #define OPTION_GFXINITATMIDPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
-    #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
-  #endif
-  #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                 GfxIntegratedInfoTableEntry;
-    #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY        {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
-  #else
-    #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIe_MID_INIT
-    #define OPTION_PCIe_MID_INIT TRUE
-  #endif
-  #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtMid;
-    #define OPTION_PCIEINITATMID_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
-  #else
-    #define OPTION_PCIEINITATMID_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_MID_INIT
-    #define OPTION_NB_MID_INIT TRUE
-  #endif
-  #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtLatePost;
-    #define OPTION_NBINITATLATEPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
-  #else
-    #define OPTION_NBINITATLATEPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
-    OPTION_GFXINITATMIDPOST_ENTRY
-    OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
-    OPTION_GNBCABLESAFEENTRY_ENTRY
-    OPTION_PCIEINITATMID_ENTRY
-    OPTION_NBINITATLATEPOST_ENTRY
-    OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
-    OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
-    OPTION_NBLCLKDPMFEATURE_ENTRY
-    OPTION_PCIEPOWERGATEFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_ALIB
-    #define OPTION_ALIB FALSE
-  #endif
-  #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                  PcieAlibFeature;
-    #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
-  #else
-    #define OPTION_PCIEALIBFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
-    OPTION_PCIEALIBFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if  (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-  S3_DISPATCH_FUNCTION  NbSmuServiceRequestS3Script;
-  S3_DISPATCH_FUNCTION  PcieLateRestoreS3Script;
-  S3_DISPATCH_FUNCTION  NbSmuIndirectWriteS3Script;
-  #define GNB_S3_DISPATCH_FUNCTION_TABLE \
-  {S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \
-  {S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \
-  {S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script},
-#endif
-
-#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h
deleted file mode 100644
index 171e9ea..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HT Assist
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_ASSIST_INSTALL_H_
-#define _OPTION_HT_ASSIST_INSTALL_H_
-
-#include "cpuHtAssist.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_HT_ASSIST_FEAT
-#define F10_HT_ASSIST_SUPPORT
-#define F15_HT_ASSIST_SUPPORT
-#define HT_ASSIST_AP_DISABLE_CACHE
-#define HT_ASSIST_AP_ENABLE_CACHE
-
-#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-    #ifdef  OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_HY == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
-          #undef OPTION_HT_ASSIST_FEAT
-          #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
-          extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
-          #undef F10_HT_ASSIST_SUPPORT
-          #define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
-        #endif
-      #endif
-    #endif
-
-    #ifdef  OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
-        #undef OPTION_HT_ASSIST_FEAT
-        #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
-        extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F15HtAssist;
-        #undef F15_HT_ASSIST_SUPPORT
-        #define F15_HT_ASSIST_SUPPORT {AMD_FAMILY_15, &F15HtAssist},
-      #endif
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
-    {
-      F10_HT_ASSIST_SUPPORT
-      F15_HT_ASSIST_SUPPORT
-      {0, NULL}
-    };
-    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
-    {
-      (sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-      &HtAssistFamilyServiceArray[0]
-    };
-
-    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
-    #undef HT_ASSIST_AP_DISABLE_CACHE
-    #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
-    #undef HT_ASSIST_AP_ENABLE_CACHE
-    #define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
-  #endif
-#endif
-
-#endif  // _OPTION_HT_ASSIST_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/Include/OptionHtInstall.h
deleted file mode 100644
index 637f069..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHtInstall.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Ht
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_INSTALL_H_
-#define _OPTION_HT_INSTALL_H_
-
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htTopologies.h"
-/*
- * Advanced Option only, hardware socket naming is the preferred method.
- */
-#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
-#else
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
-#endif
-
-/*
- * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
- */
-#ifndef OPTION_IS_RECOVERY_HT
-  #define OPTION_IS_RECOVERY_HT TRUE
-#endif
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition.
- */
-
-#ifndef OPTION_MULTISOCKET
-  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-/*
- * Based on user level options, set Ht internal options.
- * For now, Family 10h support will assume single module.  For multi module,
- * this will have to be changed to not set non-coherent only.
- */
-#define OPTION_HT_NON_COHERENT_ONLY FALSE
-
-#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
-/* Fusion Families do not need a non-coherent only option. */
-#else
-  // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
-  #if OPTION_G34_SOCKET_SUPPORT == FALSE
-  // Hydra has coherent support, other Family 10h should follow MultiSocket support.
-    #if OPTION_MULTISOCKET == FALSE
-      #undef OPTION_HT_NON_COHERENT_ONLY
-      #define OPTION_HT_NON_COHERENT_ONLY TRUE
-    #endif
-  #endif
-#endif
-
-/*
- * Macros will generate the correct item reference based on options
- */
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  // Select the interface and features
-  #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
-    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
-    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
-  #else
-    // Family 10h and 15h
-    #if OPTION_HT_NON_COHERENT_ONLY == FALSE
-      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesDefault
-      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceDefault
-    #else
-      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNonCoherentOnly
-      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceNonCoherentOnly
-    #endif
-  #endif
-  // Select Northbridge components
-  #if OPTION_FAMILY10H == TRUE
-    #if OPTION_HT_NON_COHERENT_ONLY == TRUE
-      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
-    #else
-      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbDefault, &HtFam10RevDNbDefault,
-    #endif
-  #else
-    #define INTERNAL_HT_OPTION_FAM10_NB
-  #endif
-  #if OPTION_FAMILY12H == TRUE
-    #define INTERNAL_HT_OPTION_FAM12_NB     &HtFam12Nb,
-  #else
-    #define INTERNAL_HT_OPTION_FAM12_NB
-  #endif
-  #if OPTION_FAMILY14H == TRUE
-    #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
-  #else
-    #define INTERNAL_HT_OPTION_FAM14_NB
-  #endif
-  #if OPTION_FAMILY15H == TRUE
-    #if OPTION_HT_NON_COHERENT_ONLY == TRUE
-      #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbNonCoherentOnly,
-    #else
-      #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbDefault,
-    #endif
-  #else
-    #define INTERNAL_HT_OPTION_FAM15_NB
-  #endif
-
-  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
-  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
-    #undef INTERNAL_ONLY_NB_LIST_ITEM
-    #define INTERNAL_ONLY_NB_LIST_ITEM
-  #endif
-
-  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
-   * is ok to have a comma because the final item (NULL) is added below.
-   */
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
-                                             INTERNAL_ONLY_NB_LIST_ITEM \
-                                             INTERNAL_HT_OPTION_FAM10_NB \
-                                             INTERNAL_HT_OPTION_FAM15_NB \
-                                             INTERNAL_HT_OPTION_FAM12_NB \
-                                             INTERNAL_HT_OPTION_FAM14_NB
-
-#else
-  // Not Init Early
-  #define INTERNAL_HT_OPTION_FEATURES     NULL
-  #define INTERNAL_HT_OPTION_INTERFACE    NULL
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
-  #define HT_OPTIONS_PLATFORM             NULL
-  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-#endif
-
-#ifdef AGESA_ENTRY_INIT_EARLY
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-
-    extern HT_FEATURES HtFeaturesDefault;
-    extern HT_FEATURES HtFeaturesNonCoherentOnly;
-    extern HT_FEATURES HtFeaturesNone;
-    extern HT_INTERFACE HtInterfaceDefault;
-    extern HT_INTERFACE HtInterfaceNonCoherentOnly;
-    extern HT_INTERFACE HtInterfaceMapsOnly;
-    extern HT_INTERFACE HtInterfaceNone;
-    extern NORTHBRIDGE HtFam10NbDefault;
-    extern NORTHBRIDGE HtFam10RevDNbDefault;
-    extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
-    extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
-    extern NORTHBRIDGE HtFam12Nb;
-    extern NORTHBRIDGE HtFam14Nb;
-    extern NORTHBRIDGE HtFam10NbNone;
-    extern NORTHBRIDGE HtFam15NbDefault;
-    extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
-
-    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
-      INTERNAL_HT_OPTION_SUPPORTED_NBS
-      NULL
-    };
-
-    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
-    {
-      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
-      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
-      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
-      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
-      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
-      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
-      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
-      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
-    };
-    #ifndef HT_OPTIONS_PLATFORM
-      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
-    #endif
-
-    /**
-     * A list of all the supported topologies.
-     *
-     */
-    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
-      {
-        amdHtTopologySingleNode,
-        amdHtTopologyDualNode,
-        amdHtTopologyThreeLine,
-        amdHtTopologyTriangle,
-        amdHtTopologyFourLine,
-        amdHtTopologyFourStar,
-        amdHtTopologyFourDegenerate,
-        amdHtTopologyFourSquare,
-        amdHtTopologyFourKite,
-        amdHtTopologyFourFully,
-        amdHtTopologyFiveFully,
-        amdHtTopologyFiveTwistedLadder,
-        amdHtTopologySixFully,
-        amdHtTopologySixDoubloonLower,
-        amdHtTopologySixDoubloonUpper,
-        amdHtTopologySixTwistedLadder,
-        amdHtTopologySevenFully,
-        amdHtTopologySevenTwistedLadder,
-        amdHtTopologyEightFully,
-        amdHtTopologyEightDoubloon,
-        amdHtTopologyEightTwistedLadder,
-        amdHtTopologyEightStraightLadder,
-        amdHtTopologySixTwinTriangles,
-        amdHtTopologyEightTwinFullyFourWays,
-        NULL
-      };
-      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
-    #endif
-
-    /**
-     * Declare the instance of the Ht option configuration structure
-     */
-    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
-      OPTION_IS_RECOVERY_HT,
-      CFG_SET_HTCRC_SYNC_FLOOD,
-      CFG_USE_UNIT_ID_CLUMPING,
-      HT_OPTIONS_PLATFORM,
-      INTERNAL_HT_OPTION_INTERFACE,
-      INTERNAL_HT_OPTION_FEATURES,
-      &HtInstalledFamilyNorthbridgeList,
-      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-    };
-
-  #endif
-#endif
-
-#ifndef OPTION_HT_INIIT_RESET_ENTRY
-
-  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
-
-  #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
-    #undef OPTION_HT_INIIT_RESET_ENTRY
-    #define OPTION_HT_INIIT_RESET_ENTRY NULL
-  #endif
-
-  #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
-    #undef OPTION_HT_INIIT_RESET_ENTRY
-    #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
-  #endif
-
-#endif
-
-#ifdef AGESA_ENTRY_INIT_RESET
-  #if AGESA_ENTRY_INIT_RESET == TRUE
-
-    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      0                                            // Unused by options
-    };
-
-    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
-      OPTION_HT_INIIT_RESET_ENTRY
-    };
-  #endif
-
-#endif
-
-#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h
deleted file mode 100644
index 745914f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HW C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HW_C1E_INSTALL_H_
-#define _OPTION_HW_C1E_INSTALL_H_
-
-#include "cpuHwC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_HW_C1E_FEAT
-#define F10_HW_C1E_SUPPORT
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef OPTION_FAMILY10H
-    #if OPTION_FAMILY10H == TRUE
-      #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
-        #undef OPTION_HW_C1E_FEAT
-        #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
-        extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
-        #undef F10_HW_C1E_SUPPORT
-        #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
-      #endif
-    #endif
-  #endif
-  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
-  {
-    F10_HW_C1E_SUPPORT
-    {0, NULL}
-  };
-  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
-  {
-    (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-    &HwC1eFamilyServiceArray[0]
-  };
-#endif
-
-#endif  // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h
deleted file mode 100644
index 11de68e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * IDS Option Install File
- *
- * This file generates the defaults tables for family 10h model 5 processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-#ifndef _OPTION_IDS_INSTALL_H_
-#define _OPTION_IDS_INSTALL_H_
-#include "Ids.h"
-#include "IdsHt.h"
-#include "IdsLib.h"
-#ifdef __IDS_EXTENDED__
-  #include OPTION_IDS_EXT_INSTALL_FILE
-#endif
-
-#define IDS_LATE_RUN_AP_TASK
-
-#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-    // Check for all families which include HT Features.
-    #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
-      #undef M_HTIDS_PORT_OVERRIDE_HOOK
-      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
-    #endif
-  #endif
-#endif // OPTION_IDS_LEVEL
-CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
-
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_LATE == TRUE)
-    #undef IDS_LATE_RUN_AP_TASK
-    #define IDS_LATE_RUN_AP_TASK
-  #endif
-#endif // OPTION_IDS_LEVEL
-
-#if (IDSOPT_TRACING_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_POST == TRUE)
-    #include <mu.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
-      { (UINT32) (UINT64) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
-      { (UINT32) (UINT64) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
-    };
-  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-    #include <mru.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
-      { (UINT32) (UINT64) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
-      { (UINT32) (UINT64) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
-    };
-  #else
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
-      { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
-      { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
-    };
-  #endif
-#endif
-
-
-///Ids Feat Options
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-
-    #ifndef OPTION_IDS_EXTEND_FEATS
-      #define OPTION_IDS_EXTEND_FEATS
-    #endif
-
-    #define OPTION_IDS_FEAT_ECCCTRL\
-                OPTION_IDS_FEAT_ECCCTRL_F10 \
-                OPTION_IDS_FEAT_ECCCTRL_F12 \
-                OPTION_IDS_FEAT_ECCCTRL_F15
-
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
-                OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
-                OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-
-    #define OPTION_IDS_FEAT_CPB_CTRL\
-                OPTION_IDS_FEAT_CPB_CTRL_F12
-
-    #define OPTION_IDS_FEAT_HTC_CTRL\
-                OPTION_IDS_FEAT_HTC_CTRL_F15
-
-    #define OPTION_IDS_FEAT_MEMORY_MAPPING\
-                OPTION_IDS_FEAT_MEMORY_MAPPING_F15
-
-    #define OPTION_IDS_FEAT_HT_ASSIST\
-                OPTION_IDS_FEAT_HT_ASSIST_F10HY \
-                OPTION_IDS_FEAT_HT_ASSIST_F15
-
-    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
-                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
-                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
-
-/*----------------------------------------------------------------------------
- *                        Family 10 feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
-    #define OPTION_IDS_FEAT_ECCCTRL_F10
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-//Ecc symbol size
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
-        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
-        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
-
-//ECC scrub control
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
-        #undef OPTION_IDS_FEAT_ECCCTRL_F10
-        #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
-      #endif
-    #endif
-
-    //Misc Features
-    #define OPTION_IDS_FEAT_HT_ASSIST_F10HY
-    #ifdef OPTION_FAMILY10H_HY
-      #if OPTION_FAMILY10H_HY == TRUE
-        #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
-
-        #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
-                    &IdsFeatHtAssistBlockPlatformCfgF10Hy,
-      #endif
-    #endif
-/*----------------------------------------------------------------------------
- *                        Family 12 feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
-    #define OPTION_IDS_FEAT_ECCCTRL_F12
-    #define OPTION_IDS_FEAT_CPB_CTRL_F12
-    #ifdef OPTION_FAMILY12H
-      #if OPTION_FAMILY12H == TRUE
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
-        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
-        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
-
-        //ECC scrub control
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
-        #undef OPTION_IDS_FEAT_ECCCTRL_F12
-        #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
-
-        #undef OPTION_IDS_FEAT_CPB_CTRL_F12
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
-        #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
-
-      #endif
-    #endif
-
-/*----------------------------------------------------------------------------
- *                        Family 14 feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
-        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
-      #endif
-    #endif
-
-/*----------------------------------------------------------------------------
- *                        Family 15 feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_HTC_CTRL_F15
-    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15
-    #define OPTION_IDS_FEAT_HT_ASSIST_F15
-    #define OPTION_IDS_FEAT_ECCCTRL_F15
-    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15;
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15;
-        #undef OPTION_IDS_FEAT_HTC_CTRL_F15
-        #define OPTION_IDS_FEAT_HTC_CTRL_F15\
-                    &IdsFeatHtcControlBlockF15,\
-                    &IdsFeatHtcControlLateBlockF15,
-
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15;
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15;
-        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15
-        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15\
-        &IdsFeatMemoryMappingPostBeforeBlockF15,\
-        &IdsFeatMemoryMappingChIntlvBlockF15,
-
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15;
-        #undef OPTION_IDS_FEAT_HT_ASSIST_F15
-        #define OPTION_IDS_FEAT_HT_ASSIST_F15\
-        &IdsFeatHtAssistBlockPlatformCfgF15,
-
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15;
-        #undef OPTION_IDS_FEAT_ECCCTRL_F15
-        #define OPTION_IDS_FEAT_ECCCTRL_F15 &IdsFeatEccCtrlBlockF15,
-
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15;
-        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
-        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 &IdsFeatEccSymbolSizeBlockF15,
-
-      #endif
-    #endif
-
-
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
-    {
-      IDS_FEAT_UCODE_UPDATE,
-      IDS_ALL_CORES,
-      IDS_UCODE,
-      IDS_FAMILY_ALL,
-      IdsSubUCode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
-    {
-      IDS_FEAT_POWER_POLICY,
-      IDS_ALL_CORES,
-      IDS_PLATFORMCFG_OVERRIDE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerPolicyOverride
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
-    {
-      IDS_FEAT_TARGET_PSTATE,
-      IDS_BSP_ONLY,
-      IDS_INIT_LATE_AFTER,
-      IDS_FAMILY_ALL,
-      IdsSubTargetPstate
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
-    {
-      IDS_FEAT_POSTPSTATE,
-      IDS_ALL_CORES,
-      IDS_CPU_Early_Override,
-      IDS_FAMILY_ALL,
-      IdsSubPostPState
-    };
-
-    //Dram controller Features
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
-    {
-      IDS_FEAT_DCT_ALLMEMCLK,
-      IDS_BSP_ONLY,
-      IDS_ALL_MEMORY_CLOCK,
-      IDS_FAMILY_ALL,
-      IdsSubAllMemClkEn
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
-    {
-      IDS_FEAT_DCT_GANGMODE,
-      IDS_BSP_ONLY,
-      IDS_GANGING_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubGangingMode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
-    {
-      IDS_FEAT_DCT_BURSTLENGTH,
-      IDS_BSP_ONLY,
-      IDS_BURST_LENGTH32,
-      AMD_FAMILY_10,
-      IdsSubBurstLength32
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_INIT_POST_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownCtrl
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
-    {
-      IDS_FEAT_DCT_DLLSHUTDOWN,
-      IDS_BSP_ONLY,
-      IDS_DLL_SHUT_DOWN,
-      IDS_FAMILY_ALL,
-      IdsSubDllShutDownSR
-    };
-
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_POWERDOWN_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownMode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
-    {
-      IDS_FEAT_HDTOUT,
-      IDS_BSP_ONLY,
-      IDS_INIT_EARLY_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubHdtOut
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
-    {
-      IDS_FEAT_HT_SETTING,
-      IDS_BSP_ONLY,
-      IDS_HT_CONTROL,
-      IDS_FAMILY_ALL,
-      IdsSubHtLinkControl
-    };
-
-    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-    {
-      &IdsFeatUcodeBlock,
-      &IdsFeatPowerPolicyBlock,
-
-      &IdsFeatTargetPstateBlock,
-
-      &IdsFeatPostPstateBlock,
-
-      OPTION_IDS_FEAT_ECCSYMBOLSIZE
-
-      OPTION_IDS_FEAT_ECCCTRL
-
-      &IdsFeatDctAllMemClkBlock,
-
-      &IdsFeatDctGangModeBlock,
-
-      &IdsFeatDctBurstLengthBlock,
-
-      &IdsFeatDctPowerDownCtrlBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      OPTION_IDS_FEAT_HT_ASSIST
-
-      &IdsFeatHdtOutBlock,
-
-      &IdsFeatHtSettingBlock,
-
-      OPTION_IDS_FEAT_GNB_PLATFORMCFG
-
-      OPTION_IDS_FEAT_CPB_CTRL
-
-      OPTION_IDS_FEAT_HTC_CTRL
-
-      OPTION_IDS_FEAT_MEMORY_MAPPING
-
-      OPTION_IDS_EXTEND_FEATS
-
-      NULL
-    };
-  #else
-    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-    {
-      NULL
-    };
-  #endif//IDSOPT_CONTROL_ENABLED
-#else
-  CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-  {
-    NULL
-  };
-#endif// IDSOPT_IDS_ENABLED
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h
deleted file mode 100644
index f15682f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: IO C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_IO_CSTATE_INSTALL_H_
-#define _OPTION_IO_CSTATE_INSTALL_H_
-
-#include "cpuIoCstate.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define OPTION_IO_CSTATE_FEAT
-#define F10_IO_CSTATE_SUPPORT
-#define F12_IO_CSTATE_SUPPORT
-#define F14_IO_CSTATE_SUPPORT
-#define F15_IO_CSTATE_SUPPORT
-
-#if OPTION_IO_CSTATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_PH == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
-          #undef F10_IO_CSTATE_SUPPORT
-          #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY12H
-      #if OPTION_FAMILY12H == TRUE
-        #if OPTION_FAMILY12H_LN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
-          #undef F12_IO_CSTATE_SUPPORT
-          #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        #if OPTION_FAMILY14H_ON == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
-          #undef F14_IO_CSTATE_SUPPORT
-          #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14_ON, &F14IoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_OR == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15IoCstateSupport;
-          #undef F15_IO_CSTATE_SUPPORT
-          #define F15_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15IoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
-{
-  F10_IO_CSTATE_SUPPORT
-  F12_IO_CSTATE_SUPPORT
-  F14_IO_CSTATE_SUPPORT
-  F15_IO_CSTATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
-{
-  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &IoCstateFamilyServiceArray[0]
-};
-
-#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h
deleted file mode 100644
index 6e03fea..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-
-#include "cpuLowPwrPstate.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-#define F15_LOW_PWR_PSTATE_SUPPORT
-
-#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_OR == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
-          #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-          #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
-          extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15LowPwrPstateSupport;
-          #undef F15_LOW_PWR_PSTATE_SUPPORT
-          #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15LowPwrPstateSupport},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
-{
-  F15_LOW_PWR_PSTATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
-{
-  (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &LowPwrPstateFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemory.h b/src/vendorcode/amd/agesa/Include/OptionMemory.h
deleted file mode 100644
index 1d4c08f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemory.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Memory option API.
- *
- * Contains structures and values used to control the Memory option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_H_
-#define _OPTION_MEMORY_H_
-
-/* Memory Includes */
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "ma.h"
-#include "mp.h"
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define MAX_FF_TYPES      6   ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/*
-* STANDARD MEMORY FEATURE FUNCTION POINTER
-*/
-
-typedef BOOLEAN OPTION_MEM_FEATURE_NB (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-typedef BOOLEAN MEM_TECH_FEAT (
-  IN OUT   MEM_TECH_BLOCK *TechPtr
-  );
-
-typedef UINT8 MEM_TABLE_FEAT (
-  IN OUT   MEM_TABLE_ALIAS **MTPtr
-  );
-
-#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION  0x01
-
-/**
- *  MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
- *  memory feature implementation functions.  It contains vectors for all of the
- *  features that are supported by the various Northbridge devices supported by
- *  AGESA.
- */
-typedef struct _MEM_FEAT_BLOCK_NB {
-  UINT16              OptMemFeatVersion; ///< Version of memory feature block.
-  OPTION_MEM_FEATURE_NB  *OnlineSpare; ///< Online spare support.
-  OPTION_MEM_FEATURE_NB  *InterleaveBanks; ///< Bank (Chip select) interleaving support.
-  OPTION_MEM_FEATURE_NB  *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
-  OPTION_MEM_FEATURE_NB  *CheckInterleaveNodes; ///< Check for Node interleaving support.
-  OPTION_MEM_FEATURE_NB  *InterleaveNodes; ///< Node interleaving support.
-  OPTION_MEM_FEATURE_NB  *InterleaveChannels; ///< Channel interleaving support.
-  OPTION_MEM_FEATURE_NB  *InterleaveRegion;  ///< Interleave Region support.
-  OPTION_MEM_FEATURE_NB  *CheckEcc; ///< Check for ECC support.
-  OPTION_MEM_FEATURE_NB  *InitEcc; ///< ECC support.
-  OPTION_MEM_FEATURE_NB  *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
-  OPTION_MEM_FEATURE_NB  *LvDdr3; ///< Low voltage DDR3 dimm support
-  OPTION_MEM_FEATURE_NB  *OnDimmThermal; ///< On-Dimm thermal management
-  MEM_TECH_FEAT  *DramInit; ///< Choose the type of Dram init (hardware based or software based).
-  OPTION_MEM_FEATURE_NB  *ExcludeDIMM; ///< Exclude a dimm.
-  OPTION_MEM_FEATURE_NB  *InitEarlySampleSupport; ///< Initialize early sample support.
-  OPTION_MEM_FEATURE_NB  *InitCPG; ///< Continuous pattern generation.
-  OPTION_MEM_FEATURE_NB  *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
-} MEM_FEAT_BLOCK_NB;
-
-typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  );
-
-typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
-  IN MEM_MAIN_DATA_BLOCK *MMPtr
-  );
-
-typedef BOOLEAN MEM_NB_CONSTRUCTOR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
-  IN       UINT8 NodeID
-  );
-
-typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
-  IN OUT   MEM_TECH_BLOCK *TechPtr,
-  IN OUT   MEM_NB_BLOCK   *NBPtr
-  );
-
-typedef VOID MEM_INITIALIZER (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
- );
-
-typedef AGESA_STATUS MEM_PLATFORM_CFG (
-  IN struct _MEM_DATA_STRUCT *MemData,
-  IN UINT8 SocketID,
-  IN CH_DEF_STRUCT *CurrentChannel
-  );
-
-typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  );
-
-typedef VOID MEM_TECH_TRAINING_FEAT (
-  IN OUT   MEM_TECH_BLOCK *TechPtr,
-  IN       UINT8 Pass
-  );
-
-typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  );
-
-typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
-  IN struct _MEM_DATA_STRUCT *MemData,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  );
-
-typedef AGESA_STATUS MEM_FLOW_CFG (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemData
-  );
-
-#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION  0x01
-
-/**
- * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
- * that shared between all northbridge devices.
- */
-typedef struct _MEM_FEAT_BLOCK_MAIN {
-  UINT16              OptMemFeatVersion; ///< Version of main feature block.
-  OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
-  OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
-  OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
-  OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
-  OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
-  OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
-  OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
-  OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
-  OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
-  OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
-  OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
-} MEM_FEAT_BLOCK_MAIN;
-
-#define MEM_NB_SUPPORT_STRUCT_VERSION  0x01
-#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION  0x01
-#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION  0x01
-#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
-/**
- *  MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
- *  memory feature implementation functions.  It contains vectors for all of the
- *  features that are supported by the various Technology features supported by
- *  AGESA.
- */
-typedef struct _MEM_TECH_FEAT_BLOCK {
-  UINT16  OptMemTechFeatVersion; ///< Version of memory Tech feature block.
-  MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
-  MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
-  MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
-  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
-  MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
-  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
-  MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
-  MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
-  MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
-  MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
-  MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
-  MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
-} MEM_TECH_FEAT_BLOCK;
-
-/**
- *  MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
- *  memory feature implementation functions.  It contains vectors for all of the
- *  features that are supported by the various LRDIMM features supported by
- *  AGESA.
- */
-typedef struct _MEM_TECH_LRDIMM {
-  UINT16  OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
-  MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
-} MEM_TECH_LRDIMM;
-/**
- * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
- * options together in a list to provide a single access point for all code to use
- * and to ensure that everything corresponding to the same NB type is grouped together.
- *
- * The Technology Block pointers are not included in this structure because DRAM technology
- * needs to be decoupled from the northbridge type.
- *
- */
-typedef struct _MEM_NB_SUPPORT {
-  UINT16              MemNBSupportVersion; ///< Version of northbridge support.
-  MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
-  MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
-  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
-  MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
-  MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
-} MEM_NB_SUPPORT;
-
-/*
- *  MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
- *  memory non-training feature implementation functions.  It contains vectors for all of the
- *  features that are supported by the various Technology devices supported by
- *  AGESA.
- */
-
-/**
- * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
- * that shared between all northbridge devices.
- */
-typedef struct _MEM_FEAT_TRAIN_SEQ {
-  UINT16              OptMemTrainingSequenceListVersion; ///< Version of main feature block.
-  OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
-  OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
-  MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
-} MEM_FEAT_TRAIN_SEQ;
-
-/**
- * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
- * entries which are used by PSC engine
- */
-typedef struct _MEM_PSC_TABLE_BLOCK {
-  PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
-  PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
-  PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
-  PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
-  PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
-  PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
-  PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
-  PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
-  PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
-  PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
-  PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
-  PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
-} MEM_PSC_TABLE_BLOCK;
-
-typedef BOOLEAN MEM_PSC_FLOW (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
-  );
-
-/**
- * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
- * specific configuration.
- */
-typedef struct _MEM_PSC_FLOW_BLOCK {
-  MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
-  MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
-  MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
-  MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
-  MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
-  MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
-  MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
-  MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
-  MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
-  MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
-  MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
-} MEM_PSC_FLOW_BLOCK;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-/* Feature Default Return */
-BOOLEAN MemFDefRet (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN MemMDefRet (
-  IN MEM_MAIN_DATA_BLOCK *MMPtr
-  );
-/* Table Feature Default Return */
-UINT8 MemFTableDefRet (
-  IN OUT   MEM_TABLE_ALIAS **MTPtr
-  );
-/* S3 Feature Default Return */
-BOOLEAN MemFS3DefConstructorRet (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  );
-
-BOOLEAN
-MemProcessConditionalOverrides (
-  IN       PSO_TABLE *PlatformMemoryConfiguration,
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 PsoAction,
-  IN       UINT8 Dimm
-   );
-
-#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h
deleted file mode 100644
index 2f41757..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h
+++ /dev/null
@@ -1,4051 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37402 $   @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_INSTALL_H_
-#define _OPTION_MEMORY_INSTALL_H_
-
-/*-------------------------------------------------------------------------------
- *  This option file is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-/*----------------------------------------------------------------------------------
- * FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFDefRet (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  return FALSE;
-}
-
-BOOLEAN MemMDefRet (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return TRUE;
-}
-
-BOOLEAN MemMDefRetFalse (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN MemNIdentifyDimmConstructorRetDef (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return FALSE;
-}
-/*----------------------------------------------------------------------------------
- * TABLE FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-UINT8 MemFTableDefRet (
-  IN OUT   MEM_TABLE_ALIAS **MTPtr
-  )
-{
-  return 0;
-}
-/*----------------------------------------------------------------------------------
- * FEATURE S3 BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFS3DefConstructorRet (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return TRUE;
-}
-
-#if (OPTION_MEMCTLR_DR == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
-    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
-  #else
-    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      #if (OPTION_MEMCTLR_Ni == TRUE)
-        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
-      #else
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
-      #endif
-      #if (OPTION_MEMCTLR_DA == TRUE)
-        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
-      #else
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
-      #endif
-      #if (OPTION_MEMCTLR_PH == TRUE)
-        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
-      #else
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
-      #endif
-      #if (OPTION_MEMCTLR_RB == TRUE)
-        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
-      #else
-        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
-      #endif
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
-    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
-    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
-    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
-  #else
-    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
-    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
-    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_OR == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
-    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
-  #else
-    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_HY == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
-    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
-  #else
-    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_C32 == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
-    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
-  #else
-    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_LN == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
-    #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
-  #else
-    #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-#if (OPTION_MEMCTLR_ON == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
-    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
-  #else
-    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-/*----------------------------------------------------------------------------------
- * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
- *
- *----------------------------------------------------------------------------------
-*/
-#define MEM_NB_SUPPORT_DR
-#define MEM_NB_SUPPORT_RB
-#define MEM_NB_SUPPORT_DA
-#define MEM_NB_SUPPORT_Ni
-#define MEM_NB_SUPPORT_PH
-#define MEM_NB_SUPPORT_HY
-#define MEM_NB_SUPPORT_LN
-#define MEM_NB_SUPPORT_OR
-#define MEM_NB_SUPPORT_C32
-#define MEM_NB_SUPPORT_ON
-#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-  /*----------------------------------------------------------------------------------
-   * FLOW CONTROL FUNCTION
-   *
-   *  This section selects the function that controls the memory initialization sequence
-   *  based upon the number of processor families that the BIOS will support.
-   */
-
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    extern MEM_FLOW_CFG MemMFlowDr;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    extern MEM_FLOW_CFG MemMFlowDA;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    extern MEM_FLOW_CFG MemMFlowHy;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_OR == TRUE)
-    extern MEM_FLOW_CFG MemMFlowOr;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    extern MEM_FLOW_CFG MemMFlowLN;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    extern MEM_FLOW_CFG MemMFlowC32;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    extern MEM_FLOW_CFG MemMFlowON;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_Ni == TRUE)
-    extern MEM_FLOW_CFG MemMFlowDA;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    extern MEM_FLOW_CFG MemMFlowRb;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
-  #endif
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    extern MEM_FLOW_CFG MemMFlowPh;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
-  #endif
-
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
-    MEM_MAIN_FLOW_CONTROL_PTR_Dr
-    MEM_MAIN_FLOW_CONTROL_PTR_DA
-    MEM_MAIN_FLOW_CONTROL_PTR_RB
-    MEM_MAIN_FLOW_CONTROL_PTR_PH
-    MEM_MAIN_FLOW_CONTROL_PTR_Hy
-    MEM_MAIN_FLOW_CONTROL_PTR_OR
-    MEM_MAIN_FLOW_CONTROL_PTR_LN
-    MEM_MAIN_FLOW_CONTROL_PTR_C32
-    MEM_MAIN_FLOW_CONTROL_PTR_ON
-    MEM_MAIN_FLOW_CONTROL_PTR_Ni
-    NULL
-  };
-
-  #if (OPTION_ONLINE_SPARE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
-    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
-    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
-  #else
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
-    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
-  #endif
-
-  #if (OPTION_MEM_RESTORE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
-    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
-  #else
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
-  #endif
-
-  #if (OPTION_BANK_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
-    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
-  #else
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
-  #endif
-
-  #if (OPTION_NODE_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
-    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
-  #else
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
-  #endif
-
-  #if (OPTION_DCT_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
-  #else
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
-  #endif
-
-  #if (OPTION_ECC == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
-    #define MEM_MAIN_FEATURE_ECC  MemMEcc
-    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
-    extern OPTION_MEM_FEATURE_NB MemFInitECC;
-    #define MEM_FEATURE_CK_ECC   MemFCheckECC
-    #define MEM_FEATURE_ECC   MemFInitECC
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #else
-    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
-    #define MEM_FEATURE_CK_ECC   MemFDefRet
-    #define MEM_FEATURE_ECC   MemFDefRet
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #endif
-
-  #if (OPTION_EMP == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInitEMP;
-    #define MEM_FEATURE_EMP   MemFInitEMP
-  #else
-    #define MEM_FEATURE_EMP   MemFDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
-  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
-
-  #if (OPTION_DMI == TRUE)
-    #if (OPTION_DDR3 == TRUE)
-      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
-      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
-    #else
-      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
-      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
-    #endif
-  #else
-    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
-  #endif
-
-  #if (OPTION_DDR3 == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
-    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
-    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
-    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
-  #else
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
-    #define MEM_FEATURE_LVDDR3 MemFDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
-  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
-
-  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
-  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
-
-  #if (OPTION_PARALLEL_TRAINING == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
-  #else
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-  #endif
-
-  #if (OPTION_DIMM_EXCLUDE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
-    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
-  #else
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
-  #endif
-
-  /*----------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
-   *
-   *----------------------------------------------------------------------------------
-  */
-  #if OPTION_DDR2 == TRUE
-    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
-    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
-    #if (OPTION_HW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitHw;
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
-    #else
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
-    #endif
-    #if (OPTION_SW_DRAM_INIT == TRUE)
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #else
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #endif
-  #else
-    #define MEM_TECH_CONSTRUCTOR_DDR2
-  #endif
-  #if OPTION_DDR3 == TRUE
-    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
-    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
-    #if (OPTION_HW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitHw;
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
-    #else
-      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
-    #endif
-    #if (OPTION_SW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitSw3;
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
-    #else
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #endif
-  #else
-    #define MEM_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * FEATURE BLOCKS
-   *
-   *  This section instantiates a feature block structure for each memory controller installed
-   *  by the platform solution install file.
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEERHOUND FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #undef MEM_TECH_FEATURE_CPG
-    #define MEM_TECH_FEATURE_CPG    MemFDefRet
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
-      MEM_FEATURE_NODE_INTERLEAVE,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MemFDefRet,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MemFDefRet,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MemFDefRet,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_DR
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
-    extern MEM_INITIALIZER MemNInitDefaultsDR;
-
-
-    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
-  #endif // OPTION_MEMCTRL_DR
-
-  /*---------------------------------------------------------------------------------------------------
-   * DASHOUND FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #undef MEM_TECH_FEATURE_CPG
-    #define MEM_TECH_FEATURE_CPG    MemFDefRet
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    #if (OPTION_MEMCTLR_Ni == TRUE)
-      MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
-        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-        MemFDefRet,
-        MEM_FEATURE_BANK_INTERLEAVE,
-        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-        MemFDefRet,
-        MemFDefRet,
-        MEM_FEATURE_CHANNEL_INTERLEAVE,
-        MEM_FEATURE_REGION_INTERLEAVE,
-        MEM_FEATURE_CK_ECC,
-        MEM_FEATURE_ECC,
-        MEM_FEATURE_TRAINING,
-        MEM_FEATURE_LVDDR3,
-        MemFDefRet,
-        MEM_TECH_FEATURE_DRAMINIT,
-        MEM_FEATURE_DIMM_EXCLUDE,
-        MemFDefRet,
-        MEM_TECH_FEATURE_CPG,
-        MEM_TECH_FEATURE_HWRXEN
-      };
-
-      #undef MEM_NB_SUPPORT_Ni
-      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
-      extern MEM_INITIALIZER MemNInitDefaultsNi;
-
-      #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
-    #endif
-
-    #if (OPTION_MEMCTLR_PH == TRUE)
-      MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
-        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-        MemFDefRet,
-        MEM_FEATURE_BANK_INTERLEAVE,
-        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-        MemFDefRet,
-        MemFDefRet,
-        MEM_FEATURE_CHANNEL_INTERLEAVE,
-        MEM_FEATURE_REGION_INTERLEAVE,
-        MEM_FEATURE_CK_ECC,
-        MEM_FEATURE_ECC,
-        MEM_FEATURE_TRAINING,
-        MEM_FEATURE_LVDDR3,
-        MemFDefRet,
-        MEM_TECH_FEATURE_DRAMINIT,
-        MEM_FEATURE_DIMM_EXCLUDE,
-        MemFDefRet,
-        MEM_TECH_FEATURE_CPG,
-        MEM_TECH_FEATURE_HWRXEN
-      };
-
-      #undef MEM_NB_SUPPORT_PH
-      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
-      extern MEM_INITIALIZER MemNInitDefaultsPh;
-
-      #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
-    #endif
-
-    #if (OPTION_MEMCTLR_RB == TRUE)
-      MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
-        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-        MemFDefRet,
-        MEM_FEATURE_BANK_INTERLEAVE,
-        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-        MemFDefRet,
-        MemFDefRet,
-        MEM_FEATURE_CHANNEL_INTERLEAVE,
-        MEM_FEATURE_REGION_INTERLEAVE,
-        MEM_FEATURE_CK_ECC,
-        MEM_FEATURE_ECC,
-        MEM_FEATURE_TRAINING,
-        MEM_FEATURE_LVDDR3,
-        MemFDefRet,
-        MEM_TECH_FEATURE_DRAMINIT,
-        MEM_FEATURE_DIMM_EXCLUDE,
-        MemFDefRet,
-        MEM_TECH_FEATURE_CPG,
-        MEM_TECH_FEATURE_HWRXEN
-      };
-
-      #undef MEM_NB_SUPPORT_RB
-      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
-      extern MEM_INITIALIZER MemNInitDefaultsRb;
-
-      #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
-    #endif
-
-    #if (OPTION_MEMCTLR_DA == TRUE)
-      MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
-        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-        MemFDefRet,
-        MEM_FEATURE_BANK_INTERLEAVE,
-        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-        MemFDefRet,
-        MemFDefRet,
-        MEM_FEATURE_CHANNEL_INTERLEAVE,
-        MEM_FEATURE_REGION_INTERLEAVE,
-        MEM_FEATURE_CK_ECC,
-        MEM_FEATURE_ECC,
-        MEM_FEATURE_TRAINING,
-        MEM_FEATURE_LVDDR3,
-        MemFDefRet,
-        MEM_TECH_FEATURE_DRAMINIT,
-        MEM_FEATURE_DIMM_EXCLUDE,
-        MemFDefRet,
-        MEM_TECH_FEATURE_CPG,
-        MEM_TECH_FEATURE_HWRXEN
-      };
-
-      #undef MEM_NB_SUPPORT_DA
-      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
-      extern MEM_INITIALIZER MemNInitDefaultsDA;
-
-      #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
-    #endif
-  #endif // OPTION_MEMCTRL_DA
-
-  /*---------------------------------------------------------------------------------------------------
-   * HYDRA FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #undef MEM_TECH_FEATURE_CPG
-    #define MEM_TECH_FEATURE_CPG    MemFDefRet
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
-      MEM_FEATURE_NODE_INTERLEAVE,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MemFDefRet,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MemFDefRet,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_HY
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
-    extern MEM_INITIALIZER MemNInitDefaultsHY;
-    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
-  #endif // OPTION_MEMCTRL_HY
-  /*---------------------------------------------------------------------------------------------------
-   * LLANO FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportLN
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockLn = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MemFDefRet,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MEM_FEATURE_REGION_INTERLEAVE,
-      MEM_FEATURE_CK_ECC,
-      MemFDefRet,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-    #undef MEM_NB_SUPPORT_LN
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
-    extern MEM_INITIALIZER MemNInitDefaultsLN;
-    #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
-
-  #endif // OPTION_MEMCTRL_LN
-
-  /*---------------------------------------------------------------------------------------------------
-   * ONTARIO FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportON
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockOn = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MemFDefRet,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_ON
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
-    extern MEM_INITIALIZER MemNInitDefaultsON;
-    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
-
-  #endif // OPTION_MEMCTRL_ON
-
-  /*---------------------------------------------------------------------------------------------------
-   * OROCHI FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_OR == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_MAIN_FEATURE_LVDDR3
-      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
-      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
-      MEM_FEATURE_NODE_INTERLEAVE,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MemFDefRet,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_OR
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
-    extern MEM_INITIALIZER MemNInitDefaultsOR;
-    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
-  #endif // OPTION_MEMCTRL_OR
-
-  /*---------------------------------------------------------------------------------------------------
-   * C32 FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #undef MEM_TECH_FEATURE_CPG
-    #define MEM_TECH_FEATURE_CPG    MemFDefRet
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
-      MEM_FEATURE_NODE_INTERLEAVE,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MemFDefRet,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MemFDefRet,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_C32
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
-    extern MEM_INITIALIZER MemNInitDefaultsC32;
-    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
-  #endif // OPTION_MEMCTRL_C32
-
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
-    MEM_MAIN_FEATURE_TRAINING,
-    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
-    MEM_MAIN_FEATURE_ONLINE_SPARE,
-    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
-    MEM_MAIN_FEATURE_ECC,
-    MEM_MAIN_FEATURE_MEM_CLEAR,
-    MEM_MAIN_FEATURE_MEM_DMI,
-    MEM_MAIN_FEATURE_LVDDR3,
-    MEM_MAIN_FEATURE_UMAALLOC,
-    MEM_MAIN_FEATURE_MEM_SAVE,
-    MEM_MAIN_FEATURE_MEM_RESTORE
-  };
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * Technology Training SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
-  #if OPTION_MEMCTLR_DR
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
-    #if OPTION_DDR2
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
-      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
-    #else
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-  #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
-    #if OPTION_DDR2
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
-      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
-      #if (OPTION_MEMCTLR_DA)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-      #if (OPTION_MEMCTLR_PH)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-      #if (OPTION_MEMCTLR_RB)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-
-      #if (OPTION_MEMCTLR_Ni)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-    #else
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #if (OPTION_MEMCTLR_DA)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-      #if (OPTION_MEMCTLR_PH)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-      #if (OPTION_MEMCTLR_RB)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-      #if (OPTION_MEMCTLR_Ni)
-        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
-      #else
-        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #endif
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-  #if OPTION_MEMCTLR_HY
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
-    #if OPTION_DDR2
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
-      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
-    #else
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-  #if OPTION_MEMCTLR_C32
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
-    #if OPTION_DDR2
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR2,
-        TECH_TRAIN_SW_WL_DDR2,
-        TECH_TRAIN_HW_WL_P1_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_HW_WL_P2_DDR2,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
-        TECH_TRAIN_EXIT_HW_TRN_DDR2,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
-        TECH_TRAIN_MAX_RD_LAT_DDR2
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
-      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
-    #else
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-
-  #if OPTION_MEMCTLR_LN
-    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN;
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3LN = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-
-  #if OPTION_MEMCTLR_OR
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
-    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-
-  #if OPTION_MEMCTLR_ON
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
-    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3ON = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
-  };
-
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
-    NB_TRAIN_FLOW_DDR2,
-    NB_TRAIN_FLOW_DDR3,
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
-    MEM_TECH_CONSTRUCTOR_DDR2
-    MEM_TECH_CONSTRUCTOR_DDR3
-    NULL
-  };
-   /*---------------------------------------------------------------------------------------------------
-   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if  OPTION_MEMCTLR_HY
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
-      #else
-        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
-      #else
-        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
-      #else
-        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
-    PLAT_SP_HY_FF_UDIMM2
-    PLAT_SP_HY_FF_RDIMM2
-    PLAT_SP_HY_FF_SDIMM2
-    PLAT_SP_HY_FF_UDIMM3
-    PLAT_SP_HY_FF_RDIMM3
-    PLAT_SP_HY_FF_SDIMM3
-  };
-
-  #if OPTION_MEMCTLR_DR
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
-        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
-      #else
-        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
-      #else
-        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
-        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
-      #else
-        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
-      #else
-        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
-      #else
-        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
-    PLAT_SP_DR_FF_UDIMM2
-    PLAT_SP_DR_FF_RDIMM2
-    PLAT_SP_DR_FF_SDIMM2
-    PLAT_SP_DR_FF_UDIMM3
-    PLAT_SP_DR_FF_RDIMM3
-    PLAT_SP_DR_FF_SDIMM3
-  };
-
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
-      #else
-        #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
-      #else
-        #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
-      #else
-        #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
-    PLAT_SP_DA_FF_UDIMM2
-    PLAT_SP_DA_FF_RDIMM2
-    PLAT_SP_DA_FF_SDIMM2
-    PLAT_SP_DA_FF_UDIMM3
-    PLAT_SP_DA_FF_RDIMM3
-    PLAT_SP_DA_FF_SDIMM3
-  };
-
-  #if (OPTION_MEMCTLR_Ni == TRUE)
-    #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsSNi3,
-    #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUNi3,
-  #else
-    #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
-    PLAT_SP_NI_FF_UDIMM2
-    PLAT_SP_NI_FF_RDIMM2
-    PLAT_SP_NI_FF_SDIMM2
-    PLAT_SP_NI_FF_UDIMM3
-    PLAT_SP_NI_FF_RDIMM3
-    PLAT_SP_NI_FF_SDIMM3
-  };
-
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsSPh3,
-    #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUPh3,
-  #else
-    #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
-    PLAT_SP_PH_FF_UDIMM2
-    PLAT_SP_PH_FF_RDIMM2
-    PLAT_SP_PH_FF_SDIMM2
-    PLAT_SP_PH_FF_UDIMM3
-    PLAT_SP_PH_FF_RDIMM3
-    PLAT_SP_PH_FF_SDIMM3
-  };
-
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsSRb3,
-    #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsURb3,
-  #else
-    #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
-    PLAT_SP_RB_FF_UDIMM2
-    PLAT_SP_RB_FF_RDIMM2
-    PLAT_SP_RB_FF_SDIMM2
-    PLAT_SP_RB_FF_UDIMM3
-    PLAT_SP_RB_FF_RDIMM3
-    PLAT_SP_RB_FF_SDIMM3
-  };
-
-  #if OPTION_MEMCTLR_LN
-    #if OPTION_UDIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsULN3,
-      #else
-        #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsSLN3,
-      #else
-        #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
-    PLAT_SP_LN_FF_SDIMM3
-    PLAT_SP_LN_FF_UDIMM3
-    NULL
-  };
-
-  #if  OPTION_MEMCTLR_C32
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
-      #else
-        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
-      #else
-        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
-      #endif
-      #if OPTION_DDR3
-        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
-      #else
-        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
-      #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
-    #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
-    PLAT_SP_C32_FF_UDIMM2
-    PLAT_SP_C32_FF_RDIMM2
-    PLAT_SP_C32_FF_SDIMM2
-    PLAT_SP_C32_FF_UDIMM3
-    PLAT_SP_C32_FF_RDIMM3
-    PLAT_SP_C32_FF_SDIMM3
-  };
-
-  #if OPTION_MEMCTLR_ON
-    #if OPTION_UDIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUON3,
-      #else
-        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsSON3,
-      #else
-        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = {
-    PLAT_SP_ON_FF_SDIMM3
-    PLAT_SP_ON_FF_UDIMM3
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * PLATFORM-SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  #if OPTION_MEMCTLR_DR
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
-      #else
-        #define PSC_DR_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
-      #else
-        #define PSC_DR_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
-      #else
-        #define PSC_DR_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
-      #else
-        #define PSC_DR_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
-      #else
-        #define PSC_DR_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
-      #else
-        #define PSC_DR_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
-    #if OPTION_MEMCTLR_Ni
-      #define PSC_NI_UDIMM_DDR2
-      #define PSC_NI_UDIMM_DDR3     MemAGetPsCfgUNi3,
-      #define PSC_NI_RDIMM_DDR2
-      #define PSC_NI_RDIMM_DDR3
-      #define PSC_NI_SODIMM_DDR2
-      #define PSC_NI_SODIMM_DDR3    MemAGetPsCfgSNi3,
-    #endif
-    #if OPTION_MEMCTLR_PH
-      #define PSC_PH_UDIMM_DDR2
-      #define PSC_PH_UDIMM_DDR3     MemAGetPsCfgUPh3,
-      #define PSC_PH_RDIMM_DDR2
-      #define PSC_PH_RDIMM_DDR3
-      #define PSC_PH_SODIMM_DDR2
-      #define PSC_PH_SODIMM_DDR3    MemAGetPsCfgSPh3,
-    #endif
-    #if OPTION_MEMCTLR_RB
-      #define PSC_RB_UDIMM_DDR2
-      #define PSC_RB_UDIMM_DDR3     MemAGetPsCfgURb3,
-      #define PSC_RB_RDIMM_DDR2
-      #define PSC_RB_RDIMM_DDR3
-      #define PSC_RB_SODIMM_DDR2
-      #define PSC_RB_SODIMM_DDR3    MemAGetPsCfgSRb3,
-    #endif
-    #if OPTION_MEMCTLR_DA
-      #if OPTION_UDIMMS
-        #if OPTION_DDR2
-          #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
-        #else
-          #define PSC_DA_UDIMM_DDR2
-        #endif
-        #if OPTION_DDR3
-          #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
-        #else
-          #define PSC_DA_UDIMM_DDR3
-        #endif
-      #endif
-      #if OPTION_RDIMMS
-        #if OPTION_DDR2
-          #define PSC_DA_RDIMM_DDR2
-        #else
-          #define PSC_DA_RDIMM_DDR2
-        #endif
-        #if OPTION_DDR3
-          #define PSC_DA_RDIMM_DDR3
-        #else
-          #define PSC_DA_RDIMM_DDR3
-        #endif
-      #endif
-      #if OPTION_SODIMMS
-        #if OPTION_DDR2
-          #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
-        #else
-          #define PSC_DA_SODIMM_DDR2
-        #endif
-        #if OPTION_DDR3
-          #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
-        #else
-          #define PSC_DA_SODIMM_DDR3
-        #endif
-      #endif
-    #endif
-  #endif
-
-  #if OPTION_MEMCTLR_HY
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
-      #else
-        #define PSC_HY_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
-      #else
-        #define PSC_HY_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_HY_RDIMM_DDR2
-      #else
-        #define PSC_HY_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
-      #else
-        #define PSC_HY_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
-      #else
-        #define PSC_HY_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
-      #else
-        #define PSC_HY_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  #if OPTION_MEMCTLR_C32
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
-      #else
-        #define PSC_C32_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
-      #else
-        #define PSC_C32_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_C32_RDIMM_DDR2
-      #else
-        #define PSC_C32_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
-      #else
-        #define PSC_C32_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
-      #else
-        #define PSC_C32_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
-      #else
-        #define PSC_C32_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  #if OPTION_MEMCTLR_LN
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_LN_UDIMM_DDR2     //MemAGetPsCfgULN2,
-      #else
-        #define PSC_LN_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_LN_UDIMM_DDR3    MemAGetPsCfgULN3,
-      #else
-        #define PSC_LN_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_LN_RDIMM_DDR2
-      #else
-        #define PSC_LN_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_LN_RDIMM_DDR3    //MemAGetPsCfgRLN3,
-      #else
-        #define PSC_LN_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_LN_SODIMM_DDR2    //MemAGetPsCfgSLN2,
-      #else
-        #define PSC_LN_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_LN_SODIMM_DDR3   MemAGetPsCfgSLN3,
-      #else
-        #define PSC_LN_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  #if OPTION_MEMCTLR_OR
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
-      #else
-        #define PSC_OR_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_OR_UDIMM_DDR3     //MemAGetPsCfgUOr3,
-      #else
-        #define PSC_OR_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_OR_RDIMM_DDR2
-      #else
-        #define PSC_OR_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_OR_RDIMM_DDR3     //MemAGetPsCfgROr3,
-      #else
-        #define PSC_OR_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
-      #else
-        #define PSC_OR_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
-      #else
-        #define PSC_OR_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  #if OPTION_MEMCTLR_ON
-    #if OPTION_UDIMMS
-      #if OPTION_DDR2
-        #define PSC_ON_UDIMM_DDR2     //MemAGetPsCfgUON2,
-      #else
-        #define PSC_ON_UDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_ON_UDIMM_DDR3    MemAGetPsCfgUON3,
-      #else
-        #define PSC_ON_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR2
-        #define PSC_ON_RDIMM_DDR2
-      #else
-        #define PSC_ON_RDIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_ON_RDIMM_DDR3    //MemAGetPsCfgRON3,
-      #else
-        #define PSC_ON_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR2
-        #define PSC_ON_SODIMM_DDR2    //MemAGetPsCfgSON2,
-      #else
-        #define PSC_ON_SODIMM_DDR2
-      #endif
-      #if OPTION_DDR3
-        #define PSC_ON_SODIMM_DDR3   MemAGetPsCfgSON3,
-      #else
-        #define PSC_ON_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-
-  #ifndef PSC_DR_UDIMM_DDR2
-    #define PSC_DR_UDIMM_DDR2
-  #endif
-  #ifndef PSC_DR_RDIMM_DDR2
-    #define PSC_DR_RDIMM_DDR2
-  #endif
-  #ifndef PSC_DR_SODIMM_DDR2
-    #define PSC_DR_SODIMM_DDR2
-  #endif
-  #ifndef PSC_DR_UDIMM_DDR3
-    #define PSC_DR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_DR_RDIMM_DDR3
-    #define PSC_DR_RDIMM_DDR3
-  #endif
-  #ifndef PSC_DR_SODIMM_DDR3
-    #define PSC_DR_SODIMM_DDR3
-  #endif
-  #ifndef PSC_RB_UDIMM_DDR2
-    #define PSC_RB_UDIMM_DDR2
-  #endif
-  #ifndef PSC_RB_RDIMM_DDR2
-    #define PSC_RB_RDIMM_DDR2
-  #endif
-  #ifndef PSC_RB_SODIMM_DDR2
-    #define PSC_RB_SODIMM_DDR2
-  #endif
-  #ifndef PSC_RB_UDIMM_DDR3
-    #define PSC_RB_UDIMM_DDR3
-  #endif
-  #ifndef PSC_RB_RDIMM_DDR3
-    #define PSC_RB_RDIMM_DDR3
-  #endif
-  #ifndef PSC_RB_SODIMM_DDR3
-    #define PSC_RB_SODIMM_DDR3
-  #endif
-  #ifndef PSC_DA_UDIMM_DDR2
-    #define PSC_DA_UDIMM_DDR2
-  #endif
-  #ifndef PSC_DA_RDIMM_DDR2
-    #define PSC_DA_RDIMM_DDR2
-  #endif
-  #ifndef PSC_DA_SODIMM_DDR2
-    #define PSC_DA_SODIMM_DDR2
-  #endif
-  #ifndef PSC_DA_UDIMM_DDR3
-    #define PSC_DA_UDIMM_DDR3
-  #endif
-  #ifndef PSC_DA_RDIMM_DDR3
-    #define PSC_DA_RDIMM_DDR3
-  #endif
-  #ifndef PSC_DA_SODIMM_DDR3
-    #define PSC_DA_SODIMM_DDR3
-  #endif
-  #ifndef PSC_NI_UDIMM_DDR2
-    #define PSC_NI_UDIMM_DDR2
-  #endif
-  #ifndef PSC_NI_RDIMM_DDR2
-    #define PSC_NI_RDIMM_DDR2
-  #endif
-  #ifndef PSC_NI_SODIMM_DDR2
-    #define PSC_NI_SODIMM_DDR2
-  #endif
-  #ifndef PSC_NI_UDIMM_DDR3
-    #define PSC_NI_UDIMM_DDR3
-  #endif
-  #ifndef PSC_NI_RDIMM_DDR3
-    #define PSC_NI_RDIMM_DDR3
-  #endif
-  #ifndef PSC_NI_SODIMM_DDR3
-    #define PSC_NI_SODIMM_DDR3
-  #endif
-  #ifndef PSC_PH_UDIMM_DDR2
-    #define PSC_PH_UDIMM_DDR2
-  #endif
-  #ifndef PSC_PH_RDIMM_DDR2
-    #define PSC_PH_RDIMM_DDR2
-  #endif
-  #ifndef PSC_PH_SODIMM_DDR2
-    #define PSC_PH_SODIMM_DDR2
-  #endif
-  #ifndef PSC_PH_UDIMM_DDR3
-    #define PSC_PH_UDIMM_DDR3
-  #endif
-  #ifndef PSC_PH_RDIMM_DDR3
-    #define PSC_PH_RDIMM_DDR3
-  #endif
-  #ifndef PSC_PH_SODIMM_DDR3
-    #define PSC_PH_SODIMM_DDR3
-  #endif
-  #ifndef PSC_HY_UDIMM_DDR2
-    #define PSC_HY_UDIMM_DDR2
-  #endif
-  #ifndef PSC_HY_RDIMM_DDR2
-    #define PSC_HY_RDIMM_DDR2
-  #endif
-  #ifndef PSC_HY_SODIMM_DDR2
-    #define PSC_HY_SODIMM_DDR2
-  #endif
-  #ifndef PSC_HY_UDIMM_DDR3
-    #define PSC_HY_UDIMM_DDR3
-  #endif
-  #ifndef PSC_HY_RDIMM_DDR3
-    #define PSC_HY_RDIMM_DDR3
-  #endif
-  #ifndef PSC_HY_SODIMM_DDR3
-    #define PSC_HY_SODIMM_DDR3
-  #endif
-  #ifndef PSC_LN_UDIMM_DDR2
-    #define PSC_LN_UDIMM_DDR2
-  #endif
-  #ifndef PSC_LN_RDIMM_DDR2
-    #define PSC_LN_RDIMM_DDR2
-  #endif
-  #ifndef PSC_LN_SODIMM_DDR2
-    #define PSC_LN_SODIMM_DDR2
-  #endif
-  #ifndef PSC_LN_UDIMM_DDR3
-    #define PSC_LN_UDIMM_DDR3
-  #endif
-  #ifndef PSC_LN_RDIMM_DDR3
-    #define PSC_LN_RDIMM_DDR3
-  #endif
-  #ifndef PSC_LN_SODIMM_DDR3
-    #define PSC_LN_SODIMM_DDR3
-  #endif
-  #ifndef PSC_OR_UDIMM_DDR2
-    #define PSC_OR_UDIMM_DDR2
-  #endif
-  #ifndef PSC_OR_RDIMM_DDR2
-    #define PSC_OR_RDIMM_DDR2
-  #endif
-  #ifndef PSC_OR_SODIMM_DDR2
-    #define PSC_OR_SODIMM_DDR2
-  #endif
-  #ifndef PSC_OR_UDIMM_DDR3
-    #define PSC_OR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_OR_RDIMM_DDR3
-    #define PSC_OR_RDIMM_DDR3
-  #endif
-  #ifndef PSC_OR_SODIMM_DDR3
-    #define PSC_OR_SODIMM_DDR3
-  #endif
-  #ifndef PSC_C32_UDIMM_DDR3
-    #define PSC_C32_UDIMM_DDR3
-  #endif
-  #ifndef PSC_C32_RDIMM_DDR3
-    #define PSC_C32_RDIMM_DDR3
-  #endif
-  #ifndef PSC_ON_UDIMM_DDR2
-    #define PSC_ON_UDIMM_DDR2
-  #endif
-  #ifndef PSC_ON_RDIMM_DDR2
-    #define PSC_ON_RDIMM_DDR2
-  #endif
-  #ifndef PSC_ON_SODIMM_DDR2
-    #define PSC_ON_SODIMM_DDR2
-  #endif
-  #ifndef PSC_ON_UDIMM_DDR3
-    #define PSC_ON_UDIMM_DDR3
-  #endif
-  #ifndef PSC_ON_RDIMM_DDR3
-    #define PSC_ON_RDIMM_DDR3
-  #endif
-  #ifndef PSC_ON_SODIMM_DDR3
-    #define PSC_ON_SODIMM_DDR3
-  #endif
-
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
-    PSC_DR_UDIMM_DDR2
-    PSC_DR_RDIMM_DDR2
-    PSC_DR_SODIMM_DDR2
-    PSC_DR_UDIMM_DDR3
-    PSC_DR_RDIMM_DDR3
-    PSC_DR_SODIMM_DDR3
-    PSC_RB_UDIMM_DDR3
-    PSC_RB_SODIMM_DDR3
-    PSC_DA_SODIMM_DDR2
-    PSC_DA_UDIMM_DDR3
-    PSC_DA_SODIMM_DDR3
-    PSC_NI_UDIMM_DDR3
-    PSC_NI_SODIMM_DDR3
-    PSC_PH_UDIMM_DDR3
-    PSC_PH_SODIMM_DDR3
-    PSC_HY_UDIMM_DDR3
-    PSC_HY_RDIMM_DDR3
-    PSC_HY_SODIMM_DDR3
-    PSC_LN_UDIMM_DDR3
-    PSC_LN_RDIMM_DDR3
-    PSC_LN_SODIMM_DDR3
-    PSC_OR_UDIMM_DDR3
-    PSC_OR_RDIMM_DDR3
-    PSC_OR_SODIMM_DDR3
-    PSC_C32_UDIMM_DDR3
-    PSC_C32_RDIMM_DDR3
-    PSC_ON_UDIMM_DDR3
-    PSC_ON_RDIMM_DDR3
-    PSC_ON_SODIMM_DDR3
-    NULL
-  };
-  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
-  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
-    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
-  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_FLOW_BLOCK_END NULL
-  #define PSC_TBL_END NULL
-  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
-  #if OPTION_MEMCTLR_OR
-    #if OPTION_UDIMMS
-      #if OPTION_AM3_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3  &MaxFreqTblEntUAM3,
-        extern PSC_TBL_ENTRY DramTermTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &DramTermTblEntUAM3,
-        extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &OdtPat1DTblEntUAM3,
-        extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3  &OdtPat2DTblEntUAM3,
-        extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &OdtPat3DTblEntUAM3,
-        extern PSC_TBL_ENTRY SAOTblEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_SAO_AM3  &SAOTblEntUAM3,
-        extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
-        #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
-      #endif
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32  &MaxFreqTblEntUC32,
-        extern PSC_TBL_ENTRY DramTermTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32  &DramTermTblEntUC32,
-        extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntUC32,
-        extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntUC32,
-        extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntUC32,
-        extern PSC_TBL_ENTRY SAOTblEntUC32;
-        #define PSC_TBL_OR_UDIMM3_SAO_C32  &SAOTblEntUC32,
-        extern PSC_TBL_ENTRY ClkDisMapEntUC32;
-        #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
-        extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
-        #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
-      #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34  &MaxFreqTblEntUG34,
-        extern PSC_TBL_ENTRY DramTermTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34  &DramTermTblEntUG34,
-        extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntUG34,
-        extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntUG34,
-        extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntUG34,
-        extern PSC_TBL_ENTRY SAOTblEntUG34;
-        #define PSC_TBL_OR_UDIMM3_SAO_G34  &SAOTblEntUG34,
-        extern PSC_TBL_ENTRY ClkDisMapEntUG34;
-        #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32  &MaxFreqTblEntRC32,
-        extern PSC_TBL_ENTRY DramTermTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32  &DramTermTblEntRC32,
-        extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntRC32,
-        extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntRC32,
-        extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntRC32,
-        extern PSC_TBL_ENTRY SAOTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_SAO_C32  &SAOTblEntRC32,
-        extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_RC2IBT_C32  &RC2IBTTblEntRC32,
-        extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
-        #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32  &RC10OpSpdTblEntRC32,
-        extern PSC_TBL_ENTRY ClkDisMapEntRC32;
-        #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
-      #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34  &MaxFreqTblEntRG34,
-        extern PSC_TBL_ENTRY DramTermTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34  &DramTermTblEntRG34,
-        extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntRG34,
-        extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntRG34,
-        extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntRG34,
-        extern PSC_TBL_ENTRY SAOTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_SAO_G34  &SAOTblEntRG34,
-        extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_RC2IBT_G34  &RC2IBTTblEntRG34,
-        extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
-        #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34  &RC10OpSpdTblEntRG34,
-        extern PSC_TBL_ENTRY ClkDisMapEntRG34;
-        #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
-      #endif
-    #endif
-    //#if OPTION_SODIMMS
-    //#endif
-    //#if OPTION_LRDIMMS
-    //  #if OPTION_C32_SOCKET_SUPPORT
-    //    extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32  &MaxFreqTblEntLRC32,
-    //    extern PSC_TBL_ENTRY DramTermTblEntLRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32  &DramTermTblEntLRC32,
-    //    extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntLRC32,
-    //    extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntLRC32,
-    //    extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntLRC32,
-    //    extern PSC_TBL_ENTRY SAOTblEntRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_SAO_C32  &SAOTblEntLRC32,
-    //    extern PSC_TBL_ENTRY IBTTblEntLRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_IBT_C32  &IBTTblEntLRC32,
-    //    extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
-    //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
-    //  #endif
-    //  #if OPTION_G34_SOCKET_SUPPORT
-    //    extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34  &MaxFreqTblEntLRG34,
-    //    extern PSC_TBL_ENTRY DramTermTblEntLRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34  &DramTermTblEntLRG34,
-    //    extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntLRG34,
-    //    extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntLRG34,
-    //    extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntLRG34,
-    //    extern PSC_TBL_ENTRY SAOTblEntRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_SAO_G34  &SAOTblEntLRG34,
-    //    extern PSC_TBL_ENTRY IBTTblEntLRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_IBT_G34  &IBTTblEntLRG34,
-    //    extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
-    //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
-    //  #endif
-    //#endif
-    extern PSC_TBL_ENTRY MR0WrTblEntry;
-    #define PSC_TBL_OR_MR0_WR  &MR0WrTblEntry,
-    extern PSC_TBL_ENTRY MR0CLTblEntry;
-    #define PSC_TBL_OR_MR0_CL  &MR0CLTblEntry,
-    extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
-    #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
-    extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
-    #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
-    extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
-    #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
-    extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
-    #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
-    extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
-    #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
-    extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
-    #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
-    extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
-    #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
-
-    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
-      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
-      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
-      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
-      #define PSC_TBL_OR_UDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
-      #define PSC_TBL_OR_UDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
-      #define PSC_TBL_OR_UDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
-      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
-      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
-      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
-      #define PSC_TBL_OR_RDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
-      #define PSC_TBL_OR_RDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
-      #define PSC_TBL_OR_RDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
-      #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
-      #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
-      #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
-      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
-      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
-      #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
-      #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
-      #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
-      #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
-      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
-      #define PSC_TBL_OR_LRDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
-      #define PSC_TBL_OR_LRDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
-      #define PSC_TBL_OR_LRDIMM3_IBT_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
-      #define PSC_TBL_OR_LRDIMM3_IBT_G34
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
-      #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
-      #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
-      #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
-    #endif
-    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
-      #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
-      #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
-    #endif
-    #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
-      #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
-      #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
-    #endif
-    #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
-      #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
-    #endif
-
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
-      PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
-      PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
-      PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
-      PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
-      PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
-      PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
-      PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
-      PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
-      PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
-      PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
-      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
-      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
-      PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
-      PSC_TBL_OR_UDIMM3_SAO_AM3
-      PSC_TBL_OR_UDIMM3_SAO_C32
-      PSC_TBL_OR_UDIMM3_SAO_G34
-      PSC_TBL_OR_RDIMM3_SAO_AM3
-      PSC_TBL_OR_RDIMM3_SAO_C32
-      PSC_TBL_OR_RDIMM3_SAO_G34
-      PSC_TBL_OR_LRDIMM3_SAO_C32
-      PSC_TBL_OR_LRDIMM3_SAO_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
-      PSC_TBL_OR_MR0_WR
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
-      PSC_TBL_OR_MR0_CL
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
-      PSC_TBL_OR_RDIMM3_RC2IBT_AM3
-      PSC_TBL_OR_RDIMM3_RC2IBT_C32
-      PSC_TBL_OR_RDIMM3_RC2IBT_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
-      PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-      PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
-      PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
-      PSC_TBL_OR_LRDIMM3_IBT_C32
-      PSC_TBL_OR_LRDIMM3_IBT_G34
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
-      PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
-      PSC_TBL_OR_UDIMM3_CLK_DIS_C32
-      PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
-      PSC_TBL_OR_UDIMM3_CLK_DIS_G34
-      PSC_TBL_OR_RDIMM3_CLK_DIS_C32
-      PSC_TBL_OR_RDIMM3_CLK_DIS_G34
-      PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
-      PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
-      PSC_TBL_OR_CKE_TRI
-      PSC_TBL_OR_ODT_TRI_3D
-      PSC_TBL_OR_ODT_TRI
-      PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
-      PSC_TBL_OR_LRDIMM3_ODT_TRI
-      PSC_TBL_OR_UDIMM3_CS_TRI
-      PSC_TBL_OR_CS_TRI
-      PSC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
-      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
-      (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
-      NULL,
-      NULL,
-      (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR
-    };
-
-    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
-    #define PSC_FLOW_OR_MAX_FREQ   MemPGetMaxFreqSupported
-    extern MEM_PSC_FLOW MemPGetRttNomWr;
-    #define PSC_FLOW_OR_DRAM_TERM   MemPGetRttNomWr
-    extern MEM_PSC_FLOW MemPGetODTPattern;
-    #define PSC_FLOW_OR_ODT_PATTERN   MemPGetODTPattern
-    extern MEM_PSC_FLOW MemPGetSAO;
-    #define PSC_FLOW_OR_SAO   MemPGetSAO
-    extern MEM_PSC_FLOW MemPGetMR0WrCL;
-    #define PSC_FLOW_OR_MR0_WRCL   MemPGetMR0WrCL
-    #if OPTION_RDIMMS
-      extern MEM_PSC_FLOW MemPGetRC2IBT;
-      #define PSC_FLOW_OR_RC2_IBT    MemPGetRC2IBT
-      extern MEM_PSC_FLOW MemPGetRC10OpSpd;
-      #define PSC_FLOW_OR_RC10_OPSPD   MemPGetRC10OpSpd
-    #endif
-    //#if OPTION_LRDIMMS
-    //extern MEM_PSC_FLOW MemPGetLRIBT;
-    //#define PSC_FLOW_OR_LR_IBT   MemPGetLRIBT
-    //extern MEM_PSC_FLOW MemPGetLRNPR;
-    //#define PSC_FLOW_OR_LR_NPR   MemPGetLRNPR
-    //extern MEM_PSC_FLOW MemPGetLRNLR;
-    //#define PSC_FLOW_OR_LR_NLR  MemPGetLRNLR
-    //#endif
-    #ifndef PSC_FLOW_OR_MAX_FREQ
-      #define PSC_FLOW_OR_MAX_FREQ   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_DRAM_TERM
-      #define PSC_FLOW_OR_DRAM_TERM   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_ODT_PATTERN
-      #define PSC_FLOW_OR_ODT_PATTERN   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_SAO
-      #define PSC_FLOW_OR_SAO   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_MR0_WRCL
-      #define PSC_FLOW_OR_MR0_WRCL   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_RC2_IBT
-      #define PSC_FLOW_OR_RC2_IBT   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_RC10_OPSPD
-      #define PSC_FLOW_OR_RC10_OPSPD   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_LR_IBT
-      #define PSC_FLOW_OR_LR_IBT   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_LR_NPR
-      #define PSC_FLOW_OR_LR_NPR   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_FLOW_OR_LR_NLR
-      #define PSC_FLOW_OR_LR_NLR   MEM_PSC_FLOW_DEFTRUE
-    #endif
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
-      &memPSCTblBlockOr,
-      PSC_FLOW_OR_MAX_FREQ,
-      PSC_FLOW_OR_DRAM_TERM,
-      PSC_FLOW_OR_ODT_PATTERN,
-      PSC_FLOW_OR_SAO,
-      PSC_FLOW_OR_MR0_WRCL,
-      PSC_FLOW_OR_RC2_IBT,
-      PSC_FLOW_OR_RC10_OPSPD,
-      PSC_FLOW_OR_LR_IBT,
-      PSC_FLOW_OR_LR_NPR,
-      PSC_FLOW_OR_LR_NLR
-    };
-    #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
-  #else
-    #define MEM_PSC_FLOW_BLOCK_OR
-  #endif
-
-
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
-    MEM_PSC_FLOW_BLOCK_OR
-    MEM_PSC_FLOW_BLOCK_END
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-  *
-  *  LRDIMM CONTROL
-  *
-  *---------------------------------------------------------------------------------------------------
-  */
-  #if (OPTION_LRDIMMS == TRUE)
-    #if (OPTION_MEMCTLR_OR == TRUE)
-      extern MEM_TECH_FEAT MemTLrdimmConstructor3;
-      #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
-    #else //#if (OPTION_MEMCTLR_OR == FALSE)
-      #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-    #endif
-  #else //#if (OPTION_LRDIMMS == FALSE)
-    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-  #endif
-  MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    MEM_TECH_FEATURE_LRDIMM_INIT
-  };
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY MAP
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    #undef MEM_NB_SUPPORT_DR
-    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
-  #endif
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    #undef MEM_NB_SUPPORT_RB
-    #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
-  #endif
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    #undef MEM_NB_SUPPORT_DA
-    #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
-  #endif
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    #undef MEM_NB_SUPPORT_PH
-    #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
-  #endif
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    #undef MEM_NB_SUPPORT_HY
-    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
-  #endif
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    #undef MEM_NB_SUPPORT_C32
-    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
-  #endif
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    #undef MEM_NB_SUPPORT_LN
-    #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
-  #endif
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    #undef MEM_NB_SUPPORT_ON
-    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
-  #endif
-  #if (OPTION_MEMCTLR_OR == TRUE)
-    #undef MEM_NB_SUPPORT_OR
-    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
-  #endif
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT Technology Training
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if OPTION_DDR2
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
-      NULL
-    };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
-      NULL
-    };
-  #endif
-  #if OPTION_DDR3
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
-      NULL
-    };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-      NULL
-    };
-  #endif
-    /*---------------------------------------------------------------------------------------------------
-     * DEFAULT Platform Specific list
-     *
-     *
-     *---------------------------------------------------------------------------------------------------
-     */
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_Ni == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_OR == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
-    NULL
-  };
-
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
-    NULL
-  };
-
-  MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    NULL
-  };
-#endif
-
-/*---------------------------------------------------------------------------------------------------
- * NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
-MEM_NB_SUPPORT memNBInstalled[] = {
-  MEM_NB_SUPPORT_RB
-  MEM_NB_SUPPORT_DA
-  MEM_NB_SUPPORT_Ni
-  MEM_NB_SUPPORT_PH
-  MEM_NB_SUPPORT_HY
-  MEM_NB_SUPPORT_LN
-  MEM_NB_SUPPORT_OR
-  MEM_NB_SUPPORT_C32
-  MEM_NB_SUPPORT_ON
-  MEM_NB_SUPPORT_END
-};
-
-#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h
deleted file mode 100644
index 443a3ca..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Memory option API.
- *
- * Contains structures and values used to control the Memory option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_RECOVERY_H_
-#define _OPTION_MEMORY_RECOVERY_H_
-
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-
-typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  );
-
-typedef VOID MEM_REC_TECH_CONSTRUCTOR (
-  IN OUT   MEM_TECH_BLOCK *TechPtr,
-  IN OUT   MEM_NB_BLOCK   *NBPtr
-  );
-
-#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h
deleted file mode 100644
index 2019947..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h
+++ /dev/null
@@ -1,602 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
-#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
-
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-
-  #define MEM_REC_NB_SUPPORT_OR
-
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
-    #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
-  #else
-    #define MEM_REC_NB_SUPPORT_DR
-  #endif
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
-    #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
-  #else
-    #define MEM_REC_NB_SUPPORT_RB
-  #endif
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
-    #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
-  #else
-    #define MEM_REC_NB_SUPPORT_DA
-  #endif
-  #if (OPTION_MEMCTLR_NI == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
-    #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
-  #else
-    #define MEM_REC_NB_SUPPORT_NI
-  #endif
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
-    #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
-  #else
-    #define MEM_REC_NB_SUPPORT_PH
-  #endif
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
-    #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
-  #else
-    #define MEM_REC_NB_SUPPORT_HY
-  #endif
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
-    #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
-  #else
-    #define MEM_REC_NB_SUPPORT_C32
-  #endif
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
-    #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
-  #else
-    #define MEM_REC_NB_SUPPORT_LN
-  #endif
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
-    #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
-  #else
-    #define MEM_REC_NB_SUPPORT_ON
-  #endif
-
-  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
-    MEM_REC_NB_SUPPORT_DR
-    MEM_REC_NB_SUPPORT_RB
-    MEM_REC_NB_SUPPORT_DA
-    MEM_REC_NB_SUPPORT_PH
-    MEM_REC_NB_SUPPORT_HY
-    MEM_REC_NB_SUPPORT_C32
-    MEM_REC_NB_SUPPORT_LN
-    MEM_REC_NB_SUPPORT_OR
-    MEM_REC_NB_SUPPORT_ON
-    MEM_REC_NB_SUPPORT_NI
-    NULL
-  };
-
-  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
-  #if (OPTION_DDR3 == TRUE)
-    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
-  #else
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
-    MEM_REC_TECH_CONSTRUCTOR_DDR3
-    MEM_REC_TECH_CONSTRUCTOR_DDR2
-    NULL
-  };
-
-  #if OPTION_MEMCTLR_DR
-    #define PSC_REC_DR_UDIMM_DDR2
-    #define PSC_REC_DR_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_DR_RDIMM_DDR2
-    #define PSC_REC_DR_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-    #define PSC_REC_DR_SODIMM_DDR2
-    #define PSC_REC_DR_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
-  #endif
-  #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
-    #define PSC_REC_DA_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_DA_SODIMM_DDR2
-    #define PSC_REC_DA_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_HY
-    #define PSC_REC_HY_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_HY_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_C32
-    #define PSC_REC_C32_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_C32_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_OR
-    #define PSC_REC_OR_UDIMM_DDR3    //MemRecNGetPsCfgUDIMM3OR,
-    #define PSC_REC_OR_RDIMM_DDR3    //MemRecNGetPsCfgRDIMM3OR,
-  #endif
-
-  #ifndef PSC_REC_DR_UDIMM_DDR2
-    #define PSC_REC_DR_UDIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_UDIMM_DDR3
-    #define PSC_REC_DR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DR_RDIMM_DDR2
-    #define PSC_REC_DR_RDIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_RDIMM_DDR3
-    #define PSC_REC_DR_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DR_SODIMM_DDR2
-    #define PSC_REC_DR_SODIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_SODIMM_DDR3
-    #define PSC_REC_DR_SODIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DA_UDIMM_DDR3
-    #define PSC_REC_DA_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DA_SODIMM_DDR2
-    #define PSC_REC_DA_SODIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DA_SODIMM_DDR3
-    #define PSC_REC_DA_SODIMM_DDR3
-  #endif
-  #ifndef PSC_REC_HY_UDIMM_DDR3
-    #define PSC_REC_HY_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_HY_RDIMM_DDR3
-    #define PSC_REC_HY_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_C32_UDIMM_DDR3
-    #define PSC_REC_C32_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_C32_RDIMM_DDR3
-    #define PSC_REC_C32_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_OR_UDIMM_DDR3
-    #define PSC_REC_OR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_OR_RDIMM_DDR3
-    #define PSC_REC_OR_RDIMM_DDR3
-  #endif
-
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    PSC_REC_DR_UDIMM_DDR2
-    PSC_REC_DR_RDIMM_DDR2
-    PSC_REC_DR_SODIMM_DDR2
-    PSC_REC_DR_UDIMM_DDR3
-    PSC_REC_DR_RDIMM_DDR3
-    PSC_REC_DR_SODIMM_DDR3
-    PSC_REC_DA_SODIMM_DDR2
-    PSC_REC_DA_UDIMM_DDR3
-    PSC_REC_DA_SODIMM_DDR3
-    PSC_REC_HY_UDIMM_DDR3
-    PSC_REC_HY_RDIMM_DDR3
-    PSC_REC_C32_UDIMM_DDR3
-    PSC_REC_C32_RDIMM_DDR3
-    PSC_REC_OR_UDIMM_DDR3
-    PSC_REC_OR_RDIMM_DDR3
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_REC_FLOW_BLOCK_END NULL
-  #define PSC_REC_TBL_END NULL
-  #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
-  #if OPTION_MEMCTLR_OR
-    #if OPTION_UDIMMS
-      #if OPTION_AM3_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &RecDramTermTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &RecOdtPat1DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3  &RecOdtPat2DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &RecOdtPat3DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecSAOTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3  &RecSAOTblEntUAM3,
-      #endif
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32  &RecDramTermTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &RecOdtPat1DTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32  &RecOdtPat2DTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &RecOdtPat3DTblEntUC32,
-        extern PSC_TBL_ENTRY RecSAOTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_C32  &RecSAOTblEntUC32,
-      #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34  &RecDramTermTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &RecOdtPat1DTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34  &RecOdtPat2DTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &RecOdtPat3DTblEntUG34,
-        extern PSC_TBL_ENTRY RecSAOTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_G34  &RecSAOTblEntUG34,
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32  &RecDramTermTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &RecOdtPat1DTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32  &RecOdtPat2DTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &RecOdtPat3DTblEntRC32,
-        extern PSC_TBL_ENTRY RecSAOTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_SAO_C32  &RecSAOTblEntRC32,
-        extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32  &RecRC2IBTTblEntRC32,
-      #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34  &RecDramTermTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &RecOdtPat1DTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34  &RecOdtPat2DTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &RecOdtPat3DTblEntRG34,
-        extern PSC_TBL_ENTRY RecSAOTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_SAO_G34  &RecSAOTblEntRG34,
-        extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34  &RecRC2IBTTblEntRG34,
-      #endif
-    #endif
-    //#if OPTION_SODIMMS
-    //#endif
-    //#if OPTION_LRDIMMS
-    //#endif
-    extern PSC_TBL_ENTRY RecMR0WrTblEntry;
-    #define PSC_REC_TBL_OR_MR0_WR  &RecMR0WrTblEntry,
-    extern PSC_TBL_ENTRY RecMR0CLTblEntry;
-    #define PSC_REC_TBL_OR_MR0_CL  &RecMR0CLTblEntry,
-
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
-    #endif
-
-    PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-      PSC_REC_TBL_OR_UDIMM3_SAO_C32
-      PSC_REC_TBL_OR_UDIMM3_SAO_G34
-      PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-      PSC_REC_TBL_OR_RDIMM3_SAO_C32
-      PSC_REC_TBL_OR_RDIMM3_SAO_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = {
-      PSC_REC_TBL_OR_MR0_WR
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = {
-      PSC_REC_TBL_OR_MR0_CL
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = {
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-      PSC_REC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = {
-      NULL,
-      (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL
-    };
-
-    extern MEM_PSC_FLOW MemPRecGetRttNomWr;
-    #define PSC_REC_FLOW_OR_DRAM_TERM   MemPRecGetRttNomWr
-    extern MEM_PSC_FLOW MemPRecGetODTPattern;
-    #define PSC_REC_FLOW_OR_ODT_PATTERN   MemPRecGetODTPattern
-    extern MEM_PSC_FLOW MemPRecGetSAO;
-    #define PSC_REC_FLOW_OR_SAO   MemPRecGetSAO
-    extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
-    #define PSC_REC_FLOW_OR_MR0_WRCL   MemPRecGetMR0WrCL
-    #if OPTION_RDIMMS
-      extern MEM_PSC_FLOW MemPRecGetRC2IBT;
-      #define PSC_REC_FLOW_OR_RC2_IBT    MemPRecGetRC2IBT
-    #endif
-    //#if OPTION_LRDIMMS
-    extern MEM_PSC_FLOW MemPRecGetLRIBT;
-    #define PSC_REC_FLOW_OR_LR_IBT   MemPRecGetLRIBT
-    extern MEM_PSC_FLOW MemPRecGetLRNPR;
-    #define PSC_REC_FLOW_OR_LR_NPR   MemPRecGetLRNPR
-    extern MEM_PSC_FLOW MemPRecGetLRNLR;
-    #define PSC_REC_FLOW_OR_LR_NLR  MemPRecGetLRNLR
-    //#endif
-    #ifndef PSC_REC_FLOW_OR_DRAM_TERM
-      #define PSC_REC_FLOW_OR_DRAM_TERM   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_ODT_PATTERN
-      #define PSC_REC_FLOW_OR_ODT_PATTERN   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_SAO
-      #define PSC_REC_FLOW_OR_SAO   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_MR0_WRCL
-      #define PSC_REC_FLOW_OR_MR0_WRCL   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_RC2_IBT
-      #define PSC_REC_FLOW_OR_RC2_IBT   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_IBT
-      #define PSC_REC_FLOW_OR_LR_IBT   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_NPR
-      #define PSC_REC_FLOW_OR_LR_NPR   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_NLR
-      #define PSC_REC_FLOW_OR_LR_NLR   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = {
-      &memRecPSCTblBlockOr,
-      NULL,
-      PSC_REC_FLOW_OR_DRAM_TERM,
-      PSC_REC_FLOW_OR_ODT_PATTERN,
-      PSC_REC_FLOW_OR_SAO,
-      PSC_REC_FLOW_OR_MR0_WRCL,
-      PSC_REC_FLOW_OR_RC2_IBT,
-      NULL,
-      PSC_REC_FLOW_OR_LR_IBT,
-      PSC_REC_FLOW_OR_LR_NPR,
-      PSC_REC_FLOW_OR_LR_NLR
-    };
-    #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR,
-  #else
-    #define MEM_PSC_REC_FLOW_BLOCK_OR
-  #endif
-
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    MEM_PSC_REC_FLOW_BLOCK_OR
-    MEM_PSC_REC_FLOW_BLOCK_END
-  };
-
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_NB_SUPPORT MemRecNBInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    NULL
-  };
-#endif
-#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h
deleted file mode 100644
index b1d91d9..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Message-Based C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
-#define _OPTION_MSG_BASED_C1E_INSTALL_H_
-
-#include "cpuMsgBasedC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_MSG_BASED_C1E_FEAT
-#define F10_MSG_BASED_C1E_SUPPORT
-#define F15_MSG_BASED_C1E_SUPPORT
-#if OPTION_MSG_BASED_C1E == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_HY == TRUE
-          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
-            extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
-            #undef OPTION_MSG_BASED_C1E_FEAT
-            #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
-          #endif
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
-          #undef OPTION_MSG_BASED_C1E_FEAT
-          #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY10H
-      #if OPTION_FAMILY10H == TRUE
-        #if OPTION_FAMILY10H_HY == TRUE
-          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
-            extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
-            #undef F10_MSG_BASED_C1E_SUPPORT
-            #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
-          #endif
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
-          extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15MsgBasedC1e;
-          #undef F15_MSG_BASED_C1E_SUPPORT
-          #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15MsgBasedC1e},
-        #endif
-      #endif
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
-    {
-      F10_MSG_BASED_C1E_SUPPORT
-      F15_MSG_BASED_C1E_SUPPORT
-      {0, NULL}
-    };
-    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
-    {
-      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-      &MsgBasedC1eFamilyServiceArray[0]
-    };
-  #endif
-#endif
-#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h
deleted file mode 100644
index 1e3fd14..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Multi-socket option API.
- *
- * Contains structures and values used to control the multi-socket option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MULTISOCKET_H_
-#define _OPTION_MULTISOCKET_H_
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * This function loops through all possible socket locations, gathering the number
- * of power management steps each populated socket requires, and returns the
- * highest number.
- *
- * @param[out] NumSystemSteps    Maximum number of system steps required
- * @param[in]  StdHeader         Config handle for library and services
- *
- */
-typedef VOID OPTION_MULTISOCKET_PM_STEPS (
-     OUT   UINT8 *NumSystemSteps,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/**
- * This function loops through all possible socket locations, starting core 0 of
- * each populated socket to perform the passed in AP_TASK.  After starting all
- * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
- * the system BSC only.
- *
- * @param[in]  TaskPtr           Function descriptor
- * @param[in]  StdHeader         Config handle for library and services
- * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
- *
- */
-typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
-  IN       VOID *TaskPtr,
-  IN       AMD_CONFIG_PARAMS *StdHeader,
-  IN       VOID *ConfigParams
-  );
-
-/**
- * This function loops through all possible socket locations, comparing the
- * maximum NB frequencies to determine the slowest.  This function also
- * determines if all coherent NB frequencies are equivalent.
- *
- * @param[in]  NbPstate                    NB P-state number to check (0 = fastest)
- * @param[in]  PlatformConfig              Platform profile/build option config structure.
- * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz
- * @param[out] SystemNbCofDenominator      NB frequency denominator for the system
- * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent
- * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs
- * @param[in]  StdHeader                   Config handle for library and services
- *
- * @retval     TRUE                        At least one processor has NbPstate enabled.
- * @retval     FALSE                       NbPstate is disabled on all CPUs
- */
-typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
-  IN       UINT32 NbPstate,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-     OUT   UINT32 *SystemNbCofNumerator,
-     OUT   UINT32 *SystemNbCofDenominator,
-     OUT   BOOLEAN *SystemNbCofsMatch,
-     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/**
- * This function loops through all possible socket locations, checking whether
- * any populated sockets require NB COF VID programming.
- *
- * @param[in]  StdHeader         Config handle for library and services
- *
- */
-typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/**
- * This function loops through all possible socket locations, collecting any
- * power management initialization errors that may have occurred.  These errors
- * are transferred from the core 0s of the socket in which the errors occurred
- * to the BSC's heap.  The BSC's heap is then searched for the most severe error
- * that occurred, and returns it.  This function must be called by the BSC only.
- *
- * @param[in]  StdHeader         Config handle for library and services
- *
- */
-typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-#define MULTISOCKET_STRUCT_VERSION  0x01
-
-/**
- * Provide build configuration of cpu multi-socket or single socket support.
- *
- */
-typedef struct  {
-  UINT16              OptMultiSocketVersion;                       ///< Table version
-  OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps;           ///< Method: Get number of power mgt tasks
-  OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s;   ///< Method: Perform tasks on Core 0 of each processor
-  OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings;         ///< Method: Find the limiting Northbridge frequency in the system.
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate;    ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
-  OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors;  ///< Method: Gathers error information from all Core 0s.
-} OPTION_MULTISOCKET_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif  // _OPTION_MULTISOCKET_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h
deleted file mode 100644
index 188212e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Multiple Socket Support
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MULTISOCKET_INSTALL_H_
-#define _OPTION_MULTISOCKET_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_MULTISOCKET
-  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-#if OPTION_MULTISOCKET == TRUE
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
-  #define GET_SYS_NB_COF      GetSystemNbCofMulti
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
-#else
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
-  #define GET_SYS_NB_COF      GetSystemNbCofSingle
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
-#endif
-
-/*  Declare the instance of the DMI option configuration structure  */
-OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
-  MULTISOCKET_STRUCT_VERSION,
-  GET_NUM_PM_STEPS,
-  CORE0_PM_TASK,
-  GET_SYS_NB_COF,
-  GET_SYS_NB_COF_UPDATE,
-  GET_EARLY_PM_ERRORS
-};
-
-#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h
deleted file mode 100644
index bd7d3f4..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Preserve Mailbox
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-
-#include "PreserveMailbox.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_PRESERVE_MAILBOX_FEAT
-#define F10_PRESERVE_MAILBOX_SUPPORT
-#define F15_PRESERVE_MAILBOX_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
-  #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
-    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
-    #undef OPTION_PRESERVE_MAILBOX_FEAT
-    #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
-  #endif
-  #if OPTION_FAMILY10H == TRUE
-    CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
-      MAKE_SBDFO (0, 0, 0, 3, 0x168),
-      MAKE_SBDFO (0, 0, 0, 3, 0x170),
-      ILLEGAL_SBDFO
-    };
-    CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
-      0,
-      TRUE,
-      (PCI_ADDR *)&F10PreserveMailboxRegisters
-    };
-    #undef F10_PRESERVE_MAILBOX_SUPPORT
-    #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
-  #endif
-  #if OPTION_FAMILY15H == TRUE
-    CONST PCI_ADDR ROMDATA F15PreserveMailboxRegisters [] = {
-      MAKE_SBDFO (0, 0, 0, 3, 0x168),
-      MAKE_SBDFO (0, 0, 0, 3, 0x170),
-      ILLEGAL_SBDFO
-    };
-    CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
-      0,
-      TRUE,
-      (PCI_ADDR *)&F15PreserveMailboxRegisters
-    };
-    #undef F15_PRESERVE_MAILBOX_SUPPORT
-    #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
-  #endif
-  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
-  {
-    F10_PRESERVE_MAILBOX_SUPPORT
-    F15_PRESERVE_MAILBOX_SUPPORT
-    {0, NULL}
-  };
-  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
-  {
-    (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-    &PreserveMailboxFamilyServiceArray[0]
-  };
-#endif
-
-#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPstate.h b/src/vendorcode/amd/agesa/Include/OptionPstate.h
deleted file mode 100644
index 27e1478..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPstate.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD ACPI PState option API.
- *
- * Contains structures and values used to control the PStates option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PSTATE_H_
-#define _OPTION_PSTATE_H_
-
-#include "cpuPstateTables.h"
-
-/*----------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_SSDT_FEATURE (
-  IN       AMD_CONFIG_PARAMS      *StdHeader,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN OUT   VOID                   **AcpiPstatePtr
-  );
-
-typedef UINT32 OPTION_ACPI_FEATURE (
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
-  IN OUT   VOID                   **AcpiPStatePtr,
-  IN       UINT8                  LocalApicId,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  );
-
-typedef AGESA_STATUS OPTION_PSTATE_GATHER (
-  IN       AMD_CONFIG_PARAMS *StdHeader,
-  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
-  );
-
-typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
-  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
-  IN       AMD_CONFIG_PARAMS  *StdHeader
-  );
-
-#define PSTATE_STRUCT_VERSION  0x01
-
-/// Indirection vectors for POST/PEI PState code
-typedef struct  {
-  UINT16                  OptPstateVersion;     ///< revision of this structure
-  OPTION_PSTATE_GATHER    *PstateGather;        ///< vector for data gathering routine
-  OPTION_PSTATE_LEVELING  *PstateLeveling;      ///< vector for leveling routine
-} OPTION_PSTATE_POST_CONFIGURATION;
-
-/// Indirection vectors for LATE/DXE PState code
-typedef struct  {
-  UINT16                  OptPstateVersion;     ///< revision of this structure
-  OPTION_SSDT_FEATURE     *SsdtFeature;         ///< vector for routine to generate SSDT
-  OPTION_ACPI_FEATURE     *PstateFeature;       ///< vector for routine to generate ACPI PState Objects
-  OPTION_ACPI_FEATURE     *CstateFeature;       ///< vector for routine to generate ACPI CState Objects
-  BOOLEAN                 CfgPstatePpc;         ///< boolean for creating _PPC method
-  BOOLEAN                 CfgPstatePct;         ///< boolean for creating _PCT method
-  BOOLEAN                 CfgPstatePsd;         ///< boolean for creating _PSD method
-  BOOLEAN                 CfgPstatePss;         ///< boolean for creating _PSS method
-  BOOLEAN                 CfgPstateXpss;        ///< boolean for creating _XPSS method
-} OPTION_PSTATE_LATE_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif  // _OPTION_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h
deleted file mode 100644
index 11ae4d3..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: PState
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PSTATE_INSTALL_H_
-#define _OPTION_PSTATE_INSTALL_H_
-
-#include "cpuPstateTables.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define F10_PSTATE_SERVICE_SUPPORT
-#define F12_PSTATE_SERVICE_SUPPORT
-#define F14_PSTATE_SERVICE_SUPPORT
-#define F15_PSTATE_SERVICE_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
-  //
-  //Define Pstate CPU Family service
-  //
-  #ifdef OPTION_FAMILY10H
-    #if OPTION_FAMILY10H == TRUE
-      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
-      #undef F10_PSTATE_SERVICE_SUPPORT
-      #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
-    #endif
-  #endif
-
-  #ifdef OPTION_FAMILY12H
-    #if OPTION_FAMILY12H == TRUE
-      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
-      #undef F12_PSTATE_SERVICE_SUPPORT
-      #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
-    #endif
-  #endif
-
-  #ifdef OPTION_FAMILY14H
-    #if OPTION_FAMILY14H == TRUE
-      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
-      #undef F14_PSTATE_SERVICE_SUPPORT
-      #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
-    #endif
-  #endif
-
-  #ifdef OPTION_FAMILY15H
-    #if OPTION_FAMILY15H == TRUE
-      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
-      #undef F15_PSTATE_SERVICE_SUPPORT
-      #define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
-    #endif
-  #endif
-  //
-  //Define ACPI Pstate objects.
-  //
-  #ifndef OPTION_ACPI_PSTATES
-    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
-  #endif
-  #if (OPTION_ACPI_PSTATES == TRUE)
-    OPTION_SSDT_FEATURE               GenerateSsdt;
-    #define USER_SSDT_MAIN            GenerateSsdt
-    #ifndef OPTION_MULTISOCKET
-      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-    #endif
-
-    OPTION_ACPI_FEATURE               CreatePStateAcpiTables;
-    OPTION_PSTATE_GATHER              PStateGatherMain;
-    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
-      OPTION_PSTATE_LEVELING          PStateLevelingMain;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
-    #else
-      OPTION_PSTATE_LEVELING            PStateLevelingStub;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #endif
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      #define USER_PSTATE_OPTION_MAIN   CreatePStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #endif
-    #if AGESA_ENTRY_INIT_POST == TRUE
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-    #else
-      OPTION_PSTATE_GATHER              PStateGatherStub;
-      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #endif
-    #if CFG_ACPI_PSTATES_PPC == TRUE
-      #define USER_PSTATE_CFG_PPC   TRUE
-    #else
-      #define USER_PSTATE_CFG_PPC   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PCT == TRUE
-      #define USER_PSTATE_CFG_PCT   TRUE
-    #else
-      #define USER_PSTATE_CFG_PCT   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSD == TRUE
-      #define USER_PSTATE_CFG_PSD   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSD   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSS == TRUE
-      #define USER_PSTATE_CFG_PSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSS   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_XPSS == TRUE
-      #define USER_PSTATE_CFG_XPSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_XPSS   FALSE
-    #endif
-
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_ACPI_FEATURE             CreateCStateAcpiTables;
-      #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE             CreateAcpiTablesStub;
-      #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
-    #endif
-  #else
-    OPTION_SSDT_FEATURE               GenerateSsdtStub;
-    OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-    OPTION_PSTATE_GATHER              PStateGatherStub;
-    OPTION_PSTATE_LEVELING            PStateLevelingStub;
-    #define USER_SSDT_MAIN            GenerateSsdtStub
-    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #define USER_PSTATE_CFG_PPC    FALSE
-    #define USER_PSTATE_CFG_PCT    FALSE
-    #define USER_PSTATE_CFG_PSD    FALSE
-    #define USER_PSTATE_CFG_PSS    FALSE
-    #define USER_PSTATE_CFG_XPSS   FALSE
-
-    // If ACPI Objects are disabled for PStates, we still need to check
-    // whether ACPI Objects are enabled for CStates
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_SSDT_FEATURE               GenerateSsdt;
-      OPTION_PSTATE_GATHER              PStateGatherMain;
-      OPTION_ACPI_FEATURE               CreateCStateAcpiTables;
-      #undef  USER_SSDT_MAIN
-      #define USER_SSDT_MAIN            GenerateSsdt
-      #undef  USER_PSTATE_OPTION_GATHER
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-      #undef  USER_CSTATE_OPTION_MAIN
-      #define USER_CSTATE_OPTION_MAIN   CreateCStateAcpiTables
-    #endif
-  #endif
-#else
-  OPTION_SSDT_FEATURE               GenerateSsdtStub;
-  OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-  OPTION_PSTATE_GATHER              PStateGatherStub;
-  OPTION_PSTATE_LEVELING            PStateLevelingStub;
-  #define USER_SSDT_MAIN            GenerateSsdtStub
-  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-  #define USER_PSTATE_CFG_PPC    FALSE
-  #define USER_PSTATE_CFG_PCT    FALSE
-  #define USER_PSTATE_CFG_PSD    FALSE
-  #define USER_PSTATE_CFG_PSS    FALSE
-  #define USER_PSTATE_CFG_XPSS   FALSE
-#endif
-
-/*  Declare the instance of the PSTATE option configuration structure  */
-OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_PSTATE_OPTION_GATHER,
-  USER_PSTATE_OPTION_LEVEL
-};
-
-OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_SSDT_MAIN,
-  USER_PSTATE_OPTION_MAIN,
-  USER_CSTATE_OPTION_MAIN,
-  USER_PSTATE_CFG_PPC,
-  USER_PSTATE_CFG_PCT,
-  USER_PSTATE_CFG_PSD,
-  USER_PSTATE_CFG_PSS,
-  USER_PSTATE_CFG_XPSS
-};
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
-{
-  F10_PSTATE_SERVICE_SUPPORT
-  F12_PSTATE_SERVICE_SUPPORT
-  F14_PSTATE_SERVICE_SUPPORT
-  F15_PSTATE_SERVICE_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
-{
-  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &PstateCpuFamilyServiceArray[0]
-};
-#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h
deleted file mode 100644
index 2804cae..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: S3SCRIPT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_S3SCRIPT_INSTALL_H_
-#define _OPTION_S3SCRIPT_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_S3SCRIPT
-  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_INIT      S3ScriptInitState
-  #endif
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
-  #endif
-#endif
-
-#ifndef P_S3_SCRIPT_INIT
-  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
-#endif
-
-#ifndef P_S3_SCRIPT_RESTORE
-  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
-  #undef  GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
-  #define GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-/*  Declare the instance of the S3SCRIPT option configuration structure  */
-S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
-  P_S3_SCRIPT_INIT,
-  P_S3_SCRIPT_RESTORE
-};
-
-S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
-  GNB_S3_DISPATCH_FUNCTION_TABLE
-  {0, NULL}
-};
-#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSlit.h b/src/vendorcode/amd/agesa/Include/OptionSlit.h
deleted file mode 100644
index b6c2a5b..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSlit.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD SLIT option API.
- *
- * Contains structures and values used to control the SLIT option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************