[coreboot] New patch to review: 04477eb Add the AMD Torpedo mainboard
Frank Vibrans III (efdesign98@gmail.com)
gerrit at coreboot.org
Tue Jun 21 06:52:39 CEST 2011
Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/54
-gerrit
commit 04477eb2537415ad18c0e28f5085204b52319bc9
Author: efdesign98 <efdesign98 at gmail.com>
Date: Mon Jun 20 21:48:37 2011 -0700
Add the AMD Torpedo mainboard
The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.
Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
src/mainboard/amd/Kconfig | 3 +
src/mainboard/amd/torpedo/BiosCallOuts.c | 670 ++++++
src/mainboard/amd/torpedo/BiosCallOuts.h | 76 +
src/mainboard/amd/torpedo/Kconfig | 222 ++
src/mainboard/amd/torpedo/Makefile.inc | 38 +
src/mainboard/amd/torpedo/Oem.h | 259 +++
src/mainboard/amd/torpedo/OptionsIds.h | 64 +
src/mainboard/amd/torpedo/PlatformGnbPcie.c | 176 ++
src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 72 +
src/mainboard/amd/torpedo/acpi/cpstate.asl | 75 +
src/mainboard/amd/torpedo/acpi/ide.asl | 244 ++
src/mainboard/amd/torpedo/acpi/routing.asl | 311 +++
src/mainboard/amd/torpedo/acpi/sata.asl | 149 ++
src/mainboard/amd/torpedo/acpi/ssdt2.asl | 84 +
src/mainboard/amd/torpedo/acpi/ssdt3.asl | 84 +
src/mainboard/amd/torpedo/acpi/ssdt4.asl | 84 +
src/mainboard/amd/torpedo/acpi/ssdt5.asl | 85 +
src/mainboard/amd/torpedo/acpi/usb.asl | 20 +
src/mainboard/amd/torpedo/acpi_tables.c | 258 +++
src/mainboard/amd/torpedo/agesawrapper.c | 584 +++++
src/mainboard/amd/torpedo/agesawrapper.h | 135 ++
src/mainboard/amd/torpedo/buildOpts.c | 387 ++++
src/mainboard/amd/torpedo/cfg.c | 307 +++
src/mainboard/amd/torpedo/cfg.h | 1242 +++++++++++
src/mainboard/amd/torpedo/chip.h | 23 +
src/mainboard/amd/torpedo/cmos.layout | 118 +
src/mainboard/amd/torpedo/devicetree.cb | 90 +
src/mainboard/amd/torpedo/dimmSpd.c | 241 ++
src/mainboard/amd/torpedo/dimmSpd.h | 63 +
src/mainboard/amd/torpedo/dsdt.asl | 1142 ++++++++++
src/mainboard/amd/torpedo/fadt.c | 207 ++
src/mainboard/amd/torpedo/get_bus_conf.c | 145 ++
src/mainboard/amd/torpedo/gpio.c | 482 ++++
src/mainboard/amd/torpedo/gpio.h | 2329 ++++++++++++++++++++
src/mainboard/amd/torpedo/irq_tables.c | 123 +
src/mainboard/amd/torpedo/mainboard.c | 119 +
src/mainboard/amd/torpedo/mptable.c | 252 +++
src/mainboard/amd/torpedo/pmio.c | 55 +
src/mainboard/amd/torpedo/pmio.h | 34 +
src/mainboard/amd/torpedo/reset.c | 66 +
src/mainboard/amd/torpedo/romstage.c | 127 ++
41 files changed, 11245 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig
index 6b18478..9ed3133 100644
--- a/src/mainboard/amd/Kconfig
+++ b/src/mainboard/amd/Kconfig
@@ -29,6 +29,8 @@ config BOARD_AMD_INAGUA
bool "Inagua"
config BOARD_AMD_PERSIMMON
bool "Persimmon"
+config BOARD_AMD_TORPEDO
+ bool "Torpedo"
endchoice
source "src/mainboard/amd/db800/Kconfig"
@@ -44,6 +46,7 @@ source "src/mainboard/amd/tilapia_fam10/Kconfig"
source "src/mainboard/amd/bimini_fam10/Kconfig"
source "src/mainboard/amd/inagua/Kconfig"
source "src/mainboard/amd/persimmon/Kconfig"
+source "src/mainboard/amd/torpedo/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
new file mode 100755
index 0000000..ff55e24
--- /dev/null
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -0,0 +1,670 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "Hudson-2.h"
+
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01 1
+#endif
+
+#ifndef SB_GPIO_REG24
+#define SB_GPIO_REG24 24
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27 27
+#endif
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER,
+ BiosAllocateBuffer
+ },
+
+ {AGESA_DEALLOCATE_BUFFER,
+ BiosDeallocateBuffer
+ },
+
+ {AGESA_DO_RESET,
+ BiosReset
+ },
+
+ {AGESA_LOCATE_BUFFER,
+ BiosLocateBuffer
+ },
+
+ {AGESA_READ_SPD,
+ BiosReadSpd
+ },
+
+ {AGESA_READ_SPD_RECOVERY,
+ BiosDefaultRet
+ },
+
+ {AGESA_RUNFUNC_ONAP,
+ BiosRunFuncOnAp
+ },
+
+ {AGESA_GNB_PCIE_SLOT_RESET,
+ BiosGnbPcieSlotReset
+ },
+
+ {AGESA_GET_IDS_INIT_DATA,
+ BiosGetIdsInitData
+ },
+
+ {AGESA_HOOKBEFORE_DRAM_INIT,
+ BiosHookBeforeDramInit
+ },
+
+ {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+ BiosHookBeforeDramInitRecovery
+ },
+
+ {AGESA_HOOKBEFORE_DQS_TRAINING,
+ BiosHookBeforeDQSTraining
+ },
+
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF,
+ BiosHookBeforeExitSelfRefresh
+ },
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+ UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+ for (i = 0; i < CallOutCount; i++)
+ {
+ if (BiosCallouts[i].CalloutName == Func)
+ {
+ break;
+ }
+ }
+
+ if(i >= CallOutCount)
+ {
+ return AGESA_UNSUPPORTED;
+ }
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+ /*{
+ AGESA_IDS_NV_MAIN_PLL_CON,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID_EN,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID,
+ 0x8
+ },
+
+ {
+ AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_FORCE_NB_PSTATE,
+ },
+*/
+ {
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ IDS_NV_ITEM *IdsPtr;
+
+ IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+ if (Data == IDS_CALLOUT_INIT) {
+ for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+ IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+ IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap. */
+ /* If it has, return AGESA_BOUNDS_CHK */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ to the end of the allocated nodes list.
+ */
+
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer */
+ /* size, return AGESA_BOUNDS_CHK */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ StartOfFreedNodes to reflect the new free node
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ should be place
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ concatenate both nodes
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ concatenate both nodes
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+
+ Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+ return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINT8 Value;
+ UINTN ResetType;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ ResetType = Data;
+ StdHeader = ConfigPtr;
+
+ //
+ // Perform the RESET based upon the ResetType. In case of
+ // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+ // AmdResetManager. During the critical condition, where reset is required
+ // immediately, the reset will be invoked directly by writing 0x04 to port
+ // 0xCF9 (Reset Port).
+ //
+ switch (ResetType) {
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
+ break;
+
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ break;
+
+ default:
+ break;
+ }
+
+ Status = 0;
+ return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
+
+ return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_UNSUPPORTED;
+}
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ MEM_DATA_STRUCT *MemData;
+ UINT32 AcpiMmioAddr;
+ UINT32 GpioMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
+ UINT8 TempData8;
+
+ FcnData = Data;
+ MemData = ConfigPtr;
+
+ Status = AGESA_SUCCESS;
+ /* Get SB MMIO Base (AcpiMmioAddr) */
+ WriteIo8 (0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16 = Data8<<8;
+ WriteIo8 (0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16 |= Data8;
+ AcpiMmioAddr = (UINT32)Data16 << 16;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_5) {
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_35) {
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_25) {
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ } else {}
+ return Status;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ PCIe_SLOT_RESET_INFO *ResetInfo;
+
+ UINT32 GpioMmioAddr;
+ UINT32 AcpiMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
+
+ FcnData = Data;
+ ResetInfo = ConfigPtr;
+ // Get SB MMIO Base (AcpiMmioAddr)
+ WriteIo8(0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16=Data8<<8;
+ WriteIo8(0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16|=Data8;
+ AcpiMmioAddr = (UINT32)Data16 << 16;
+ Status = AGESA_UNSUPPORTED;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+
+ if (ResetInfo->ResetControl == DeassertSlotReset) {
+ if (ResetInfo->ResetId & BIT2+BIT3) { //de-assert
+ // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
+ if (Data8 & BIT7) {
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+ while (!(Data8 & BIT7)) {
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+ }
+ // GPIO44: PE_GPIO0 MXM Reset
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+ Status = AGESA_SUCCESS;
+ }
+ } else {
+ Status = AGESA_UNSUPPORTED;
+ }
+ // Travis
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+ //DE-Assert ALL PCIE RESET
+ // APU GPP0 (Dev 4)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+ // APU GPP1 (Dev 5)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+ // APU GPP2 (Dev 6)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+ // APU GPP3 (Dev 7)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+ } else {
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
+ // GPIO44: PE_GPIO0 MXM Reset
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+ Status = AGESA_SUCCESS;
+ }
+ // Travis
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+ //Assert ALL PCIE RESET
+ // APU GPP0 (Dev 4)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+ // APU GPP1 (Dev 5)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+ // APU GPP2 (Dev 6)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+ // APU GPP3 (Dev 7)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+ }
+ return Status;
+}
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.h b/src/mainboard/amd/torpedo/BiosCallOuts.h
new file mode 100755
index 0000000..4be7a04
--- /dev/null
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define BIOS_HEAP_START_ADDRESS 0x00010000
+#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+ //UINT32 AvailableSize;
+ UINT32 StartOfAllocatedNodes;
+ UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+ UINT32 BufferHandle;
+ UINT32 BufferSize;
+ UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+// These registers are not defined in cimx/SB900/Hudson-2.h
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG25 25
+#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
new file mode 100755
index 0000000..57d8c05
--- /dev/null
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -0,0 +1,222 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_AMD_TORPEDO
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select DIMM_DDR3
+ select DIMM_UNREGISTERED
+ select CPU_AMD_AGESA_FAMILY12
+ select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY12
+ select SOUTHBRIDGE_AMD_CIMX_SB900
+ select SUPERIO_SMSC_KBC1100
+ select BOARD_HAS_FADT
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_MAINBOARD_RESOURCES
+ select HAVE_HARD_RESET
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select LIFT_BSP_APIC_ID
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_2048
+ select ENABLE_APIC_EXT_ID
+ select TINY_BOOTBLOCK
+ select GFXUMA
+
+config AMD_AGESA
+ bool
+ default y
+
+config AMD_CIMX_SB900
+ bool
+ default y
+
+config MAINBOARD_DIR
+ string
+ default amd/torpedo
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Torpedo"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 1
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config STACK_SIZE
+ hex
+ default 0x10000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config SIO_PORT
+ hex
+ default 0x2e
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS
+ bool
+ default n
+
+#config VGA_BIOS_FILE
+# string "VGA BIOS path and filename"
+# depends on VGA_BIOS
+# default "rom/video/LlanoGenericVbios.bin"
+
+config VGA_BIOS_ID
+ string "VGA device PCI IDs"
+ depends on VGA_BIOS
+ default "1002,9641"
+
+config AHCI_BIOS
+ bool
+ default n
+
+#config AHCI_BIOS_FILE
+# string "AHCI ROM path and filename"
+# depends on AHCI_BIOS
+# default "rom/ahci/sb900.bin"
+
+config AHCI_BIOS_ID
+ string "AHCI device PCI IDs"
+ depends on AHCI_BIOS
+ default "1022,7801"
+
+config XHC_BIOS
+ bool
+ default n
+
+#config XHC_BIOS_FILE
+# string "XHC BIOS path and filename"
+# depends on XHC_BIOS
+# default "rom/xhc/Xhc.rom"
+
+config XHC_BIOS_ID
+ string "XHC device PCI IDs"
+ depends on XHC_BIOS
+ default "1022,7812"
+
+config CONSOLE_POST
+ bool
+ depends on !NO_POST
+ default y
+
+config SATA_CONTROLLER_MODE
+ hex
+ default 0x0
+ depends on SOUTHBRIDGE_AMD_CIMX_SB900
+
+config ONBOARD_LAN
+ bool
+ default y
+
+config ONBOARD_1394
+ bool
+ default y
+
+config ONBOARD_USB30
+ bool
+ default n
+
+config ONBOARD_BLUETOOTH
+ bool
+ default y
+
+config ONBOARD_WEBCAM
+ bool
+ default y
+
+config ONBOARD_TRAVIS
+ bool
+ default y
+
+config ONBOARD_LIGHTSENSOR
+ bool
+ default n
+
+endif # BOARD_AMD_TORPEDO
+
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
new file mode 100755
index 0000000..051d936
--- /dev/null
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -0,0 +1,38 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+romstage-y += cfg.c
+romstage-y += gpio.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+ramstage-y += cfg.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
+
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
new file mode 100755
index 0000000..50bb506
--- /dev/null
+++ b/src/mainboard/amd/torpedo/Oem.h
@@ -0,0 +1,259 @@
+/*;********************************************************************************
+;
+; Copyright 2011 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD. This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property. Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions. If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY: The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you. Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#define BIOS_SIZE 0x04 //04 - 1MB
+#define LEGACY_FREE 0x00
+#if CONFIG_ONBOARD_USB30 == 0
+ #define XHCI_SUPPORT 0x01
+#endif
+
+//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot.
+//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
+
+/**
+ * Module Specific Defines for platform BIOS
+ *
+ */
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef MOVE_PCIEBAR_TO_F0000000
+ #define PCIEX_BASE_ADDRESS 0xF7000000
+#else
+ #define PCIEX_BASE_ADDRESS 0xE0000000
+#endif
+
+/**
+ * SMBUS0_BASE_ADDRESS - Smbus base address
+ *
+ */
+#ifndef SMBUS0_BASE_ADDRESS
+ #define SMBUS0_BASE_ADDRESS 0xB00
+#endif
+
+/**
+ * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
+ *
+ */
+#ifndef SMBUS1_BASE_ADDRESS
+ #define SMBUS1_BASE_ADDRESS 0xB20
+#endif
+
+/**
+ * SIO_PME_BASE_ADDRESS - Super IO PME base address
+ *
+ */
+#ifndef SIO_PME_BASE_ADDRESS
+ #define SIO_PME_BASE_ADDRESS 0xE00
+#endif
+
+/**
+ * SPI_BASE_ADDRESS - SPI controller (ROM) base address
+ *
+ */
+#ifndef SPI_BASE_ADDRESS
+ #define SPI_BASE_ADDRESS 0xFEC10000
+#endif
+
+/**
+ * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
+ *
+ */
+#ifndef WATCHDOG_TIMER_BASE_ADDRESS
+ #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
+#endif
+
+/**
+ * HPET_BASE_ADDRESS - HPET base address
+ *
+ */
+#ifndef HPET_BASE_ADDRESS
+ #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
+#endif
+
+/**
+ * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
+ *
+ */
+#ifdef ALT_ADDR_400
+ #define ACPI_BLK_BASE 0x400
+#else
+ #define ACPI_BLK_BASE 0x800
+#endif
+
+#define PM1_STATUS_OFFSET 0x00
+#define PM1_ENABLE_OFFSET 0x02
+#define PM1_CONTROL_OFFSET 0x04
+#define PM_TIMER_OFFSET 0x08
+#define CPU_CONTROL_OFFSET 0x10
+#define EVENT_STATUS_OFFSET 0x20
+#define EVENT_ENABLE_OFFSET 0x24
+
+/**
+ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
+ *
+ */
+#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
+
+/**
+ * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
+ *
+ */
+#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
+
+/**
+ * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
+ *
+ */
+#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
+
+/**
+ * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
+ *
+ */
+#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
+
+/**
+ * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
+ *
+ */
+#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
+
+/**
+ * SMI_CMD_PORT - ACPI SMI Command block base address
+ *
+ */
+#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
+
+/**
+ * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
+ *
+ */
+#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
+
+/**
+ * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
+ * Define value for SSID while SATA controller set to IDE mode.
+ */
+#define SATA_IDE_MODE_SSID 0x78001022
+/**
+ * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
+ * Define value for SSID while SATA controller set to RAID mode.
+ */
+#define SATA_RAID_MODE_SSID 0x78021022
+
+/**
+ * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
+ * Define value for SSID while SATA controller set to RAID5 mode.
+ */
+#define SATA_RAID5_MODE_SSID 0x78031022
+
+/**
+ * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
+ * Define value for SSID while SATA controller set to AHCI mode.
+ */
+#define SATA_AHCI_SSID 0x78011022
+
+/**
+ * OHCI_SSID - All SB OHCI controllers SSID value.
+ *
+ */
+#define OHCI_SSID 0x78071022
+
+/**
+ * EHCI_SSID - All SB EHCI controllers SSID value.
+ *
+ */
+#define EHCI_SSID 0x78081022
+
+/**
+ * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
+ *
+ */
+#define OHCI4_SSID 0x78091022
+
+/**
+ * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
+ *
+ */
+#define SMBUS_SSID 0x780B1022
+
+/**
+ * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
+ *
+ */
+#define IDE_SSID 0x780C1022
+
+/**
+ * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
+ *
+ */
+#define AZALIA_SSID 0x780D1022
+
+/**
+ * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
+ *
+ */
+#define LPC_SSID 0x780E1022
+
+/**
+ * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
+ *
+ */
+#define PCIB_SSID 0x780F1022
+
diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h
new file mode 100755
index 0000000..e3a1d73
--- /dev/null
+++ b/src/mainboard/amd/torpedo/OptionsIds.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c
new file mode 100755
index 0000000..2d011d9
--- /dev/null
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+ // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ {
+ 0, //Descriptor flags
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ {
+ 0, //Descriptor flags
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ }
+ // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+// {
+// DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
+// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+// }
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+ // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
+ {
+ 0, //Descriptor flags
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
+ }
+};
+
+PCIe_COMPLEX_DESCRIPTOR Llano = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ &PortList[0],
+ &DdiList[0]
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ VOID *LlanoPcieComplexListPtr;
+ VOID *LlanoPciePortPtr;
+ VOID *LlanoPcieDdiPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+ // GNB PCIe topology Porting
+
+ //
+ // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ //
+ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
+ sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ ASSERT(FALSE);
+ return;
+ }
+
+ LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+ LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
+ LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ LibAmdMemFill (LlanoPcieComplexListPtr,
+ 0,
+ sizeof (PCIe_COMPLEX_DESCRIPTOR),
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (LlanoPciePortPtr,
+ 0,
+ sizeof (PCIe_PORT_DESCRIPTOR) * 7,
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (LlanoPcieDdiPtr,
+ 0,
+ sizeof (PCIe_DDI_DESCRIPTOR) * 6,
+ &InitEarly->StdHeader);
+
+ LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+ LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
+ LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
+
+
+ ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
+
+ InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
new file mode 100755
index 0000000..f35d8db
--- /dev/null
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/torpedo/acpi/cpstate.asl b/src/mainboard/amd/torpedo/acpi/cpstate.asl
new file mode 100755
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package ()
+ {
+ 0x00000AF0,
+ 0x0000BF81,
+ 0x00000002,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package ()
+ {
+ 0x00000578,
+ 0x000076F2,
+ 0x00000002,
+ 0x00000002,
+ 0x00000001,
+ 0x00000001
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/amd/torpedo/acpi/ide.asl b/src/mainboard/amd/torpedo/acpi/ide.asl
new file mode 100755
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
diff --git a/src/mainboard/amd/torpedo/acpi/routing.asl b/src/mainboard/amd/torpedo/acpi/routing.asl
new file mode 100755
index 0000000..db1fdf6
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/routing.asl
@@ -0,0 +1,311 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - RS780 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ Package(){0x0001FFFF, 0, INTC, 0 },
+ Package(){0x0001FFFF, 1, INTD, 0 },
+ /* Bus 0, Dev 2 - */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 3 - */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+ /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+ /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - RS780 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ Package(){0x0001FFFF, 0, 0, 18 },
+ Package(){0x0001FFFF, 1, 0, 19 },
+ /* Bus 0, Dev 2 */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+ /* Bus 0, Dev 3 */
+ Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+ /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+ Package(){0x0010FFFF, 0, 0, 18 },
+ Package(){0x0010FFFF, 1, 0, 17 },
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ Package(){0x0011FFFF, 0, 0, 19 },
+ /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* For Device(PBR2) PIC mode*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+
+ Name(APS2, Package(){
+ /* For Device(PBR2) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS3, Package(){
+ /* For Device(PBR3) PIC mode*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS3, Package(){
+ /* For Device(PBR3) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PS4, Package(){
+ /* For Device(PBR4) PIC mode*/
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+
+ Name(APS4, Package(){
+ /* For Device(PBR4) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* For Device(PBR5) PIC mode*/
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+
+ Name(APS5, Package(){
+ /* For Device(PBR5) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* For Device(PBR6) PIC mode*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+
+ Name(APS6, Package(){
+ /* For Device(PBR6) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* For Device(PBR7) PIC mode*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* For Device(PBR7) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PE0, Package(){
+ /* For Device(PE20) PIC mode*/
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+
+ Name(APE0, Package(){
+ /* For Device(PE20) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PE1, Package(){
+ /* For Device(PE21) PIC mode*/
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+
+ Name(APE1, Package(){
+ /* For Device(PE21) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PE2, Package(){
+ /* For Device(PE22) PIC mode*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+
+ Name(APE2, Package(){
+ /* For Device(PE22) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE3, Package(){
+ /* For Device(PE23) PIC mode*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APE3, Package(){
+ /* For Device(PE23) APIC mode*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+}
diff --git a/src/mainboard/amd/torpedo/acpi/sata.asl b/src/mainboard/amd/torpedo/acpi/sata.asl
new file mode 100755
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/amd/torpedo/acpi/ssdt2.asl b/src/mainboard/amd/torpedo/acpi/ssdt2.asl
new file mode 100755
index 0000000..ef1a4bf
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/ssdt2.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci2_hc.asl"
+ }
+ }
+
+}
+
diff --git a/src/mainboard/amd/torpedo/acpi/ssdt3.asl b/src/mainboard/amd/torpedo/acpi/ssdt3.asl
new file mode 100755
index 0000000..68a4b95
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/ssdt3.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci3_hc.asl"
+ }
+ }
+
+}
+
diff --git a/src/mainboard/amd/torpedo/acpi/ssdt4.asl b/src/mainboard/amd/torpedo/acpi/ssdt4.asl
new file mode 100755
index 0000000..e06fe8a
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/ssdt4.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci4_hc.asl"
+ }
+ }
+
+}
+
diff --git a/src/mainboard/amd/torpedo/acpi/ssdt5.asl b/src/mainboard/amd/torpedo/acpi/ssdt5.asl
new file mode 100755
index 0000000..a141a37
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/ssdt5.asl
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci5_hc.asl"
+ }
+ }
+
+}
+
diff --git a/src/mainboard/amd/torpedo/acpi/usb.asl b/src/mainboard/amd/torpedo/acpi/usb.asl
new file mode 100755
index 0000000..d80bc2a
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi/usb.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c
new file mode 100755
index 0000000..7f4f2d9
--- /dev/null
+++ b/src/mainboard/amd/torpedo/acpi_tables.c
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+extern u32 apicid_sb900;
+
+
+#if DUMP_ACPI_TABLES == 1
+
+static void dump_mem(u32 start, u32 end)
+{
+
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);
+
+ /* Write SB900 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16 bytes */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+#if 0 // Don't need HPET table.
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+#endif
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* SRAT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy(current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ //acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ }
+
+ /* SLIT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy(current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ //acpi_create_slit(slit);
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ }
+
+ /* SSDT */
+ current = ( current + 0x0f) & -0x10;
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy(current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ ssdt = (acpi_header_t *) current;
+ memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+ current += ssdt->length;
+ memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+
+ /* DSDT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; // it will used by fadt
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ // it needs 64 bit alignment
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current; // it will be used by fadt
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c
new file mode 100755
index 0000000..2995856
--- /dev/null
+++ b/src/mainboard/amd/torpedo/agesawrapper.c
@@ -0,0 +1,584 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+#include <arch/io.h>
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+ReadAmdSbPmr (
+ IN UINT8 IndexValue,
+ OUT UINT8 *DataValue
+ );
+
+UINT32
+WriteAmdSbPmr (
+ IN UINT8 IndexValue,
+ IN UINT8 DataValue
+ );
+
+VOID
+ClearSBSmiAndWake (
+ IN UINT16 PmBase
+ );
+
+VOID
+ClearAllSmiEnableInPmio (
+ VOID
+ );
+
+
+
+/* Read SB Power Management Area */
+UINT32
+ReadAmdSbPmr (
+ IN UINT8 IndexValue,
+ OUT UINT8 *DataValue
+ )
+{
+ WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
+ *DataValue = ReadIo8 (SB_PM_DATA_PORT);
+ return 0;
+}
+
+/* Write ATI SB Power Management Area */
+UINT32
+WriteAmdSbPmr (
+ IN UINT8 IndexValue,
+ IN UINT8 DataValue
+ )
+{
+ WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
+ WriteIo8 (SB_PM_DATA_PORT, DataValue);
+ return 0;
+}
+
+/* Clear any SMI status or wake status left over from boot. */
+VOID
+ClearSBSmiAndWake (
+ IN UINT16 PmBase
+ )
+{
+ UINT16 Pm1Sts;
+ UINT32 Pm1Cnt;
+ UINT32 Gpe0Sts;
+
+ /* Read the ACPI registers */
+ Pm1Sts = ReadIo16 (PmBase + R_SB_ACPI_PM1_STATUS);
+ Pm1Cnt = ReadIo32 (PmBase + R_SB_ACPI_PM1_STATUS);
+ Gpe0Sts = ReadIo32 (PmBase + R_SB_ACPI_EVENT_STATUS);
+
+ /* Clear any SMI or wake state from the boot */
+ Pm1Sts &= B_PWR_BTN_STATUS + B_WAKEUP_STATUS;
+ Pm1Cnt &= ~(B_SCI_EN);
+
+ /* Write back */
+ WriteIo16 (PmBase + R_SB_ACPI_PM1_STATUS, Pm1Sts);
+ WriteIo32 (PmBase + R_SB_ACPI_PM_CONTROL, Pm1Cnt);
+ WriteIo32 (PmBase + R_SB_ACPI_EVENT_STATUS, Gpe0Sts);
+}
+
+/* Clear all SMI enable bit in PMIO register */
+VOID
+ClearAllSmiEnableInPmio (
+ VOID
+ )
+{
+ UINT32 AcpiMmioAddr;
+ UINT32 SmiMmioAddr;
+ UINT8 Data8 = 0 ;
+ UINT16 Data16 = 0;
+
+ /* Get SB900 MMIO Base (AcpiMmioAddr) */
+ ReadAmdSbPmr (SB_PMIOA_REG24 + 3, &Data8);
+ Data16=Data8<<8;
+ ReadAmdSbPmr (SB_PMIOA_REG24 + 2, &Data8);
+ Data16|=Data8;
+ AcpiMmioAddr = (UINT32)Data16 << 16;
+ SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
+
+ Mmio32 (SmiMmioAddr, 0xA0) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xA4) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xA8) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xAC) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xB0) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xB4) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xB8) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xBC) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xC0) = 0x0;
+ Mmio32 (SmiMmioAddr, 0xC4) = 0x0;
+}
+
+UINT32
+agesawrapper_amdinitcpuio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+
+ /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00000B00;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = 0x00000A03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set TOM-DFFFFFFF to Node0 Link0. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00DFFF00;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
+ PciData = 0x00FFFF00 | 0x80;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
+ PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+//- PciData = 0x0000F000;
+ PciData = 0x00FFF000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000013;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitmmio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000ull;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set Ontario Link Data */
+//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+//- PciData = 0x01308002;
+//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+//- PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Enable Non-Post Memory in CPU */
+ PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA4);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA0);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Enable memory access */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+ LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+ PciData |= BIT1;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+ LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
+//- ClearSBSmiAndWake (SB_ACPI_BASE_ADDRESS);
+//- ClearAllSmiEnableInPmio ();
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitreset (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+
+ LibAmdMemFill (&AmdResetParams,
+ 0,
+ sizeof (AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = NULL;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+ return (UINT32)status;
+ }
+
+UINT32
+agesawrapper_amdinitearly (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+ status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitpost (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+ {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitenv (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+ int pick
+ )
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+
+ case PICK_PSTATE:
+ return AcpiPstate;
+
+ case PICK_SRAT:
+ return AcpiSrat;
+
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ default:
+ return NULL;
+ }
+}
+
+UINT32
+agesawrapper_amdinitmid (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio ();
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+
+ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitlate (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill (&AmdLateParams,
+ 0,
+ sizeof (AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+ Status = AmdInitLate (&AmdLateParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ AcpiAlib = AmdLateParams.AcpiAlib;
+
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdlaterunaptask (
+ UINT32 Data,
+ VOID *ConfigPtr
+ )
+{
+ AGESA_STATUS Status;
+ AP_EXE_PARAMS ApExeParams;
+
+ LibAmdMemFill (&ApExeParams,
+ 0,
+ sizeof (AP_EXE_PARAMS),
+ &(ApExeParams.StdHeader));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+
+ Status = AmdLateRunApTask (&ApExeParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdreadeventlog (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill (&AmdEventParams,
+ 0,
+ sizeof (EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ Status = AmdReadEventLog (&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ Status = AmdReadEventLog (&AmdEventParams);
+ }
+
+ return (UINT32)Status;
+}
diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h
new file mode 100755
index 0000000..979f743
--- /dev/null
+++ b/src/mainboard/amd/torpedo/agesawrapper.h
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+/* Hudson-2 ACPI PmIO Space Define */
+#define SB_ACPI_BASE_ADDRESS 0x0400
+#define ACPI_MMIO_BASE 0xFED80000
+#define SB_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 // ??
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACPI_SMI_DATA_PORT 0xB1
+#define R_SB_ACPI_PM1_STATUS 0x00
+#define R_SB_ACPI_PM1_ENABLE 0x02
+#define R_SB_ACPI_PM_CONTROL 0x04
+#define R_SB_ACPI_EVENT_STATUS 0x20
+#define R_SB_ACPI_EVENT_ENABLE 0x24
+#define B_PWR_BTN_STATUS BIT8
+#define B_WAKEUP_STATUS BIT15
+#define B_SCI_EN BIT0
+#define SB_PM_INDEX_PORT 0xCD6
+#define SB_PM_DATA_PORT 0xCD7
+#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
+#define MmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+#define Mmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+#define Mmio32( BaseAddr, Register ) \
+ *Mmio32Ptr( BaseAddr, Register )
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+//void brazos_platform_stage(void);
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+
+UINT32 agesawrapper_amdreadeventlog (void);
+UINT32 agesawrapper_amdinitcpuio (void);
+UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Data, VOID *ConfigPtr);
+void *agesawrapper_getlateinitptr (int pick);
+
+#endif
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
new file mode 100755
index 0000000..0379a81
--- /dev/null
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -0,0 +1,387 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Sabine/Lynx platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+#include "AGESA.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+
+/* Select the cpu family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT TRUE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_SUPPORT FALSE
+
+/* Select the cpu socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
+#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
+#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE
+#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT TRUE
+#define BLDOPT_REMOVE_SLIT TRUE
+#define BLDOPT_REMOVE_WHEA TRUE
+#define BLDOPT_REMOVE_DMI FALSE
+#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
+
+//For revision C single-link processors
+#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
+
+/*
+ * Agesa entry points used in this implementation.
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "LlanoPI "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+
+//enable HW C1E
+#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware
+//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
+
+
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero.
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero.
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
+
+#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE
+#define BLDCFG_STEREO_3D_PINOUT TRUE
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
+//#define OPTION_NB_LCLK_DPM_INIT FALSE
+//#define OPTION_POWER_GATE FALSE
+//#define OPTION_PCIE_POWER_GATE FALSE
+//#define OPTION_ALIB FALSE
+//#define OPTION_PCIe_MID_INIT FALSE
+//#define OPTION_NB_MID_INIT FALSE
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//DA Customer table
+UINT8 AGESA_MEM_TABLE_LN[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x15, 0x14, 0x21, 0x11, 0x40, 0x2A, 0x34, 0x2D, 0x15),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x17, 0x16, 0x21, 0x11, 0x3F, 0x2A, 0x35, 0x2E, 0x17),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x77, 0x70, 0x77, 0x60, 0x95, 0x83, 0x8F, 0x90, 0x77),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x7D, 0x75, 0x7F, 0x6C, 0x9A, 0x8D, 0x94, 0x98, 0x7D),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x03, 0x04, 0x0F, 0x00, 0x2D, 0x1B, 0x23, 0x1C, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x05, 0x05, 0x0F, 0x00, 0x2E, 0x19, 0x24, 0x1C, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x0C, 0x0A, 0x0A, 0x0E, 0x0A, 0x0C, 0x0C, 0x0A, 0x0C),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x0A, 0x0C, 0x0E, 0x0A, 0x0C, 0x0A, 0x0C, 0x0E, 0x0A),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ // --------------------------------------------------------------------------------------------------------------------------------------------------
+
+ // MaxRdLatency
+ // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct0, BFMaxLatency, MTOverride, 0x0C),
+ // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct1, BFMaxLatency, MTOverride, 0x0C),
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableLN = sizeof (AGESA_MEM_TABLE_LN) / sizeof (AGESA_MEM_TABLE_LN[0]);
+
+/* ***************************************************************************
+ * Optional User code to be included into the AGESA build
+ * These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+// IN UINTN FcnData,
+// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+// )
+//{
+// /* platform code to read an SPD... */
+// return Status;
+//}
+
+
diff --git a/src/mainboard/amd/torpedo/cfg.c b/src/mainboard/amd/torpedo/cfg.c
new file mode 100755
index 0000000..809b7a3
--- /dev/null
+++ b/src/mainboard/amd/torpedo/cfg.c
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <string.h>
+#include "SbPlatform.h"
+#include "cfg.h"
+#include <console/console.h> /* printk */
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb900_cimx_config(AMDSBCFG *sb_config)
+{
+ if (!sb_config) {
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+ return;
+ }
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
+ memset(sb_config, 0, sizeof(AMDSBCFG));
+
+ /* static Build Parameters */
+ sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+ sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+ sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
+
+ /* Turn on CDROM and HDD Power */
+ sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED;
+
+ // header
+ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
+
+ // Build Parameters
+ sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option
+ sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option
+ sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option
+ sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option
+ sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option
+ sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option
+ sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level
+ sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level
+ sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level
+ sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level
+ sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level
+ sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level
+ sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level
+ sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level
+ sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level
+ // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired
+
+ //
+ // Common Function
+ //
+ sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option
+ sb_config->S3Resume = 0; // CIMx Internal Used
+ sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level
+ sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option
+ sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option
+ sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option
+ sb_config->S4Resume = 0; // CIMx Internal Used
+ sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option
+ sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option
+ sb_config->sdConfig = SB_SD_CONFIG; // External Option
+ sb_config->sdSpeed = SB_SD_SPEED; // Internal Option
+ sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option
+ sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option
+ sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option
+ sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option
+ sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option
+ sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level
+ sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option
+ sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option
+ sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option
+ sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option
+ sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option
+ sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option
+ sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option
+ sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option
+ sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option
+ sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option
+ sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option
+ sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option
+ sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option
+ sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option
+ sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level
+ // USB
+ sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option
+ // GEC
+ sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option
+ sb_config->IrConfig = SB_IR_CONTROLLER; // External Option
+ sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option
+ // Azalia
+ sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option
+ sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level
+ sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level
+ sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level
+ sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level
+ sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level
+ sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option
+ sb_config->HpetTimer = SB_HPET_TIMER; // External Option
+ sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option*
+ // Generic
+ sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option
+ // USB
+ sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option
+ sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
+ // sb_config->HpetMsiDis = 0; // Field Retired
+ // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired
+ // sb_config->PcibAutoClkCtr = 0; // Field Retired
+ sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level
+ sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level
+ sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level
+ sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level
+ sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option
+ sb_config->GppFoundGfxDev = 0; // CIMx Internal Used
+ sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option
+ sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option
+ sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option
+ sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option
+ sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option
+ sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
+ sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option
+ sb_config->PcieAER = INCHIP_PCIE_AER; // External Option
+ sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option
+ sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
+ sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option
+ sb_config->sdbEnable = 0; // CIMx Internal Used
+ sb_config->TempMMIO = NULL; // CIMx Internal Used
+ // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired
+ sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option
+ sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option
+ sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option
+ sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option
+ sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option
+ sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option
+ sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option
+ sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option
+ sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option
+ sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option
+ sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option
+ sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option
+ // sb_config->sdb = 0; // Field Retired
+ sb_config->GppGen2Strap = 0; // CIMx Internal Used
+ sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option
+ sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level
+ sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option
+ sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option
+ sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option
+ // sb_config->UmiLinkWidth = 0; // Field Retired
+ sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option
+ // sb_config->PcieRefClockOverclocking = 0; // Field Retired
+ sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option
+ sb_config->PwrFailShadow = 0x02; // Board Level
+ sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option
+ sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level
+ sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level
+
+ /* General */
+ sb_config->PciClks = SB_PCI_CLOCK_RESERVED;
+ sb_config->hwm.hwmEnable = 0x0;
+
+#ifndef __PRE_RAM__
+ /* ramstage cimx config here */
+ if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+ sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
+ }
+
+ //sb_config->
+#endif //!__PRE_RAM__
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
+}
+
+void SbPowerOnInit_Config(AMDSBCFG *sb_config)
+{
+ if (!sb_config) {
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+ return;
+ }
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
+ memset(sb_config, 0, sizeof(AMDSBCFG));
+
+ // Set the build parameters
+ sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired
+ sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level
+ sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option
+ sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option
+ // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired
+ sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option
+ sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option
+ sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level
+ sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level
+ sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level
+ sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level
+ sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option
+ sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option
+ sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option
+ sb_config->NbSbGen2 = NB_SB_GEN2; // External Option
+ sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option
+ sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
+ sb_config->sdbEnable = 0; // CIMx Internal Used
+ sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option
+
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
+}
+
+
diff --git a/src/mainboard/amd/torpedo/cfg.h b/src/mainboard/amd/torpedo/cfg.h
new file mode 100755
index 0000000..6565d6c
--- /dev/null
+++ b/src/mainboard/amd/torpedo/cfg.h
@@ -0,0 +1,1242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _SB900_CFG_H_
+#define _SB900_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @section BIOSSize BIOSSize
+ * @li <b>0</b> - 1M
+ * @li <b>1</b> - 2M
+ * @li <b>3</b> - 4M
+ * @li <b>7</b> - 8M
+ * In Hudson-2, default ROM size is 1M Bytes, if your platform
+ * ROM bigger then 1M you have to set the ROM size outside CIMx
+ * module and before AGESA module get call.
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE
+ * @li <b>1</b> - Legacy free enable
+ * @li <b>0</b> - Legacy free disable
+ */
+#ifndef SBCIMx_LEGACY_FREE
+ #define SBCIMx_LEGACY_FREE 0
+#endif
+
+/**
+ * @section SpiSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_SPEED
+ #define SBCIMX_SPI_SPEED 0
+#endif
+
+/**
+ * @section SpiFastSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_FASTSPEED
+ #define SBCIMX_SPI_FASTSPEED 0
+#endif
+
+/**
+ * @section SpiMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_MODE
+ #define SBCIMX_SPI_MODE 0
+#endif
+
+/**
+ * @section SpiBurstWrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_BURST_WRITE
+ #define SBCIMX_SPI_BURST_WRITE 0
+#endif
+
+/**
+ * @section INCHIP_EC_KBD INCHIP_EC_KBD
+ * @li <b>0</b> - Use SIO PS/2 function.
+ * @li <b>1</b> - Use EC PS/2 function.
+ */
+#ifndef INCHIP_EC_KBD
+ #define INCHIP_EC_KBD 0
+#endif
+
+/**
+ * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10
+ * @li <b>0</b> - EC controller NOT support Channel10
+ * @li <b>1</b> - EC controller support Channel10.
+ */
+#ifndef INCHIP_EC_CHANNEL10
+ #define INCHIP_EC_CHANNEL10 1
+#endif
+
+/**
+ * @section Smbus0BaseAddress
+ */
+// #ifndef SMBUS0_BASE_ADDRESS
+// #define SMBUS0_BASE_ADDRESS 0xB00
+// #endif
+
+/**
+ * @section Smbus1BaseAddress
+ */
+// #ifndef SMBUS1_BASE_ADDRESS
+// #define SMBUS1_BASE_ADDRESS 0xB21
+// #endif
+
+/**
+ * @section SioPmeBaseAddress
+ */
+// #ifndef SIO_PME_BASE_ADDRESS
+// #define SIO_PME_BASE_ADDRESS 0xE00
+// #endif
+
+/**
+ * @section WatchDogTimerBase
+ */
+// #ifndef WATCHDOG_TIMER_BASE_ADDRESS
+// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
+// #endif
+
+/**
+ * @section GecShadowRomBase
+ */
+#ifndef GEC_ROM_SHADOW_ADDRESS
+ #define GEC_ROM_SHADOW_ADDRESS 0xFED61000
+#endif
+
+/**
+ * @section SpiRomBaseAddress
+ */
+// #ifndef SPI_BASE_ADDRESS
+// #define SPI_BASE_ADDRESS 0xFEC10000
+// #endif
+
+/**
+ * @section AcpiPm1EvtBlkAddr
+ */
+// #ifndef PM1_EVT_BLK_ADDRESS
+// #define PM1_EVT_BLK_ADDRESS 0x400
+// #endif
+
+/**
+ * @section AcpiPm1CntBlkAddr
+ */
+// #ifndef PM1_CNT_BLK_ADDRESS
+// #define PM1_CNT_BLK_ADDRESS 0x404
+// #endif
+
+/**
+ * @section AcpiPmTmrBlkAddr
+ */
+// #ifndef PM1_TMR_BLK_ADDRESS
+// #define PM1_TMR_BLK_ADDRESS 0x408
+// #endif
+
+/**
+ * @section CpuControlBlkAddr
+ */
+// #ifndef CPU_CNT_BLK_ADDRESS
+// #define CPU_CNT_BLK_ADDRESS 0x410
+// #endif
+
+/**
+ * @section AcpiGpe0BlkAddr
+ */
+// #ifndef GPE0_BLK_ADDRESS
+// #define GPE0_BLK_ADDRESS 0x420
+// #endif
+
+/**
+ * @section SmiCmdPortAddr
+ */
+// #ifndef SMI_CMD_PORT
+// #define SMI_CMD_PORT 0xB0
+// #endif
+
+/**
+ * @section AcpiPmaCntBlkAddr
+ */
+// #ifndef ACPI_PMA_CNT_BLK_ADDRESS
+// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+// #endif
+
+/**
+ * @section SataController
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_SATA_CONTROLLER
+ #define INCHIP_SATA_CONTROLLER 1
+#endif
+
+/**
+ * @section SataIdeCombMdPriSecOpt
+ * @li <b>0</b> - Primary
+ * @li <b>1</b> - Secondary<TD></TD>
+ * Sata Controller set as primary or
+ * secondary while Combined Mode is enabled
+ */
+#ifndef SATA_COMBINE_MODE_CHANNEL
+ #define SATA_COMBINE_MODE_CHANNEL 0
+#endif
+
+/**
+ * @section SataSetMaxGen2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * SataController Set to Max Gen2 mode
+ */
+#ifndef SATA_MAX_GEN2_MODE
+ #define SATA_MAX_GEN2_MODE 0
+#endif
+
+/**
+ * @section SataIdeCombinedMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * Sata IDE Controller set to Combined Mode
+ */
+#ifndef SATA_COMBINE_MODE
+ #define SATA_COMBINE_MODE 0
+#endif
+
+#define SATA_CLK_RESERVED 9
+
+/**
+ * @section NbSbGen2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef NB_SB_GEN2
+ #define NB_SB_GEN2 1
+#endif
+
+/**
+ * @section SataInternal100Spread
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_SATA_INTERNAL_100_SPREAD
+ #define INCHIP_SATA_INTERNAL_100_SPREAD 0
+#endif
+
+/**
+ * @section Cg2Pll
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_CG2_PLL
+ #define INCHIP_CG2_PLL 0
+#endif
+
+
+
+
+/**
+ * @section SpreadSpectrum
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * Spread Spectrum function
+ */
+#define INCHIP_SPREAD_SPECTRUM 1
+
+/**
+ * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG
+ *
+ * - Usb Ohci1 Contoller is define at BIT0
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 18 Func0)
+ * - Usb Ehci1 Contoller is define at BIT1
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 18 Func2)
+ * - Usb Ohci2 Contoller is define at BIT2
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 19 Func0)
+ * - Usb Ehci2 Contoller is define at BIT3
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 19 Func2)
+ * - Usb Ohci3 Contoller is define at BIT4
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 22 Func0)
+ * - Usb Ehci3 Contoller is define at BIT5
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 22 Func2)
+ * - Usb Ohci4 Contoller is define at BIT6
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 20 Func5)
+ */
+#define INCHIP_USB_CINFIG 0x7F
+#define INCHIP_USB_OHCI1_CINFIG 0x01
+#define INCHIP_USB_OHCI2_CINFIG 0x01
+#if CONFIG_ONBOARD_USB30 == 1
+#define INCHIP_USB_OHCI3_CINFIG 0x00
+#else
+#define INCHIP_USB_OHCI3_CINFIG 0x01
+#endif
+#define INCHIP_USB_OHCI4_CINFIG 0x01
+#define INCHIP_USB_EHCI1_CINFIG 0x01
+#define INCHIP_USB_EHCI2_CINFIG 0x01
+#define INCHIP_USB_EHCI3_CINFIG 0x01
+
+/**
+ * @section INCHIP_SATA_MODE INCHIP_SATA_MODE
+ * @li <b>000</b> - Native IDE mode
+ * @li <b>001</b> - RAID mode
+ * @li <b>010</b> - AHCI mode
+ * @li <b>011</b> - Legacy IDE mode
+ * @li <b>100</b> - IDE->AHCI mode
+ * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
+ * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
+ */
+#define INCHIP_SATA_MODE 0
+
+/**
+ * @section INCHIP_IDE_MODE INCHIP_IDE_MODE
+ * @li <b>0</b> - Legacy IDE mode
+ * @li <b>1</b> - Native IDE mode<TD></TD>
+ * ** DO NOT ALLOW SATA & IDE use same mode **
+ */
+#define INCHIP_IDE_MODE 1
+
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+/**
+ * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
+ * @li <b>0</b> - Auto : Detect Azalia controller automatically.
+ * @li <b>1</b> - Diable : Disable Azalia controller.
+ * @li <b>2</b> - Enable : Enable Azalia controller.
+ */
+#define INCHIP_AZALIA_CONTROLLER 2
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+#define INCHIP_AZALIA_PIN_CONFIG 1
+
+/**
+ * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG
+ *
+ * SDIN0 is define at BIT0 & BIT1
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN1 is define at BIT2 & BIT3
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN2 is define at BIT4 & BIT5
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN3 is define at BIT6 & BIT7
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin
+ */
+#define AZALIA_PIN_CONFIG 0x2A
+
+/**
+ * @section AzaliaSnoop
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable *
+ */
+#define INCHIP_AZALIA_SNOOP 0x01
+
+/**
+ * @section NCHIP_GEC_CONTROLLER
+ * @li <b>0</b> - Enable *
+ * @li <b>1</b> - Disable
+ */
+#define INCHIP_GEC_CONTROLLER 0x00
+
+/**
+ * @section SB_HPET_TIMER SB_HPET_TIMER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_HPET_TIMER 1
+
+/**
+ * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_CONTROLLER 1
+
+/**
+ * @section GPP_LINK_CONFIG GPP_LINK_CONFIG
+ * @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ * @li <b>0001</b> - N/A
+ * @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ * @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ * @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ */
+#define GPP_LINK_CONFIG 4
+
+/**
+ * @section SB_GPP_PORT0 SB_GPP_PORT0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT0 1
+
+/**
+ * @section SB_GPP_PORT1 SB_GPP_PORT1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT1 1
+
+/**
+ * @section SB_GPP_PORT2 SB_GPP_PORT2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT2 1
+
+/**
+ * @section SB_GPP_PORT3 SB_GPP_PORT3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT3 1
+
+/**
+ * @section SB_IR_CONTROLLER
+ * @li <b>00 </b> - disable
+ * @li <b>01 </b> - Rx and Tx0
+ * @li <b>10 </b> - Rx and Tx1
+ * @li <b>11 </b> - Rx and both Tx0,Tx1
+ */
+#define SB_IR_CONTROLLER 3
+
+/**
+ * @section INCHIP_USB_PHY_POWER_DOWN
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_USB_PHY_POWER_DOWN 0
+
+/**
+ * @section INCHIP_NATIVE_PCIE_SUPPOORT
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_NATIVE_PCIE_SUPPOORT 1
+
+/**
+ * @section INCHIP_NB_SB_GEN2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_NB_SB_GEN2 1
+
+/**
+ * @section INCHIP_GPP_GEN2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_GEN2 1
+
+/**
+ * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1
+
+/**
+ * @section INCHIP_GEC_PHY_STATUS
+ * @li <b>0</b> - Gb PHY Mode *
+ * @li <b>1</b> - 100/10 PHY Mode
+ */
+#define INCHIP_GEC_PHY_STATUS 0
+
+/**
+ * @section INCHIP_GEC_POWER_POLICY
+ * @li <b>0</b> - S3/S5
+ * @li <b>1</b> - S5
+ * @li <b>2</b> - S3
+ * @li <b>3</b> - Never power down *
+ */
+#define INCHIP_GEC_POWER_POLICY 3
+
+/**
+ * @section INCHIP_GEC_DEBUGBUS
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GEC_DEBUGBUS 0
+
+/**
+ * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ * SataController Set to Max Gen2 mode
+ */
+#define SATA_MAX_GEN2_MODE 0
+
+/**
+ * @section INCHIP_SATA_AGGR_LINK_PM_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ * SataController Set to aggressive link PM capability
+ */
+#define INCHIP_SATA_AGGR_LINK_PM_CAP 0
+
+/**
+ * @section INCHIP_SATA_PORT_MULT_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ * SataController Set to Port Multiple capability
+ */
+#define INCHIP_SATA_PORT_MULT_CAP 1
+
+/**
+ * @section INCHIP_SATA_PSC_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+*/
+#define INCHIP_SATA_PSC_CAP 0
+
+/**
+ * @section INCHIP_SATA_SSC_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_SSC_CAP 0
+
+/**
+ * @section INCHIP_SATA_CLK_AUTO_OFF
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_CLK_AUTO_OFF 1
+
+/**
+ * @section INCHIP_SATA_FIS_BASE_SW
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_FIS_BASE_SW 1
+
+/**
+ * @section INCHIP_SATA_CCC_SUPPORT
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_CCC_SUPPORT 1
+
+/**
+ * @section INCHIP_SATA_MSI_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_MSI_CAP 1
+
+/**
+ * @section CIMXSB_SATA_TARGET_8DEVICE_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0
+
+/**
+ * @section SATA_DISABLE_GENERIC_MODE
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISABLE_GENERIC_MODE_CAP 0
+
+/**
+ * @section SATA_AHCI_ENCLOSURE_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_AHCI_ENCLOSURE_CAP 0
+
+/**
+ * @section SataForceRaid (RISD5 mode)
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_SATA_FORCE_RAID5 0
+
+/**
+ * @section SATA_GPIO_0_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_GPIO_0_CAP 0
+
+/**
+ * @section SATA_GPIO_1_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_GPIO_1_CAP 0
+
+/**
+ * @section SataPhyPllShutDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SATA_PHY_PLL_SHUTDOWN 1
+
+/**
+ * @section ImcEnableOverWrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IMC_ENABLE_OVER_WRITE 0
+
+/**
+ * @section UsbMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define USB_MSI 0
+
+/**
+ * @section HdAudioMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define HDAUDIO_MSI 0
+
+/**
+ * @section LpcMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define LPC_MSI 0
+
+/**
+ * @section PcibMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define PCIB_MSI 0
+
+/**
+ * @section AbMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define AB_MSI 0
+
+/**
+ * @section GecShadowRomBase
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define GEC_SHADOWROM_BASE 0xFED61000
+
+/**
+ * @section SataController
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SATA_CONTROLLER 1
+
+/**
+ * @section SataIdeCombMdPriSecOpt
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_IDE_COMBMD_PRISEC_OPT 0
+
+/**
+ * @section SataIdeCombinedMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_IDECOMBINED_MODE 0
+
+/**
+ * @section sdConfig
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_CONFIG 1
+
+/**
+ * @section sdSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_SPEED 1
+
+/**
+ * @section sdBitwidth
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_BITWIDTH 1
+
+/**
+ * @section SataDisUnusedIdePChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISUNUSED_IDE_P_CHANNEL 0
+
+/**
+ * @section SataDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISUNUSED_IDE_S_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdePChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IDE_DISUNUSED_IDE_P_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IDE_DISUNUSED_IDE_S_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+
+/**
+ * @section SataEspPort0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT0 0
+
+/**
+ * @section SataEspPort1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT1 0
+
+/**
+ * @section SataEspPort2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT2 0
+
+/**
+ * @section SataEspPort3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT3 0
+
+/**
+ * @section SataEspPort4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT4 0
+
+/**
+ * @section SataEspPort5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT5 0
+
+/**
+ * @section SataEspPort6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT6 0
+
+/**
+ * @section SataEspPort7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT7 0
+
+/**
+ * @section SataPortPower0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT0 0
+
+/**
+ * @section SataPortPower1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT1 0
+
+/**
+ * @section SataPortPower2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT2 0
+
+/**
+ * @section SataPortPower3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT3 0
+
+/**
+ * @section SataPortPower4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT4 0
+
+/**
+ * @section SataPortPower5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT5 0
+
+/**
+ * @section SataPortPower6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT6 0
+
+/**
+ * @section SataPortPower7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT7 0
+
+/**
+ * @section SataPortMd0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT0 3
+
+/**
+ * @section SataPortMd1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT1 3
+
+/**
+ * @section SataPortMd2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT2 3
+
+/**
+ * @section SataPortMd3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT3 3
+
+/**
+ * @section SataPortMd4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT4 0
+
+/**
+ * @section SataPortMd5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT5 0
+
+/**
+ * @section SataPortMd6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT6 0
+
+/**
+ * @section SataPortMd7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT7 0
+
+/**
+ * @section SataHotRemovelEnh0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT0 0
+
+/**
+ * @section SataHotRemovelEnh1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT1 0
+
+/**
+ * @section SataHotRemovelEnh2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT2 0
+
+/**
+ * @section SataHotRemovelEnh3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT3 0
+
+/**
+ * @section SataHotRemovelEnh4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT4 0
+
+/**
+ * @section SataHotRemovelEnh5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT5 0
+
+/**
+ * @section SataHotRemovelEnh6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT6 0
+
+/**
+ * @section SataHotRemovelEnh7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT7 0
+
+/**
+ * @section XhciSwitch
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#if CONFIG_ONBOARD_USB30 == 1
+ #define SB_XHCI_SWITCH 0
+#else
+#define SB_XHCI_SWITCH 1
+#endif
+
+/**
+ * @section FrontPanelDetected
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FRONT_PANEL_DETECTED 0
+
+/**
+ * @section AnyHT200MhzLink
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ANY_HT_200MHZ_LINK 0
+
+/**
+ * @section PcibClkStopOverride
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0
+
+/**
+ * @section GppLinkConfig
+ * @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ * @li <b>0001</b> - N/A
+ * @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ * @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ * @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ */
+#define INCHIP_GPP_LINK_CONFIG 4
+
+/**
+ * @section GppUnhidePorts
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_UNHIDE_PORTS 0
+
+/**
+ * @section GppPortAspm
+ * @li <b>01</b> - Disabled
+ * @li <b>01</b> - L0s
+ * @li <b>10</b> - L1
+ * @li <b>11</b> - L0s + L1
+ */
+#define INCHIP_GPP_PORT_ASPM 3
+
+/**
+ * @section GppLaneReversal
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_LANEREVERSAL 0
+
+/**
+ * @section AlinkPhyPllPowerDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1
+
+/**
+ * @section GppPhyPllPowerDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1
+
+/**
+ * @section GppDynamicPowerSaving
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1
+
+/**
+ * @section PcieAER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIE_AER 0
+
+/**
+ * @section PcieRAS
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIE_RAS 0
+
+/**
+ * @section GppHardwareDowngrade
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_HARDWARE_DOWNGRADE 0
+
+/**
+ * @section GppToggleReset
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_TOGGLE_RESET 0
+
+/**
+ * @section SbPcieOrderRule
+ * @li <b>00</b> - Disable
+ * @li <b>01</b> - Rule 1
+ * @li <b>10</b> - Rule 2
+ */
+#define INCHIP_SB_PCIE_ORDER_RULE 2
+
+/**
+ * @section AcDcMsg
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ACDC_MSG 0
+
+/**
+ * @section TimerTickTrack
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_TIMER_TICK_TRACK 1
+
+/**
+ * @section ClockInterruptTag
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_CLOCK_INTERRUPT_TAG 1
+
+/**
+ * @section OhciTrafficHanding
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_OHCI_TRAFFIC_HANDING 0
+
+/**
+ * @section EhciTrafficHanding
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_EHCI_TRAFFIC_HANDING 0
+
+/**
+ * @section FusionMsgCMultiCore
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FUSION_MSGC_MULTICORE 0
+
+/**
+ * @section FusionMsgCStage
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FUSION_MSGC_STAGE 0
+
+/**
+ * @section ALinkClkGateOff
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_CLK_GATE_OFF 0
+
+/**
+ * @section BLinkClkGateOff
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_BLINK_CLK_GATE_OFF 0
+
+/**
+ * @section SlowSpeedABlinkClock
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0
+
+/**
+ * @section AbClockGating
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_AB_CLOCK_GATING 1
+
+/**
+ * @section GppClockGating
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_CLOCK_GATING 1
+
+/**
+ * @section L1TimerOverwrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_L1_TIMER_OVERWRITE 0
+
+/**
+ * @section UmiDynamicSpeedChange
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0
+
+/**
+ * @section SbAlinkGppTxDriverStrength
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0
+
+/**
+ * @section StressResetMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_STRESS_RESET_MODE 0
+
+#ifndef SB_PCI_CLOCK_RESERVED
+ #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F
+#endif
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb900_cimx_config(AMDSBCFG *sb_cfg);
+void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func Southbridge CIMx Function ID.
+ * @param[in] data Southbridge Input Data.
+ * @param[in] sb_cfg Southbridge configuration structure pointer.
+ *
+ */
+u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif
diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h
new file mode 100755
index 0000000..a252705
--- /dev/null
+++ b/src/mainboard/amd/torpedo/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/amd/torpedo/cmos.layout b/src/mainboard/amd/torpedo/cmos.layout
new file mode 100755
index 0000000..8315401
--- /dev/null
+++ b/src/mainboard/amd/torpedo/cmos.layout
@@ -0,0 +1,118 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb
new file mode 100755
index 0000000..2b6d896
--- /dev/null
+++ b/src/mainboard/amd/torpedo/devicetree.cb
@@ -0,0 +1,90 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family12/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/agesa/family12
+ device lapic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ subsystemid 0x1022 0x1705 inherit
+ chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family12 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics Bridge
+ device pci 1.1 on end # Audio Controller
+ device pci 2.0 on end # Root Port
+ device pci 3.0 on end # Root Port
+ device pci 4.0 on end # PCIE P2P bridge
+ device pci 5.0 on end # PCIE P2P bridge
+ device pci 6.0 on end # PCIE P2P bridge
+ device pci 7.0 on end # PCIE P2P bridge
+ device pci 8.0 on end # NB/SB Link P2P bridge
+ end # agesa northbridge
+ chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
+ device pci 10.0 on end # USB XHCI
+ device pci 10.1 on end # USB XHCI
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE
+ device pci 14.2 on end # HDA
+ device pci 14.3 on # LPC
+ chip superio/smsc/kbc1100
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ end # kbc1100
+ end #LPC
+ device pci 14.4 on end # PCI bridge
+ device pci 14.5 on end # USB 2
+ device pci 14.6 on end # Ethernet Controller
+ device pci 14.7 on end # SD Flash Controller
+ device pci 15.0 on end # PCIe PortA
+ device pci 15.1 on end # PCIe PortB
+ device pci 15.2 on end # PCIe PortC
+ device pci 15.3 on end # PCIe PortD
+ register "gpp_configuration" = "4" #1:1:1:1
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end #southbridge/amd/cimx/sb900
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+ end #pci_domain
+end #northbridge/amd/agesa/family12/root_complex
+
diff --git a/src/mainboard/amd/torpedo/dimmSpd.c b/src/mainboard/amd/torpedo/dimmSpd.c
new file mode 100755
index 0000000..55fb2c3
--- /dev/null
+++ b/src/mainboard/amd/torpedo/dimmSpd.c
@@ -0,0 +1,241 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define SMBUS_BASE_ADDR 0xB00
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct _DIMM_INFO_SMBUS{
+ UINT8 SocketId;
+ UINT8 MemChannelId;
+ UINT8 DimmId;
+ UINT8 SmbusAddress;
+} DIMM_INFO_SMBUS;
+/*
+* SPD address table - porting required
+*/
+STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] =
+{
+ /* Socket, Channel, Dimm, Smbus */
+ {0, 0, 0, 0xA0},
+ {0, 1, 0, 0xA2}
+};
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+STATIC
+VOID
+WritePmReg (
+ IN UINT8 Reg,
+ IN UINT8 Data
+ )
+{
+ __outbyte (0xCD6, Reg);
+ __outbyte (0xCD7, Data);
+}
+STATIC
+VOID
+SetupFch (
+ IN UINT16
+ IN IoBase
+ )
+{
+ WritePmReg (0x2D, IoBase >> 8);
+ WritePmReg (0x2C, IoBase | 1);
+ WritePmReg (0x29, 0x80);
+ WritePmReg (0x28, 0x61);
+ /* set SMBus clock to 400 KHz */
+ __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
+}
+
+/*
+ *
+ * ReadSmbusByteData - read a single SPD byte from any offset
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByteData (
+ IN UINT16 Iobase,
+ IN UINT8 Address,
+ OUT UINT8 *Buffer,
+ IN UINTN Offset
+ )
+{
+ UINTN Status;
+ UINT64 Limit;
+
+ Address |= 1; // set read bit
+
+ __outbyte (Iobase + 0, 0xFF); // clear error status
+ __outbyte (Iobase + 1, 0x1F); // clear error status
+ __outbyte (Iobase + 3, Offset); // offset in eeprom
+ __outbyte (Iobase + 4, Address); // slave address and read bit
+ __outbyte (Iobase + 2, 0x48); // read byte command
+
+ /* time limit to avoid hanging for unexpected error status (should never happen) */
+ Limit = __rdtsc () + 2000000000 / 10;
+ for (;;) {
+ Status = __inbyte (Iobase);
+ if (__rdtsc () > Limit) break;
+ if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ Buffer [0] = __inbyte (Iobase + 5);
+ if (Status == 2) Status = 0; // check for done with no errors
+ return Status;
+ }
+
+/*
+ *
+ * ReadSmbusByte - read a single SPD byte from the default offset
+ * this function is faster function readSmbusByteData
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByte (
+ IN UINT16 Iobase,
+ IN UINT8 Address,
+ OUT UINT8 *Buffer
+ )
+{
+ UINTN Status;
+ UINT64 Limit;
+
+ __outbyte (Iobase + 0, 0xFF); // clear error status
+ __outbyte (Iobase + 2, 0x44); // read command
+
+ // time limit to avoid hanging for unexpected error status
+ Limit = __rdtsc () + 2000000000 / 10;
+ for (;;) {
+ Status = __inbyte (Iobase);
+ if (__rdtsc () > Limit) break;
+ if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ Buffer [0] = __inbyte (Iobase + 5);
+ if (Status == 2) Status = 0; // check for done with no errors
+ return Status;
+}
+
+/*
+ *
+ * ReadSpd - Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Optimization relies on autoincrement to avoid
+ * sending offset for every byte.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSpd (
+ IN UINT16 IoBase,
+ IN UINT8 SmbusSlaveAddress,
+ OUT UINT8 *Buffer,
+ IN UINTN Count
+ )
+{
+ UINTN Index, Status;
+
+ /* read the first byte using offset zero */
+ Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
+ if (Status) return Status;
+
+ /* read the remaining bytes using auto-increment for speed */
+ for (Index = 1; Index < Count; Index++){
+ Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
+ if (Status) return Status;
+ }
+ return 0;
+}
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+ IN UINT32 Func,
+ IN UINT32 Data,
+ IN OUT AGESA_READ_SPD_PARAMS *SpdData
+ )
+{
+ UINT8 SmBusAddress = 0;
+ UINTN Index;
+ UINTN MaxSocket = DIMENSION (SpdAddrLookup);
+ for (Index = 0; Index < MaxSocket; Index ++){
+ if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) &&
+ (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) &&
+ (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) {
+ SmBusAddress = SpdAddrLookup[Index].SmbusAddress;
+ break;
+ }
+ }
+
+
+ if (SmBusAddress == 0) return AGESA_ERROR;
+ SetupFch (SMBUS_BASE_ADDR);
+ return ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 128);
+}
diff --git a/src/mainboard/amd/torpedo/dimmSpd.h b/src/mainboard/amd/torpedo/dimmSpd.h
new file mode 100755
index 0000000..069c34a
--- /dev/null
+++ b/src/mainboard/amd/torpedo/dimmSpd.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+ IN UINT32 Func,
+ IN UINT32 Data,
+ IN OUT AGESA_READ_SPD_PARAMS *SpdData
+ );
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl
new file mode 100755
index 0000000..2355e46
--- /dev/null
+++ b/src/mainboard/amd/torpedo/dsdt.asl
@@ -0,0 +1,1142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "TORPEDO ", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* Some global data */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(GPIC, 0x1) /* Assume PIC */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ CPU0, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
+ Processor(
+ CPU1, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0000, /* PBLK system I/O address !hardcoded! */
+ 0x00 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
+ Processor(
+ CPU2, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0000, /* PBLK system I/O address !hardcoded! */
+ 0x00 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
+ Processor(
+ CPU3, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0000, /* PBLK system I/O address !hardcoded! */
+ 0x00 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
+ } /* End _PR scope */
+
+ /* PIC IRQ mapping registers, C00h-C01h. */
+ OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002)
+ Field(PIRQ, ByteAcc, NoLock, Preserve) {
+ PIDX, 0x00000008,
+ PDAT, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) {
+ PIRA, 0x00000008, /* Index 0 */
+ PIRB, 0x00000008, /* Index 1 */
+ PIRC, 0x00000008, /* Index 2 */
+ PIRD, 0x00000008, /* Index 3 */
+ PIRE, 0x00000008, /* Index 4 */
+ PIRF, 0x00000008, /* Index 5 */
+ PIRG, 0x00000008, /* Index 6 */
+ PIRH, 0x00000008, /* Index 7 */
+ Offset(0x10),
+ PIRS, 0x00000008,
+ Offset(0x13),
+ HDAD, 0x00000008,
+ , 0x00000008,
+ GEC, 0x00000008,
+ Offset(0x30),
+ USB1, 0x00000008,
+ USB2, 0x00000008,
+ USB3, 0x00000008,
+ USB4, 0x00000008,
+ USB5, 0x00000008,
+ USB6, 0x00000008,
+ USB7, 0x00000008,
+ Offset(0x40),
+ IDE, 0x00000008,
+ SATA, 0x00000008,
+ Offset(0x50),
+ GPP0, 0x00000008,
+ GPP1, 0x00000008,
+ GPP2, 0x00000008,
+ GPP3, 0x00000008
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers, TODO:PMIO is quite different in SB900. */
+ OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PMRG, ByteAcc, NoLock, Preserve) {
+ PMRI, 0x00000008,
+ PMRD, 0x00000008,
+ }
+ IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) {
+ Offset(0x24),
+ MMSO,32,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x50),
+ HPAD,32,
+ Offset(0x60),
+ P1EB,16,
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xC8),
+ ,2,
+ SPRE,1,
+ TPDE,1,
+ Offset(0xF0),
+ ,3,
+ RSTU,1
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1E0, SystemIO, P1EB, 0x04)
+ Field(P1E0, ByteAcc, NoLock, Preserve) {
+ ,14,
+ PEWS,1,
+ WSTA,1,
+ ,14,
+ PEWD,1
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ Scope(\_SB) {
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ /* Debug Port registers, 80h. */
+ OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001)
+ Field(DBBG, ByteAcc, NoLock, Preserve) {
+ DBG8, 0x00000008,
+ }
+
+ Method(_PIC, 1) {
+ Store(Arg0, GPIC)
+ If (GPIC) {
+ Store(0xAA, \_SB.DBG8)
+ \_SB.DSPI()
+ } else {
+ Store(0xAC, \_SB.DBG8)
+ }
+ }
+
+ Method(DSPI, 0) {
+ \_SB.GRUA(0x1F)
+ \_SB.GRUB(0x1F)
+ \_SB.GRUC(0x1F)
+ \_SB.GRUD(0x1F)
+ Store(0x1F, PIRE)
+ Store(0x1F, PIRF)
+ Store(0x1F, PIRG)
+ Store(0x1F, PIRH)
+ }
+
+ Method(GRUA, 1) {
+ Store(Arg0, PIRA)
+ Store(Arg0, HDAD)
+ Store(Arg0, GEC)
+ Store(Arg0, GPP0)
+ Store(Arg0, GPP0)
+ }
+
+ Method(GRUB, 1) {
+ Store(Arg0, PIRB)
+ Store(Arg0, USB2)
+ Store(Arg0, USB4)
+ Store(Arg0, USB6)
+ Store(Arg0, GPP1)
+ Store(Arg0, IDE)
+ }
+
+ Method(GRUC, 1) {
+ Store(Arg0, PIRC)
+ Store(Arg0, USB1)
+ Store(Arg0, USB3)
+ Store(Arg0, USB5)
+ Store(Arg0, USB7)
+ Store(Arg0, GPP2)
+ }
+
+ Method(GRUD, 1) {
+ Store(Arg0, PIRD)
+ Store(Arg0, SATA)
+ Store(Arg0, GPP3)
+ }
+
+ Name(IRQB, ResourceTemplate() {
+ IRQ(Level, ActiveLow, Shared) {
+ 15
+ }})
+
+ Name(IRQP, ResourceTemplate() {
+ IRQ(Level, ActiveLow, Shared) {
+ 3, 4, 5, 7, 10, 11, 12, 14, 15
+ }})
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+ Method(_STA, 0) {
+ if (PIRA) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ \_SB.GRUA(0x1F)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ \_SB.GRUA(Local0)
+ }
+ }
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+ Method(_STA, 0) {
+ if (PIRB) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ \_SB.GRUB(0x1F)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ \_SB.GRUB(Local0)
+ }
+ }
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+ Method(_STA, 0) {
+ if (PIRC) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ \_SB.GRUC(0x1F)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ \_SB.GRUC(Local0)
+ }
+ }
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+ Method(_STA, 0) {
+ if (PIRD) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ \_SB.GRUD(0x1F)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ \_SB.GRUD(Local0)
+ }
+ }
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+ Method(_STA, 0) {
+ if (PIRE) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ Store(0x1F, PIRE)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ Store(Local0, PIRE)
+ }
+ }
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+ Method(_STA, 0) {
+ if (PIRF) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ Store(0x1F, PIRF)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ Store(Local0, PIRF)
+ }
+ }
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+ Method(_STA, 0) {
+ if (PIRG) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ Store(0x1F, PIRG)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRG, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ Store(Local0, PIRG)
+ }
+ }
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+ Method(_STA, 0) {
+ if (PIRH) {
+ Return(0x0B)
+ } else {
+ Return(0x09)
+ }
+ }
+ Method(_DIS ,0) {
+ Store(0x1F, PIRH)
+ }
+ Method(_PRS ,0) {
+ Return(IRQP)
+ }
+ Method(_CRS ,0) {
+ CreateWordField(IRQB, 1, IRQN)
+ ShiftLeft(1, PIRH, IRQN)
+ Return(IRQB)
+ }
+ Method(_SRS, 1) {
+ CreateWordField(Arg0, 1, IRQM)
+ FindSetRightBit(IRQM, Local0)
+ Decrement(Local0)
+ Store(Local0, PIRH)
+ }
+ }
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PEWS, PEWS)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ } /* End Scope GPE */
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+ Method(_PRT,0) {
+ If(GPIC){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Method(_STA,0) {
+ Return(0x0F)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* The external GFX bridge */
+ Device(PBR3) {
+ Name(_ADR, 0x00030000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS3) } /* APIC mode */
+ Return (PS3) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR3 */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+ Device(PE20) {
+ Name(_ADR, 0x00150000)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APE0) } /* APIC mode */
+ Return (PE0) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE20 */
+ Device(PE21) {
+ Name(_ADR, 0x00150001)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APE1) } /* APIC mode */
+ Return (PE1) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE21 */
+ Device(PE22) {
+ Name(_ADR, 0x00150002)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APE2) } /* APIC mode */
+ Return (APE2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE22 */
+ Device(PE23) {
+ Name(_ADR, 0x00150003)
+ Method(_PRT,0) {
+ If(GPIC){ Return(APE3) } /* APIC mode */
+ Return (PE3) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE23 */
+
+ /* Describe the Southbridge devices */
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ }
+ } /* end AZHD */
+
+ Device(GEC) {
+ Name(_ADR, 0x00140006)
+ } /* end GEC */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/usb.asl"
+ } /* end UOH1 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130000)
+ #include "acpi/usb.asl"
+ } /* end UOH3 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00160000)
+ #include "acpi/usb.asl"
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00140005)
+ #include "acpi/usb.asl"
+ } /* end UEH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00120002)
+ #include "acpi/usb.asl"
+ } /* end UOH2 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130002)
+ #include "acpi/usb.asl"
+ } /* end UOH4 */
+
+ Device(UOH6) {
+ Name(_ADR, 0x00160002)
+ #include "acpi/usb.asl"
+ } /* end UOH5 */
+
+ Device(XHC0) {
+ Name(_ADR, 0x00100000)
+ #include "acpi/usb.asl"
+ } /* end XHC0 */
+
+ Device(XHC1) {
+ Name(_ADR, 0x00100001)
+ #include "acpi/usb.asl"
+ } /* end XHC1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+ Device (PS2M) {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ }
+
+ Device (PS2K) {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ } /* end LIBR */
+
+ Device(STCR) {
+ Name(_ADR, 0x00110000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
new file mode 100755
index 0000000..5701dab
--- /dev/null
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+//#include "../../../southbridge/amd/sb900/sb900.h"
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of sb900. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
+#define ACPI_PM2_CNT_BLK (pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (pm_base + 0x08) /* 4 bytes */
+#define ACPI_GPE0_BLK (pm_base + 0x20) /* 8 bytes */
+#define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ pm_base &= 0xFFFF;
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "AMD ", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (u32) facs;
+ fadt->dsdt = (u32) dsdt;
+ /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+ pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+ pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+ pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+ pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+ pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+ pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+ pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
+ pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+
+ pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
+ pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+
+ pm_iowrite(0x6E, ACPI_PM2_CNT_BLK & 0xFF);
+ pm_iowrite(0x6F, ACPI_PM2_CNT_BLK >> 8);
+
+ pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK;
+ fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+ fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
+ fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
+ fadt->flags = 0x0001c1a5;/* 0x25; */
+
+ fadt->res2 = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32) facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32) dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
new file mode 100755
index 0000000..436f6a8
--- /dev/null
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam12.h>
+#include "agesawrapper.h"
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_isa;
+u8 bus_sb900[3];
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+ 0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sb900;
+
+//KZ [092110]extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+
+
+
+void get_bus_conf(void)
+{
+ u32 status;
+
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+
+ get_bus_conf_done = 1;
+
+ printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+/*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
+
+ sbdn_sb900 = 0;
+
+ for (i = 0; i < 3; i++) {
+ bus_sb900[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+
+ bus_type[0] = 1; /* pci */
+
+// bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
+
+ /* sb900 */
+ dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4));
+
+
+
+ if (dev) {
+ bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sb900[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ for (i = 0; i < 4; i++) {
+ dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, i));
+ if (dev) {
+ bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ }
+ for (j = bus_sb900[2]; j < bus_isa; j++)
+ bus_type[j] = 1;
+
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+
+ sb_Late_Post();
+ printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+}
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
new file mode 100755
index 0000000..14dcd2c
--- /dev/null
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -0,0 +1,482 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "Filecode.h"
+#include "Hudson-2.h"
+#include "AmdSbLib.h"
+#include "gpio.h"
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01 1
+#endif
+
+#ifndef SB_GPIO_REG07
+#define SB_GPIO_REG07 7
+#endif
+
+#ifndef SB_GPIO_REG25
+#define SB_GPIO_REG25 25
+#endif
+
+#ifndef SB_GPIO_REG26
+#define SB_GPIO_REG26 26
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27 27
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ void gpioEarlyInit (void);
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+void
+gpioEarlyInit(
+ void
+ )
+{
+ u8 Flags;
+ u8 Data8 = 0;
+ u8 StripInfo = 0;
+ u8 BoardType = 1;
+ u8 RegIndex8 = 0;
+ u8 boardRevC = 0x2;
+ u16 Data16 = 0;
+ u32 Index = 0;
+ u32 AcpiMmioAddr = 0;
+ u32 GpioMmioAddr = 0;
+ u32 IoMuxMmioAddr = 0;
+ u32 MiscMmioAddr = 0;
+ u32 SmiMmioAddr = 0;
+ u32 andMask32 = 0;
+
+ // Enable HUDSON MMIO Base (AcpiMmioAddr)
+ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+ Data8 |= BIT0;
+ WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+ // Get HUDSON MMIO Base (AcpiMmioAddr)
+ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
+ Data16 = Data8 << 8;
+ ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
+ Data16 |= Data8;
+ AcpiMmioAddr = (u32)Data16 << 16;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
+ MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
+ Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
+ if ((Data8 & BIT4) == 0) {
+ BoardType = 0; // external clock board
+ }
+ Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
+ StripInfo = (Data8 & BIT7) >> 7;
+ Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
+ StripInfo |= (Data8 & BIT7) >> 6;
+ if (StripInfo < boardRevC) { // for old board. Rev B
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
+ }
+ for (Index = 0; Index < MAX_GPIO_NO; Index++) {
+ if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
+ if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
+ // Configure multi-funtion
+ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
+ }
+ // Configure GPIO
+ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
+ Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
+ Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
+ }
+ if (Index == GPIO_65) {
+ if ( BoardType == 0 ) {
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
+ }
+ }
+ }
+ // Configure GEVENT
+ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
+ SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
+
+ andMask32 = ~(1 << (Index - GEVENT_00));
+
+ //EventEnable: 0-Disable, 1-Enable
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
+
+ //SciTrig: 0-Falling Edge, 1-Rising Edge
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
+
+ //SciLevl: 0-Edge trigger, 1-Level Trigger
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
+
+ //SmiSciEn: 0-Not send SMI, 1-Send SMI
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
+
+ //SciS0En: 0-Disable, 1-Enable
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
+
+ //SciMap: 00000b ~ 11111b
+ RegIndex8=(u8)((Index - GEVENT_00) >> 2);
+ Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
+
+ //SmiTrig: 0-Active Low, 1-Active High
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
+
+ //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
+ RegIndex8=(u8)((Index - GEVENT_00) >> 4);
+ Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
+ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
+ }
+ }
+
+ //
+ // config MXM
+ // GPIO9: Input for MXM_PRESENT2#
+ // GPIO10: Input for MXM_PRESENT1#
+ // GPIO28: Input for MXM_PWRGD
+ // GPIO35: Output for MXM Reset
+ // GPIO45: Output for MXM Power Enable, active HIGH
+ // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
+ // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
+ //
+ // set INTE#/GPIO32 as GPO for PCIE_SW
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
+
+ // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
+
+ // set AD9/GPIO9 as GPI for MXM_PRESENT2#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
+
+ // set AD10/GPIO10 as GPI for MXM_PRESENT1#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
+
+ // set GNT1#/GPIO44 as GPO for MXM Reset
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
+
+ // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
+
+ // set AD28/GPIO28 as GPI for MXM_PWRGD
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
+
+ // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
+
+ //
+ // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
+ //
+ //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
+ //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
+
+ // check if there any GFX card
+ Flags = 0;
+ // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
+ // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
+ ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
+ if (!(Data8 & BIT7))
+ {
+ //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
+ ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
+ if (!(Data8 & BIT7))
+ {
+ Flags = 1;
+ }
+ }
+ if ( Flags )
+ {
+ // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
+ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
+
+ // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
+
+ //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+ SbStall (10000);
+
+ // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
+
+ //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+ // WAIT POWER READY: GPIO28 (MXM_PWRGD)
+ //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
+ ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+ while (!(Data8 && BIT7))
+ {
+ ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+ }
+ // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
+ // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
+ }
+ else
+ {
+ // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
+
+ //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+ SbStall (10000);
+
+ // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
+ }
+
+ //
+ // APU GPP0: On board LAN
+ // GPIO25: PCIE_RST#_LAN, LOW active
+ // GPIO63: LAN_CLKREQ#
+ // GPIO197: LOM_POWER, HIGH Active
+ // Clock: GPP_CLK3
+ //
+ // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+
+ // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
+
+ //
+ // APU GPP1: WUSB
+ // GPIO1: MPCIE_RST2#, LOW active
+ // GPIO13: WU_DISABLE#, LOW active
+ // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
+ //
+ // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Setup AD01/GPIO01 as GPO for MPCIE_RST2#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
+// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
+// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ //
+ // APU GPP2: WWAN
+ // GPIO0: MPCIE_RST1#, LOW active
+ // GPIO14: WP_DISABLE#, LOW active
+ // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
+ //
+ // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Set AD00/GPIO00 as GPO for MPCIE_RST1#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
+ RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
+// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
+// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
+
+ //
+ // APU GPP3: 1394
+ // GPIO59: Power control, HIGH active
+ // GPIO27: PCIE_RST#_1394, LOW active
+ // GPIO41: CLKREQ#
+ // Clock: GPP_CLK8
+ //
+ // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
+// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+
+ // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
+
+ // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
+ // To fix glitch issue
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
+ //
+ // Enable/Disable OnBoard LAN
+ //
+ if (!CONFIG_ONBOARD_LAN)
+ { // 1 - DISABLED
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
+ }
+// else
+// { // 0 - AUTO
+// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
+// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
+// }
+
+
+ //
+ // Enable/Disable 1394
+ //
+ if (!CONFIG_ONBOARD_1394)
+ { // 1 - DISABLED
+// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
+ RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
+// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
+ }
+// else
+// { // 0 - AUTO
+// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
+// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
+//
+// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
+// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
+// }
+
+//
+// external USB 3.0 control:
+// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
+// GPIO26: PCIE_RST#_USB3.0
+// GPIO46: PCIE_USB30_CLKREQ#
+// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
+// Clock: GPP_CLK7
+// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
+// disable Onboard NEC USB3.0 controller
+ if (!CONFIG_ONBOARD_USB30) {
+ RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
+ RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
+ RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+ }
+// }
+
+//
+// BlueTooth control: BT_ON
+// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
+// GPIO07: BT_ON, 0 - OFF, 1 - ON
+//
+if (!CONFIG_ONBOARD_BLUETOOTH) {
+//- if (SystemConfiguration.amdBlueTooth == 1) {
+ RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
+//- }
+}
+
+//
+// WebCam control:
+// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
+// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
+//
+if (!CONFIG_ONBOARD_WEBCAM) {
+//- if (SystemConfiguration.amdWebCam == 1) {
+ RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
+//- }
+}
+
+//
+// Travis enable:
+// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
+// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
+//
+if (!CONFIG_ONBOARD_TRAVIS) {
+//- if (SystemConfiguration.amdTravisCtrl == 0) {
+ RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
+//- }
+}
+
+//
+// Disable Light Sensor if needed
+//
+if (CONFIG_ONBOARD_LIGHTSENSOR) {
+//- if (SystemConfiguration.amdLightSensor == 1) {
+ RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
+//- }
+}
+
+}
+
+
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
new file mode 100755
index 0000000..159394e
--- /dev/null
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -0,0 +1,2329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include <stdint.h>
+#include <cbtypes.h>
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define Mmio_Address( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+
+#define Mmio32_Ptr( BaseAddr, Register ) \
+ ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) )
+
+#define Mmio32_G( BaseAddr, Register ) \
+ *Mmio32_Ptr( BaseAddr, Register )
+
+#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \
+ Mmio32_G( BaseAddr, Register ) = \
+ (u32) ( \
+ ( Mmio32_G( BaseAddr, Register ) & \
+ (u32)(AndData) \
+ ) | \
+ (u32)(OrData) \
+ )
+
+#define Mmio8_Ptr( BaseAddr, Register ) \
+ ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) )
+
+#define Mmio8_G( BaseAddr, Register ) \
+ *Mmio8_Ptr( BaseAddr, Register )
+
+#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \
+ Mmio8_G( BaseAddr, Register ) = \
+ (u8) ( \
+ ( Mmio8_G( BaseAddr, Register ) & \
+ (u8)(AndData) \
+ ) | \
+ (u8)(OrData) \
+ )
+
+#define SMIREG_EVENT_ENABLE 0x04
+#define SMIREG_SCITRIG 0x08
+#define SMIREG_SCILEVEL 0x0C
+#define SMIREG_SMISCIEN 0x14
+#define SMIREG_SCIS0EN 0x20
+#define SMIREG_SCIMAP0 0x40
+#define SMIREG_SCIMAP1 0x44
+#define SMIREG_SCIMAP2 0x48
+#define SMIREG_SCIMAP3 0x4C
+#define SMIREG_SCIMAP4 0x50
+#define SMIREG_SCIMAP5 0x54
+#define SMIREG_SCIMAP6 0x58
+#define SMIREG_SCIMAP7 0x5C
+#define SMIREG_SCIMAP8 0x60
+#define SMIREG_SCIMAP9 0x64
+#define SMIREG_SCIMAP10 0x68
+#define SMIREG_SCIMAP11 0x6C
+#define SMIREG_SCIMAP12 0x70
+#define SMIREG_SCIMAP13 0x74
+#define SMIREG_SCIMAP14 0x78
+#define SMIREG_SCIMAP15 0x7C
+#define SMIREG_SMITRIG 0x98
+#define SMIREG_SMICONTROL0 0xA0
+#define SMIREG_SMICONTROL1 0xA4
+
+#define FUNCTION0 0
+#define FUNCTION1 1
+#define FUNCTION2 2
+#define FUNCTION3 3
+#define NonGpio 0x80 // BIT7
+
+// S0-domain General Purpose I/O: GPIO 00~67
+#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED
+#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT
+#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT
+#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED
+#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF
+#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level
+#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED
+#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED
+#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702
+#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711
+#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703
+#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default
+#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted.
+#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
+#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
+#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
+ // 1:BATTERY IS FINE(DEFAULT)
+ // 0:BATTERY IS LOW
+#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
+#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default
+#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high
+#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high
+#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high
+#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT
+#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT
+#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0
+#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1
+ // 00 - REVA
+ // 01 - REVB
+ // 10 - REVC
+ // 11 - REVD
+#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO
+#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active.
+ // 0:USB3.0 I/F in Express CARD
+ // 1:PCIE I/F in Express CARD detection
+#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF
+#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH#
+#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC
+#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED
+#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted.
+#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ#
+#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ#
+#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK
+#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE
+#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
+#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ#
+#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA
+#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ
+#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1
+#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V
+#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1
+#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT
+#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE
+#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE
+#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE)
+ // 1:ENABLE; 0:DISABLE
+ // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10
+#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN
+#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER
+#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER
+#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE
+#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ#
+#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700
+#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711
+#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ#
+#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703
+#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM
+#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default
+#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT#
+#define GPIO_68_SELECT FUNCTION0+NonGpio
+#define GPIO_69_SELECT FUNCTION0+NonGpio
+#define GPIO_70_SELECT FUNCTION0+NonGpio
+#define GPIO_71_SELECT FUNCTION0+NonGpio
+#define GPIO_72_SELECT FUNCTION0+NonGpio
+#define GPIO_73_SELECT FUNCTION0+NonGpio
+#define GPIO_74_SELECT FUNCTION0+NonGpio
+#define GPIO_75_SELECT FUNCTION0+NonGpio
+#define GPIO_76_SELECT FUNCTION0+NonGpio
+#define GPIO_77_SELECT FUNCTION0+NonGpio
+#define GPIO_78_SELECT FUNCTION0+NonGpio
+#define GPIO_79_SELECT FUNCTION0+NonGpio
+#define GPIO_80_SELECT FUNCTION0+NonGpio
+#define GPIO_81_SELECT FUNCTION0+NonGpio
+#define GPIO_82_SELECT FUNCTION0+NonGpio
+#define GPIO_83_SELECT FUNCTION0+NonGpio
+#define GPIO_84_SELECT FUNCTION0+NonGpio
+#define GPIO_85_SELECT FUNCTION0+NonGpio
+#define GPIO_86_SELECT FUNCTION0+NonGpio
+#define GPIO_87_SELECT FUNCTION0+NonGpio
+#define GPIO_88_SELECT FUNCTION0+NonGpio
+#define GPIO_89_SELECT FUNCTION0+NonGpio
+#define GPIO_90_SELECT FUNCTION0+NonGpio
+#define GPIO_91_SELECT FUNCTION0+NonGpio
+#define GPIO_92_SELECT FUNCTION0+NonGpio
+#define GPIO_93_SELECT FUNCTION0+NonGpio
+#define GPIO_94_SELECT FUNCTION0+NonGpio
+#define GPIO_95_SELECT FUNCTION0+NonGpio
+// GEVENT 00~23 are mapped to GPIO 96~119
+#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0#
+#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1#
+#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP
+#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI#
+#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT#
+#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active
+#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
+ // there is a confliction to IR function when this pin is as a GEVENT.
+#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
+ // special pin difination for SB900 VGA OUTPUT, high active,
+ // VGA power for Hudson-M2 will be down when it was asserted.
+#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active
+#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio)
+#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2
+#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0
+#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
+ // [option for SPI_TPM_CS# in Hudson-M2 A12)]
+#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
+ // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
+#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
+ // plus judge GPIO40 and GPIO19 level,low is assert.
+ // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default)
+ // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option)
+#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active
+#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention,
+ // low active, when it's low, BIOS will enbale ODD_PWR
+#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17#
+#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK
+#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST#
+#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT
+#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
+#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED#
+#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI
+#define GPIO_120_SELECT FUNCTION0+NonGpio
+#define GPIO_121_SELECT FUNCTION0+NonGpio
+#define GPIO_122_SELECT FUNCTION0+NonGpio
+#define GPIO_123_SELECT FUNCTION0+NonGpio
+#define GPIO_124_SELECT FUNCTION0+NonGpio
+#define GPIO_125_SELECT FUNCTION0+NonGpio
+#define GPIO_126_SELECT FUNCTION0+NonGpio
+#define GPIO_127_SELECT FUNCTION0+NonGpio
+#define GPIO_128_SELECT FUNCTION0+NonGpio
+#define GPIO_129_SELECT FUNCTION0+NonGpio
+#define GPIO_130_SELECT FUNCTION0+NonGpio
+#define GPIO_131_SELECT FUNCTION0+NonGpio
+#define GPIO_132_SELECT FUNCTION0+NonGpio
+#define GPIO_133_SELECT FUNCTION0+NonGpio
+#define GPIO_134_SELECT FUNCTION0+NonGpio
+#define GPIO_135_SELECT FUNCTION0+NonGpio
+#define GPIO_136_SELECT FUNCTION0+NonGpio
+#define GPIO_137_SELECT FUNCTION0+NonGpio
+#define GPIO_138_SELECT FUNCTION0+NonGpio
+#define GPIO_139_SELECT FUNCTION0+NonGpio
+#define GPIO_140_SELECT FUNCTION0+NonGpio
+#define GPIO_141_SELECT FUNCTION0+NonGpio
+#define GPIO_142_SELECT FUNCTION0+NonGpio
+#define GPIO_143_SELECT FUNCTION0+NonGpio
+#define GPIO_144_SELECT FUNCTION0+NonGpio
+#define GPIO_145_SELECT FUNCTION0+NonGpio
+#define GPIO_146_SELECT FUNCTION0+NonGpio
+#define GPIO_147_SELECT FUNCTION0+NonGpio
+#define GPIO_148_SELECT FUNCTION0+NonGpio
+#define GPIO_149_SELECT FUNCTION0+NonGpio
+#define GPIO_150_SELECT FUNCTION0+NonGpio
+#define GPIO_151_SELECT FUNCTION0+NonGpio
+#define GPIO_152_SELECT FUNCTION0+NonGpio
+#define GPIO_153_SELECT FUNCTION0+NonGpio
+#define GPIO_154_SELECT FUNCTION0+NonGpio
+#define GPIO_155_SELECT FUNCTION0+NonGpio
+#define GPIO_156_SELECT FUNCTION0+NonGpio
+#define GPIO_157_SELECT FUNCTION0+NonGpio
+#define GPIO_158_SELECT FUNCTION0+NonGpio
+#define GPIO_159_SELECT FUNCTION0+NonGpio
+#define GPIO_160_SELECT FUNCTION0+NonGpio
+
+// S5-domain General Purpose I/O
+#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST#
+#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM
+#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM
+#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM
+#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM
+#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2
+#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0
+#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1
+#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2
+#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail.
+#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0,
+#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE
+#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3
+#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT#
+#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_178_SELECT FUNCTION2 // MEM_1V5
+#define GPIO_179_SELECT FUNCTION2 // MEM_1V35
+#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO
+#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR
+#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3
+#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0
+#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB#
+#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB
+#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB
+#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE
+#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE
+ // option for HDMI CEC signal OW ACTIVE
+#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active
+#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
+#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA
+#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK
+#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK,
+#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA
+#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK,
+#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA
+#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active
+ // RESERVED FOR LCD BACKLIGHT PWM
+#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL
+#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM
+#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF
+#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI
+#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO
+#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO
+#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO
+#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK,
+#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA
+#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
+
+#define TYPE_GPI (1<<5)
+#define TYPE_GPO (0<<5)
+
+#define GPIO_00_TYPE TYPE_GPO
+#define GPIO_01_TYPE TYPE_GPO
+#define GPIO_02_TYPE TYPE_GPO
+#define GPIO_03_TYPE TYPE_GPO
+#define GPIO_04_TYPE TYPE_GPO
+#define GPIO_05_TYPE TYPE_GPO
+#define GPIO_06_TYPE TYPE_GPO
+#define GPIO_07_TYPE TYPE_GPO
+#define GPIO_08_TYPE TYPE_GPO
+#define GPIO_09_TYPE TYPE_GPI
+#define GPIO_10_TYPE TYPE_GPI
+#define GPIO_11_TYPE TYPE_GPO
+#define GPIO_12_TYPE TYPE_GPO
+#define GPIO_13_TYPE TYPE_GPO
+#define GPIO_14_TYPE TYPE_GPO
+#define GPIO_15_TYPE TYPE_GPO
+#define GPIO_16_TYPE TYPE_GPO
+#define GPIO_17_TYPE TYPE_GPO
+#define GPIO_18_TYPE TYPE_GPO
+#define GPIO_19_TYPE TYPE_GPO
+#define GPIO_20_TYPE TYPE_GPO
+#define GPIO_21_TYPE TYPE_GPO
+#define GPIO_22_TYPE TYPE_GPO
+#define GPIO_23_TYPE TYPE_GPO
+#define GPIO_24_TYPE TYPE_GPO
+#define GPIO_25_TYPE TYPE_GPO
+#define GPIO_26_TYPE TYPE_GPO
+#define GPIO_27_TYPE TYPE_GPO
+#define GPIO_28_TYPE TYPE_GPI
+#define GPIO_29_TYPE TYPE_GPO
+#define GPIO_30_TYPE TYPE_GPI
+#define GPIO_31_TYPE TYPE_GPI
+#define GPIO_32_TYPE TYPE_GPO
+#define GPIO_33_TYPE TYPE_GPI
+#define GPIO_34_TYPE TYPE_GPO
+#define GPIO_35_TYPE TYPE_GPO
+#define GPIO_36_TYPE TYPE_GPO
+#define GPIO_37_TYPE TYPE_GPO
+#define GPIO_38_TYPE TYPE_GPO
+#define GPIO_39_TYPE TYPE_GPO
+#define GPIO_40_TYPE TYPE_GPO
+#define GPIO_41_TYPE TYPE_GPI
+#define GPIO_42_TYPE TYPE_GPI
+#define GPIO_43_TYPE TYPE_GPO
+#define GPIO_44_TYPE TYPE_GPO
+#define GPIO_45_TYPE TYPE_GPO
+#define GPIO_46_TYPE TYPE_GPI
+#define GPIO_47_TYPE TYPE_GPO
+#define GPIO_48_TYPE TYPE_GPO
+#define GPIO_49_TYPE TYPE_GPO
+#define GPIO_50_TYPE TYPE_GPO
+#define GPIO_51_TYPE TYPE_GPO
+#define GPIO_52_TYPE TYPE_GPO
+#define GPIO_53_TYPE TYPE_GPO
+#define GPIO_54_TYPE TYPE_GPO
+#define GPIO_55_TYPE TYPE_GPO
+#define GPIO_56_TYPE TYPE_GPI
+#define GPIO_57_TYPE TYPE_GPO
+#define GPIO_58_TYPE TYPE_GPO
+#define GPIO_59_TYPE TYPE_GPO
+#define GPIO_60_TYPE TYPE_GPI
+#define GPIO_61_TYPE TYPE_GPI
+#define GPIO_62_TYPE TYPE_GPI
+#define GPIO_63_TYPE TYPE_GPI
+#define GPIO_64_TYPE TYPE_GPI
+#define GPIO_65_TYPE TYPE_GPI
+#define GPIO_66_TYPE TYPE_GPO
+#define GPIO_67_TYPE TYPE_GPO
+#define GPIO_68_TYPE TYPE_GPO
+#define GPIO_69_TYPE TYPE_GPO
+#define GPIO_70_TYPE TYPE_GPO
+#define GPIO_71_TYPE TYPE_GPO
+#define GPIO_72_TYPE TYPE_GPO
+#define GPIO_73_TYPE TYPE_GPO
+#define GPIO_74_TYPE TYPE_GPO
+#define GPIO_75_TYPE TYPE_GPO
+#define GPIO_76_TYPE TYPE_GPO
+#define GPIO_77_TYPE TYPE_GPO
+#define GPIO_78_TYPE TYPE_GPO
+#define GPIO_79_TYPE TYPE_GPO
+#define GPIO_80_TYPE TYPE_GPO
+#define GPIO_81_TYPE TYPE_GPO
+#define GPIO_82_TYPE TYPE_GPO
+#define GPIO_83_TYPE TYPE_GPO
+#define GPIO_84_TYPE TYPE_GPO
+#define GPIO_85_TYPE TYPE_GPO
+#define GPIO_86_TYPE TYPE_GPO
+#define GPIO_87_TYPE TYPE_GPO
+#define GPIO_88_TYPE TYPE_GPO
+#define GPIO_89_TYPE TYPE_GPO
+#define GPIO_90_TYPE TYPE_GPO
+#define GPIO_91_TYPE TYPE_GPO
+#define GPIO_92_TYPE TYPE_GPO
+#define GPIO_93_TYPE TYPE_GPO
+#define GPIO_94_TYPE TYPE_GPO
+#define GPIO_95_TYPE TYPE_GPO
+
+// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119
+#define GPIO_96_TYPE TYPE_GPI
+#define GPIO_97_TYPE TYPE_GPI
+#define GPIO_98_TYPE TYPE_GPI
+#define GPIO_99_TYPE TYPE_GPI
+#define GPIO_100_TYPE TYPE_GPI
+#define GPIO_101_TYPE TYPE_GPI
+#define GPIO_102_TYPE TYPE_GPO
+#define GPIO_103_TYPE TYPE_GPO
+#define GPIO_104_TYPE TYPE_GPI
+#define GPIO_105_TYPE TYPE_GPI
+#define GPIO_106_TYPE TYPE_GPO
+#define GPIO_107_TYPE TYPE_GPI
+#define GPIO_108_TYPE TYPE_GPI
+#define GPIO_109_TYPE TYPE_GPI
+#define GPIO_110_TYPE TYPE_GPI
+#define GPIO_111_TYPE TYPE_GPI
+#define GPIO_112_TYPE TYPE_GPI
+#define GPIO_113_TYPE TYPE_GPI
+#define GPIO_114_TYPE TYPE_GPO
+#define GPIO_115_TYPE TYPE_GPI
+#define GPIO_116_TYPE TYPE_GPI
+#define GPIO_117_TYPE TYPE_GPI
+#define GPIO_118_TYPE TYPE_GPI
+#define GPIO_119_TYPE TYPE_GPI
+
+#define GPIO_120_TYPE TYPE_GPO
+#define GPIO_121_TYPE TYPE_GPO
+#define GPIO_122_TYPE TYPE_GPO
+#define GPIO_123_TYPE TYPE_GPO
+#define GPIO_124_TYPE TYPE_GPO
+#define GPIO_125_TYPE TYPE_GPO
+#define GPIO_126_TYPE TYPE_GPO
+#define GPIO_127_TYPE TYPE_GPO
+#define GPIO_128_TYPE TYPE_GPO
+#define GPIO_129_TYPE TYPE_GPO
+#define GPIO_130_TYPE TYPE_GPO
+#define GPIO_131_TYPE TYPE_GPO
+#define GPIO_132_TYPE TYPE_GPO
+#define GPIO_133_TYPE TYPE_GPO
+#define GPIO_134_TYPE TYPE_GPO
+#define GPIO_135_TYPE TYPE_GPO
+#define GPIO_136_TYPE TYPE_GPO
+#define GPIO_137_TYPE TYPE_GPO
+#define GPIO_138_TYPE TYPE_GPO
+#define GPIO_139_TYPE TYPE_GPO
+#define GPIO_140_TYPE TYPE_GPO
+#define GPIO_141_TYPE TYPE_GPO
+#define GPIO_142_TYPE TYPE_GPO
+#define GPIO_143_TYPE TYPE_GPO
+#define GPIO_144_TYPE TYPE_GPO
+#define GPIO_145_TYPE TYPE_GPO
+#define GPIO_146_TYPE TYPE_GPO
+#define GPIO_147_TYPE TYPE_GPO
+#define GPIO_148_TYPE TYPE_GPO
+#define GPIO_149_TYPE TYPE_GPO
+#define GPIO_150_TYPE TYPE_GPO
+#define GPIO_151_TYPE TYPE_GPO
+#define GPIO_152_TYPE TYPE_GPO
+#define GPIO_153_TYPE TYPE_GPO
+#define GPIO_154_TYPE TYPE_GPO
+#define GPIO_155_TYPE TYPE_GPO
+#define GPIO_156_TYPE TYPE_GPO
+#define GPIO_157_TYPE TYPE_GPO
+#define GPIO_158_TYPE TYPE_GPO
+#define GPIO_159_TYPE TYPE_GPO
+#define GPIO_160_TYPE TYPE_GPO
+#define GPIO_161_TYPE TYPE_GPO
+#define GPIO_162_TYPE TYPE_GPO
+#define GPIO_163_TYPE TYPE_GPO
+#define GPIO_164_TYPE TYPE_GPI
+#define GPIO_165_TYPE TYPE_GPO
+#define GPIO_166_TYPE TYPE_GPI
+#define GPIO_167_TYPE TYPE_GPI
+#define GPIO_168_TYPE TYPE_GPI
+#define GPIO_169_TYPE TYPE_GPI
+#define GPIO_170_TYPE TYPE_GPO
+#define GPIO_171_TYPE TYPE_GPI
+#define GPIO_172_TYPE TYPE_GPO
+#define GPIO_173_TYPE TYPE_GPI
+#define GPIO_174_TYPE TYPE_GPI
+#define GPIO_175_TYPE TYPE_GPO
+#define GPIO_176_TYPE TYPE_GPO
+#define GPIO_177_TYPE TYPE_GPO
+#define GPIO_178_TYPE TYPE_GPO
+#define GPIO_179_TYPE TYPE_GPO
+#define GPIO_180_TYPE TYPE_GPO
+#define GPIO_181_TYPE TYPE_GPO
+#define GPIO_182_TYPE TYPE_GPO
+#define GPIO_183_TYPE TYPE_GPO
+#define GPIO_184_TYPE TYPE_GPI
+#define GPIO_185_TYPE TYPE_GPO
+#define GPIO_186_TYPE TYPE_GPO
+#define GPIO_187_TYPE TYPE_GPO
+#define GPIO_188_TYPE TYPE_GPO
+#define GPIO_189_TYPE TYPE_GPI
+#define GPIO_190_TYPE TYPE_GPI
+#define GPIO_191_TYPE TYPE_GPO
+#define GPIO_192_TYPE TYPE_GPO
+#define GPIO_193_TYPE TYPE_GPO
+#define GPIO_194_TYPE TYPE_GPO
+#define GPIO_195_TYPE TYPE_GPO
+#define GPIO_196_TYPE TYPE_GPO
+#define GPIO_197_TYPE TYPE_GPO
+#define GPIO_198_TYPE TYPE_GPO
+#define GPIO_199_TYPE TYPE_GPI
+#define GPIO_200_TYPE TYPE_GPO
+#define GPIO_201_TYPE TYPE_GPI
+#define GPIO_202_TYPE TYPE_GPI
+#define GPIO_203_TYPE TYPE_GPI
+#define GPIO_204_TYPE TYPE_GPI
+#define GPIO_205_TYPE TYPE_GPI
+#define GPIO_206_TYPE TYPE_GPI
+#define GPIO_207_TYPE TYPE_GPI
+#define GPIO_208_TYPE TYPE_GPI
+#define GPIO_209_TYPE TYPE_GPO
+#define GPIO_210_TYPE TYPE_GPO
+#define GPIO_211_TYPE TYPE_GPO
+#define GPIO_212_TYPE TYPE_GPO
+#define GPIO_213_TYPE TYPE_GPO
+#define GPIO_214_TYPE TYPE_GPO
+#define GPIO_215_TYPE TYPE_GPO
+#define GPIO_216_TYPE TYPE_GPO
+#define GPIO_217_TYPE TYPE_GPO
+#define GPIO_218_TYPE TYPE_GPO
+#define GPIO_219_TYPE TYPE_GPO
+#define GPIO_220_TYPE TYPE_GPO
+#define GPIO_221_TYPE TYPE_GPO
+#define GPIO_222_TYPE TYPE_GPO
+#define GPIO_223_TYPE TYPE_GPO
+#define GPIO_224_TYPE TYPE_GPO
+#define GPIO_225_TYPE TYPE_GPO
+#define GPIO_226_TYPE TYPE_GPO
+#define GPIO_227_TYPE TYPE_GPO
+#define GPIO_228_TYPE TYPE_GPO
+#define GPIO_229_TYPE TYPE_GPO
+
+#define GPO_LOW (0<<6)
+#define GPO_HI (1<<6)
+
+#define GPO_00_LEVEL GPO_HI
+#define GPO_01_LEVEL GPO_HI
+#define GPO_02_LEVEL GPO_HI
+#define GPO_03_LEVEL GPO_HI
+#define GPO_04_LEVEL GPO_HI
+#define GPO_05_LEVEL GPO_HI
+#define GPO_06_LEVEL GPO_HI
+#define GPO_07_LEVEL GPO_HI
+#define GPO_08_LEVEL GPO_HI
+#define GPO_09_LEVEL GPO_LOW
+#define GPO_10_LEVEL GPO_LOW
+#define GPO_11_LEVEL GPO_HI
+#define GPO_12_LEVEL GPO_HI
+#define GPO_13_LEVEL GPO_HI
+#define GPO_14_LEVEL GPO_HI
+#define GPO_15_LEVEL GPO_HI
+#define GPO_16_LEVEL GPO_HI
+#define GPO_17_LEVEL GPO_HI
+#define GPO_18_LEVEL GPO_HI
+#define GPO_19_LEVEL GPO_LOW
+#define GPO_20_LEVEL GPO_LOW
+#define GPO_21_LEVEL GPO_LOW
+#define GPO_22_LEVEL GPO_HI
+#define GPO_23_LEVEL GPO_HI
+#define GPO_24_LEVEL GPO_HI
+#define GPO_25_LEVEL GPO_HI
+#define GPO_26_LEVEL GPO_HI
+#define GPO_27_LEVEL GPO_HI
+#define GPO_28_LEVEL GPO_LOW
+#define GPO_29_LEVEL GPO_HI
+#define GPO_30_LEVEL GPO_LOW
+#define GPO_31_LEVEL GPO_LOW
+#define GPO_32_LEVEL GPO_HI
+#define GPO_33_LEVEL GPO_LOW
+#define GPO_34_LEVEL GPO_LOW
+#define GPO_35_LEVEL GPO_LOW
+#define GPO_36_LEVEL GPO_LOW
+#define GPO_37_LEVEL GPO_HI
+#define GPO_38_LEVEL GPO_HI
+#define GPO_39_LEVEL GPO_HI
+#define GPO_40_LEVEL GPO_LOW
+#define GPO_41_LEVEL GPO_LOW
+#define GPO_42_LEVEL GPO_LOW
+#define GPO_43_LEVEL GPO_LOW
+#define GPO_44_LEVEL GPO_HI
+#define GPO_45_LEVEL GPO_HI
+#define GPO_46_LEVEL GPO_LOW
+#define GPO_47_LEVEL GPO_LOW
+#define GPO_48_LEVEL GPO_LOW
+#define GPO_49_LEVEL GPO_HI
+#define GPO_50_LEVEL GPO_HI
+#define GPO_51_LEVEL GPO_LOW
+#define GPO_52_LEVEL GPO_HI
+#define GPO_53_LEVEL GPO_HI
+#define GPO_54_LEVEL GPO_LOW
+#define GPO_55_LEVEL GPO_LOW
+#define GPO_56_LEVEL GPO_LOW
+#define GPO_57_LEVEL GPO_HI
+#define GPO_58_LEVEL GPO_HI
+#define GPO_59_LEVEL GPO_HI
+#define GPO_60_LEVEL GPO_LOW
+#define GPO_61_LEVEL GPO_LOW
+#define GPO_62_LEVEL GPO_LOW
+#define GPO_63_LEVEL GPO_LOW
+#define GPO_64_LEVEL GPO_LOW
+#define GPO_65_LEVEL GPO_LOW
+#define GPO_66_LEVEL GPO_LOW
+#define GPO_67_LEVEL GPO_LOW
+#define GPO_68_LEVEL GPO_LOW
+#define GPO_69_LEVEL GPO_LOW
+#define GPO_70_LEVEL GPO_LOW
+#define GPO_71_LEVEL GPO_LOW
+#define GPO_72_LEVEL GPO_LOW
+#define GPO_73_LEVEL GPO_LOW
+#define GPO_74_LEVEL GPO_LOW
+#define GPO_75_LEVEL GPO_LOW
+#define GPO_76_LEVEL GPO_LOW
+#define GPO_77_LEVEL GPO_LOW
+#define GPO_78_LEVEL GPO_LOW
+#define GPO_79_LEVEL GPO_LOW
+#define GPO_80_LEVEL GPO_LOW
+#define GPO_81_LEVEL GPO_LOW
+#define GPO_82_LEVEL GPO_LOW
+#define GPO_83_LEVEL GPO_LOW
+#define GPO_84_LEVEL GPO_LOW
+#define GPO_85_LEVEL GPO_LOW
+#define GPO_86_LEVEL GPO_LOW
+#define GPO_87_LEVEL GPO_LOW
+#define GPO_88_LEVEL GPO_LOW
+#define GPO_89_LEVEL GPO_LOW
+#define GPO_90_LEVEL GPO_LOW
+#define GPO_91_LEVEL GPO_LOW
+#define GPO_92_LEVEL GPO_LOW
+#define GPO_93_LEVEL GPO_LOW
+#define GPO_94_LEVEL GPO_LOW
+#define GPO_95_LEVEL GPO_LOW
+#define GPO_96_LEVEL GPO_LOW
+#define GPO_97_LEVEL GPO_LOW
+#define GPO_98_LEVEL GPO_LOW
+#define GPO_99_LEVEL GPO_LOW
+#define GPO_100_LEVEL GPO_LOW
+#define GPO_101_LEVEL GPO_LOW
+#define GPO_102_LEVEL GPO_LOW
+#define GPO_103_LEVEL GPO_LOW
+#define GPO_104_LEVEL GPO_LOW
+#define GPO_105_LEVEL GPO_LOW
+#define GPO_106_LEVEL GPO_LOW
+#define GPO_107_LEVEL GPO_LOW
+#define GPO_108_LEVEL GPO_HI
+#define GPO_109_LEVEL GPO_LOW
+#define GPO_110_LEVEL GPO_HI
+#define GPO_111_LEVEL GPO_HI
+#define GPO_112_LEVEL GPO_HI
+#define GPO_113_LEVEL GPO_LOW
+#define GPO_114_LEVEL GPO_LOW
+#define GPO_115_LEVEL GPO_LOW
+#define GPO_116_LEVEL GPO_LOW
+#define GPO_117_LEVEL GPO_LOW
+#define GPO_118_LEVEL GPO_LOW
+#define GPO_119_LEVEL GPO_LOW
+#define GPO_120_LEVEL GPO_LOW
+#define GPO_121_LEVEL GPO_LOW
+#define GPO_122_LEVEL GPO_LOW
+#define GPO_123_LEVEL GPO_LOW
+#define GPO_124_LEVEL GPO_LOW
+#define GPO_125_LEVEL GPO_LOW
+#define GPO_126_LEVEL GPO_LOW
+#define GPO_127_LEVEL GPO_LOW
+#define GPO_128_LEVEL GPO_LOW
+#define GPO_129_LEVEL GPO_LOW
+#define GPO_130_LEVEL GPO_LOW
+#define GPO_131_LEVEL GPO_LOW
+#define GPO_132_LEVEL GPO_LOW
+#define GPO_133_LEVEL GPO_LOW
+#define GPO_134_LEVEL GPO_LOW
+#define GPO_135_LEVEL GPO_LOW
+#define GPO_136_LEVEL GPO_LOW
+#define GPO_137_LEVEL GPO_LOW
+#define GPO_138_LEVEL GPO_LOW
+#define GPO_139_LEVEL GPO_LOW
+#define GPO_140_LEVEL GPO_LOW
+#define GPO_141_LEVEL GPO_LOW
+#define GPO_142_LEVEL GPO_LOW
+#define GPO_143_LEVEL GPO_LOW
+#define GPO_144_LEVEL GPO_LOW
+#define GPO_145_LEVEL GPO_LOW
+#define GPO_146_LEVEL GPO_LOW
+#define GPO_147_LEVEL GPO_LOW
+#define GPO_148_LEVEL GPO_LOW
+#define GPO_149_LEVEL GPO_LOW
+#define GPO_150_LEVEL GPO_LOW
+#define GPO_151_LEVEL GPO_LOW
+#define GPO_152_LEVEL GPO_LOW
+#define GPO_153_LEVEL GPO_LOW
+#define GPO_154_LEVEL GPO_LOW
+#define GPO_155_LEVEL GPO_LOW
+#define GPO_156_LEVEL GPO_LOW
+#define GPO_157_LEVEL GPO_LOW
+#define GPO_158_LEVEL GPO_LOW
+#define GPO_159_LEVEL GPO_LOW
+#define GPO_160_LEVEL GPO_LOW
+#define GPO_161_LEVEL GPO_LOW
+#define GPO_162_LEVEL GPO_LOW
+#define GPO_163_LEVEL GPO_LOW
+#define GPO_164_LEVEL GPO_LOW
+#define GPO_165_LEVEL GPO_LOW
+#define GPO_166_LEVEL GPO_LOW
+#define GPO_167_LEVEL GPO_LOW
+#define GPO_168_LEVEL GPO_LOW
+#define GPO_169_LEVEL GPO_LOW
+#define GPO_170_LEVEL GPO_HI
+#define GPO_171_LEVEL GPO_LOW
+#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+#define GPO_173_LEVEL GPO_LOW
+#define GPO_174_LEVEL GPO_LOW
+#define GPO_175_LEVEL GPO_LOW
+#define GPO_176_LEVEL GPO_LOW
+#define GPO_177_LEVEL GPO_LOW
+#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU
+#define GPO_179_LEVEL GPO_HI
+#define GPO_180_LEVEL GPO_HI
+#define GPO_181_LEVEL GPO_LOW
+#define GPO_182_LEVEL GPO_HI
+#define GPO_183_LEVEL GPO_LOW
+#define GPO_184_LEVEL GPO_LOW
+#define GPO_185_LEVEL GPO_LOW
+#define GPO_186_LEVEL GPO_LOW
+#define GPO_187_LEVEL GPO_LOW
+#define GPO_188_LEVEL GPO_LOW
+#define GPO_189_LEVEL GPO_LOW
+#define GPO_190_LEVEL GPO_LOW
+#define GPO_191_LEVEL GPO_LOW
+#define GPO_192_LEVEL GPO_LOW
+#define GPO_193_LEVEL GPO_LOW
+#define GPO_194_LEVEL GPO_LOW
+#define GPO_195_LEVEL GPO_LOW
+#define GPO_196_LEVEL GPO_LOW
+#define GPO_197_LEVEL GPO_LOW
+#define GPO_198_LEVEL GPO_LOW
+#define GPO_199_LEVEL GPO_LOW
+#define GPO_200_LEVEL GPO_HI
+#define GPO_201_LEVEL GPO_LOW
+#define GPO_202_LEVEL GPO_LOW
+#define GPO_203_LEVEL GPO_LOW
+#define GPO_204_LEVEL GPO_LOW
+#define GPO_205_LEVEL GPO_LOW
+#define GPO_206_LEVEL GPO_LOW
+#define GPO_207_LEVEL GPO_LOW
+#define GPO_208_LEVEL GPO_LOW
+#define GPO_209_LEVEL GPO_LOW
+#define GPO_210_LEVEL GPO_LOW
+#define GPO_211_LEVEL GPO_LOW
+#define GPO_212_LEVEL GPO_LOW
+#define GPO_213_LEVEL GPO_LOW
+#define GPO_214_LEVEL GPO_LOW
+#define GPO_215_LEVEL GPO_LOW
+#define GPO_216_LEVEL GPO_LOW
+#define GPO_217_LEVEL GPO_LOW
+#define GPO_218_LEVEL GPO_LOW
+#define GPO_219_LEVEL GPO_LOW
+#define GPO_220_LEVEL GPO_LOW
+#define GPO_221_LEVEL GPO_LOW
+#define GPO_222_LEVEL GPO_LOW
+#define GPO_223_LEVEL GPO_LOW
+#define GPO_224_LEVEL GPO_LOW
+#define GPO_225_LEVEL GPO_LOW
+#define GPO_226_LEVEL GPO_LOW
+#define GPO_227_LEVEL GPO_LOW
+#define GPO_228_LEVEL GPO_LOW
+#define GPO_229_LEVEL GPO_LOW
+
+#define GPIO_NONSTICKY (0<<2)
+#define GPIO_STICKY (1<<2)
+
+#define GPIO_00_STICKY GPIO_NONSTICKY
+#define GPIO_01_STICKY GPIO_NONSTICKY
+#define GPIO_02_STICKY GPIO_NONSTICKY
+#define GPIO_03_STICKY GPIO_NONSTICKY
+#define GPIO_04_STICKY GPIO_NONSTICKY
+#define GPIO_05_STICKY GPIO_NONSTICKY
+#define GPIO_06_STICKY GPIO_NONSTICKY
+#define GPIO_07_STICKY GPIO_NONSTICKY
+#define GPIO_08_STICKY GPIO_NONSTICKY
+#define GPIO_09_STICKY GPIO_NONSTICKY
+#define GPIO_10_STICKY GPIO_NONSTICKY
+#define GPIO_11_STICKY GPIO_NONSTICKY
+#define GPIO_12_STICKY GPIO_NONSTICKY
+#define GPIO_13_STICKY GPIO_NONSTICKY
+#define GPIO_14_STICKY GPIO_NONSTICKY
+#define GPIO_15_STICKY GPIO_NONSTICKY
+#define GPIO_16_STICKY GPIO_NONSTICKY
+#define GPIO_17_STICKY GPIO_STICKY
+#define GPIO_18_STICKY GPIO_NONSTICKY
+#define GPIO_19_STICKY GPIO_NONSTICKY
+#define GPIO_20_STICKY GPIO_NONSTICKY
+#define GPIO_21_STICKY GPIO_NONSTICKY
+#define GPIO_22_STICKY GPIO_NONSTICKY
+#define GPIO_23_STICKY GPIO_NONSTICKY
+#define GPIO_24_STICKY GPIO_NONSTICKY
+#define GPIO_25_STICKY GPIO_NONSTICKY
+#define GPIO_26_STICKY GPIO_NONSTICKY
+#define GPIO_27_STICKY GPIO_NONSTICKY
+#define GPIO_28_STICKY GPIO_NONSTICKY
+#define GPIO_29_STICKY GPIO_NONSTICKY
+#define GPIO_30_STICKY GPIO_NONSTICKY
+#define GPIO_31_STICKY GPIO_NONSTICKY
+#define GPIO_32_STICKY GPIO_NONSTICKY
+#define GPIO_33_STICKY GPIO_NONSTICKY
+#define GPIO_34_STICKY GPIO_NONSTICKY
+#define GPIO_35_STICKY GPIO_NONSTICKY
+#define GPIO_36_STICKY GPIO_NONSTICKY
+#define GPIO_37_STICKY GPIO_NONSTICKY
+#define GPIO_38_STICKY GPIO_NONSTICKY
+#define GPIO_39_STICKY GPIO_NONSTICKY
+#define GPIO_40_STICKY GPIO_NONSTICKY
+#define GPIO_41_STICKY GPIO_NONSTICKY
+#define GPIO_42_STICKY GPIO_NONSTICKY
+#define GPIO_43_STICKY GPIO_NONSTICKY
+#define GPIO_44_STICKY GPIO_NONSTICKY
+#define GPIO_45_STICKY GPIO_NONSTICKY
+#define GPIO_46_STICKY GPIO_NONSTICKY
+#define GPIO_47_STICKY GPIO_NONSTICKY
+#define GPIO_48_STICKY GPIO_NONSTICKY
+#define GPIO_49_STICKY GPIO_NONSTICKY
+#define GPIO_50_STICKY GPIO_NONSTICKY
+#define GPIO_51_STICKY GPIO_NONSTICKY
+#define GPIO_52_STICKY GPIO_NONSTICKY
+#define GPIO_53_STICKY GPIO_NONSTICKY
+#define GPIO_54_STICKY GPIO_NONSTICKY
+#define GPIO_55_STICKY GPIO_NONSTICKY
+#define GPIO_56_STICKY GPIO_NONSTICKY
+#define GPIO_57_STICKY GPIO_NONSTICKY
+#define GPIO_58_STICKY GPIO_NONSTICKY
+#define GPIO_59_STICKY GPIO_NONSTICKY
+#define GPIO_60_STICKY GPIO_NONSTICKY
+#define GPIO_61_STICKY GPIO_NONSTICKY
+#define GPIO_62_STICKY GPIO_NONSTICKY
+#define GPIO_63_STICKY GPIO_NONSTICKY
+#define GPIO_64_STICKY GPIO_NONSTICKY
+#define GPIO_65_STICKY GPIO_NONSTICKY
+#define GPIO_66_STICKY GPIO_NONSTICKY
+#define GPIO_67_STICKY GPIO_NONSTICKY
+#define GPIO_68_STICKY GPIO_NONSTICKY
+#define GPIO_69_STICKY GPIO_NONSTICKY
+#define GPIO_70_STICKY GPIO_NONSTICKY
+#define GPIO_71_STICKY GPIO_NONSTICKY
+#define GPIO_72_STICKY GPIO_NONSTICKY
+#define GPIO_73_STICKY GPIO_NONSTICKY
+#define GPIO_74_STICKY GPIO_NONSTICKY
+#define GPIO_75_STICKY GPIO_NONSTICKY
+#define GPIO_76_STICKY GPIO_NONSTICKY
+#define GPIO_77_STICKY GPIO_NONSTICKY
+#define GPIO_78_STICKY GPIO_NONSTICKY
+#define GPIO_79_STICKY GPIO_NONSTICKY
+#define GPIO_80_STICKY GPIO_NONSTICKY
+#define GPIO_81_STICKY GPIO_NONSTICKY
+#define GPIO_82_STICKY GPIO_NONSTICKY
+#define GPIO_83_STICKY GPIO_NONSTICKY
+#define GPIO_84_STICKY GPIO_NONSTICKY
+#define GPIO_85_STICKY GPIO_NONSTICKY
+#define GPIO_86_STICKY GPIO_NONSTICKY
+#define GPIO_87_STICKY GPIO_NONSTICKY
+#define GPIO_88_STICKY GPIO_NONSTICKY
+#define GPIO_89_STICKY GPIO_NONSTICKY
+#define GPIO_90_STICKY GPIO_NONSTICKY
+#define GPIO_91_STICKY GPIO_NONSTICKY
+#define GPIO_92_STICKY GPIO_NONSTICKY
+#define GPIO_93_STICKY GPIO_NONSTICKY
+#define GPIO_94_STICKY GPIO_NONSTICKY
+#define GPIO_95_STICKY GPIO_NONSTICKY
+#define GPIO_96_STICKY GPIO_NONSTICKY
+#define GPIO_97_STICKY GPIO_NONSTICKY
+#define GPIO_98_STICKY GPIO_NONSTICKY
+#define GPIO_99_STICKY GPIO_NONSTICKY
+#define GPIO_100_STICKY GPIO_NONSTICKY
+#define GPIO_101_STICKY GPIO_NONSTICKY
+#define GPIO_102_STICKY GPIO_STICKY
+#define GPIO_103_STICKY GPIO_STICKY
+#define GPIO_104_STICKY GPIO_NONSTICKY
+#define GPIO_105_STICKY GPIO_NONSTICKY
+#define GPIO_106_STICKY GPIO_NONSTICKY
+#define GPIO_107_STICKY GPIO_NONSTICKY
+#define GPIO_108_STICKY GPIO_STICKY
+#define GPIO_109_STICKY GPIO_NONSTICKY
+#define GPIO_110_STICKY GPIO_NONSTICKY
+#define GPIO_111_STICKY GPIO_NONSTICKY
+#define GPIO_112_STICKY GPIO_NONSTICKY
+#define GPIO_113_STICKY GPIO_NONSTICKY
+#define GPIO_114_STICKY GPIO_NONSTICKY
+#define GPIO_115_STICKY GPIO_NONSTICKY
+#define GPIO_116_STICKY GPIO_NONSTICKY
+#define GPIO_117_STICKY GPIO_NONSTICKY
+#define GPIO_118_STICKY GPIO_NONSTICKY
+#define GPIO_119_STICKY GPIO_NONSTICKY
+#define GPIO_120_STICKY GPIO_NONSTICKY
+#define GPIO_121_STICKY GPIO_NONSTICKY
+#define GPIO_122_STICKY GPIO_NONSTICKY
+#define GPIO_123_STICKY GPIO_NONSTICKY
+#define GPIO_124_STICKY GPIO_NONSTICKY
+#define GPIO_125_STICKY GPIO_NONSTICKY
+#define GPIO_126_STICKY GPIO_NONSTICKY
+#define GPIO_127_STICKY GPIO_NONSTICKY
+#define GPIO_128_STICKY GPIO_NONSTICKY
+#define GPIO_129_STICKY GPIO_NONSTICKY
+#define GPIO_130_STICKY GPIO_NONSTICKY
+#define GPIO_131_STICKY GPIO_NONSTICKY
+#define GPIO_132_STICKY GPIO_NONSTICKY
+#define GPIO_133_STICKY GPIO_NONSTICKY
+#define GPIO_134_STICKY GPIO_NONSTICKY
+#define GPIO_135_STICKY GPIO_NONSTICKY
+#define GPIO_136_STICKY GPIO_NONSTICKY
+#define GPIO_137_STICKY GPIO_NONSTICKY
+#define GPIO_138_STICKY GPIO_NONSTICKY
+#define GPIO_139_STICKY GPIO_NONSTICKY
+#define GPIO_140_STICKY GPIO_NONSTICKY
+#define GPIO_141_STICKY GPIO_NONSTICKY
+#define GPIO_142_STICKY GPIO_NONSTICKY
+#define GPIO_143_STICKY GPIO_NONSTICKY
+#define GPIO_144_STICKY GPIO_NONSTICKY
+#define GPIO_145_STICKY GPIO_NONSTICKY
+#define GPIO_146_STICKY GPIO_NONSTICKY
+#define GPIO_147_STICKY GPIO_NONSTICKY
+#define GPIO_148_STICKY GPIO_NONSTICKY
+#define GPIO_149_STICKY GPIO_NONSTICKY
+#define GPIO_150_STICKY GPIO_NONSTICKY
+#define GPIO_151_STICKY GPIO_NONSTICKY
+#define GPIO_152_STICKY GPIO_NONSTICKY
+#define GPIO_153_STICKY GPIO_NONSTICKY
+#define GPIO_154_STICKY GPIO_NONSTICKY
+#define GPIO_155_STICKY GPIO_NONSTICKY
+#define GPIO_156_STICKY GPIO_NONSTICKY
+#define GPIO_157_STICKY GPIO_NONSTICKY
+#define GPIO_158_STICKY GPIO_NONSTICKY
+#define GPIO_159_STICKY GPIO_NONSTICKY
+#define GPIO_160_STICKY GPIO_NONSTICKY
+#define GPIO_161_STICKY GPIO_NONSTICKY
+#define GPIO_162_STICKY GPIO_NONSTICKY
+#define GPIO_163_STICKY GPIO_NONSTICKY
+#define GPIO_164_STICKY GPIO_NONSTICKY
+#define GPIO_165_STICKY GPIO_NONSTICKY
+#define GPIO_166_STICKY GPIO_NONSTICKY
+#define GPIO_167_STICKY GPIO_NONSTICKY
+#define GPIO_168_STICKY GPIO_NONSTICKY
+#define GPIO_169_STICKY GPIO_NONSTICKY
+#define GPIO_170_STICKY GPIO_STICKY
+#define GPIO_171_STICKY GPIO_NONSTICKY
+#define GPIO_172_STICKY GPIO_STICKY
+#define GPIO_173_STICKY GPIO_NONSTICKY
+#define GPIO_174_STICKY GPIO_NONSTICKY
+#define GPIO_175_STICKY GPIO_NONSTICKY
+#define GPIO_176_STICKY GPIO_NONSTICKY
+#define GPIO_177_STICKY GPIO_NONSTICKY
+#define GPIO_178_STICKY GPIO_NONSTICKY
+#define GPIO_179_STICKY GPIO_NONSTICKY
+#define GPIO_180_STICKY GPIO_NONSTICKY
+#define GPIO_181_STICKY GPIO_NONSTICKY
+#define GPIO_182_STICKY GPIO_NONSTICKY
+#define GPIO_183_STICKY GPIO_NONSTICKY
+#define GPIO_184_STICKY GPIO_NONSTICKY
+#define GPIO_185_STICKY GPIO_NONSTICKY
+#define GPIO_186_STICKY GPIO_NONSTICKY
+#define GPIO_187_STICKY GPIO_NONSTICKY
+#define GPIO_188_STICKY GPIO_NONSTICKY
+#define GPIO_189_STICKY GPIO_NONSTICKY
+#define GPIO_190_STICKY GPIO_NONSTICKY
+#define GPIO_191_STICKY GPIO_NONSTICKY
+#define GPIO_192_STICKY GPIO_NONSTICKY
+#define GPIO_193_STICKY GPIO_NONSTICKY
+#define GPIO_194_STICKY GPIO_NONSTICKY
+#define GPIO_195_STICKY GPIO_NONSTICKY
+#define GPIO_196_STICKY GPIO_NONSTICKY
+#define GPIO_197_STICKY GPIO_NONSTICKY
+#define GPIO_198_STICKY GPIO_NONSTICKY
+#define GPIO_199_STICKY GPIO_NONSTICKY
+#define GPIO_200_STICKY GPIO_NONSTICKY
+#define GPIO_201_STICKY GPIO_NONSTICKY
+#define GPIO_202_STICKY GPIO_NONSTICKY
+#define GPIO_203_STICKY GPIO_NONSTICKY
+#define GPIO_204_STICKY GPIO_NONSTICKY
+#define GPIO_205_STICKY GPIO_NONSTICKY
+#define GPIO_206_STICKY GPIO_NONSTICKY
+#define GPIO_207_STICKY GPIO_NONSTICKY
+#define GPIO_208_STICKY GPIO_NONSTICKY
+#define GPIO_209_STICKY GPIO_NONSTICKY
+#define GPIO_210_STICKY GPIO_NONSTICKY
+#define GPIO_211_STICKY GPIO_NONSTICKY
+#define GPIO_212_STICKY GPIO_NONSTICKY
+#define GPIO_213_STICKY GPIO_NONSTICKY
+#define GPIO_214_STICKY GPIO_NONSTICKY
+#define GPIO_215_STICKY GPIO_NONSTICKY
+#define GPIO_216_STICKY GPIO_NONSTICKY
+#define GPIO_217_STICKY GPIO_NONSTICKY
+#define GPIO_218_STICKY GPIO_NONSTICKY
+#define GPIO_219_STICKY GPIO_NONSTICKY
+#define GPIO_220_STICKY GPIO_NONSTICKY
+#define GPIO_221_STICKY GPIO_NONSTICKY
+#define GPIO_222_STICKY GPIO_NONSTICKY
+#define GPIO_223_STICKY GPIO_NONSTICKY
+#define GPIO_224_STICKY GPIO_NONSTICKY
+#define GPIO_225_STICKY GPIO_NONSTICKY
+#define GPIO_226_STICKY GPIO_NONSTICKY
+#define GPIO_227_STICKY GPIO_NONSTICKY
+#define GPIO_228_STICKY GPIO_NONSTICKY
+#define GPIO_229_STICKY GPIO_NONSTICKY
+
+#define PULLUP_ENABLE (0<<3)
+#define PULLUP_DISABLE (1<<3)
+
+#define GPIO_00_PULLUP PULLUP_DISABLE
+#define GPIO_01_PULLUP PULLUP_DISABLE
+#define GPIO_02_PULLUP PULLUP_DISABLE
+#define GPIO_03_PULLUP PULLUP_DISABLE
+#define GPIO_04_PULLUP PULLUP_DISABLE
+#define GPIO_05_PULLUP PULLUP_DISABLE
+#define GPIO_06_PULLUP PULLUP_DISABLE
+#define GPIO_07_PULLUP PULLUP_DISABLE
+#define GPIO_08_PULLUP PULLUP_DISABLE
+#define GPIO_09_PULLUP PULLUP_DISABLE
+#define GPIO_10_PULLUP PULLUP_DISABLE
+#define GPIO_11_PULLUP PULLUP_DISABLE
+#define GPIO_12_PULLUP PULLUP_DISABLE
+#define GPIO_13_PULLUP PULLUP_DISABLE
+#define GPIO_14_PULLUP PULLUP_DISABLE
+#define GPIO_15_PULLUP PULLUP_DISABLE
+#define GPIO_16_PULLUP PULLUP_DISABLE
+#define GPIO_17_PULLUP PULLUP_DISABLE
+#define GPIO_18_PULLUP PULLUP_DISABLE
+#define GPIO_19_PULLUP PULLUP_DISABLE
+#define GPIO_20_PULLUP PULLUP_DISABLE
+#define GPIO_21_PULLUP PULLUP_DISABLE
+#define GPIO_22_PULLUP PULLUP_DISABLE
+#define GPIO_23_PULLUP PULLUP_DISABLE
+#define GPIO_24_PULLUP PULLUP_DISABLE
+#define GPIO_25_PULLUP PULLUP_DISABLE
+#define GPIO_26_PULLUP PULLUP_DISABLE
+#define GPIO_27_PULLUP PULLUP_DISABLE
+#define GPIO_28_PULLUP PULLUP_DISABLE
+#define GPIO_29_PULLUP PULLUP_DISABLE
+#define GPIO_30_PULLUP PULLUP_DISABLE
+#define GPIO_31_PULLUP PULLUP_DISABLE
+#define GPIO_32_PULLUP PULLUP_DISABLE
+#define GPIO_33_PULLUP PULLUP_DISABLE
+#define GPIO_34_PULLUP PULLUP_DISABLE
+#define GPIO_35_PULLUP PULLUP_DISABLE
+#define GPIO_36_PULLUP PULLUP_DISABLE
+#define GPIO_37_PULLUP PULLUP_DISABLE
+#define GPIO_38_PULLUP PULLUP_DISABLE
+#define GPIO_39_PULLUP PULLUP_DISABLE
+#define GPIO_40_PULLUP PULLUP_DISABLE
+#define GPIO_41_PULLUP PULLUP_DISABLE
+#define GPIO_42_PULLUP PULLUP_DISABLE
+#define GPIO_43_PULLUP PULLUP_DISABLE
+#define GPIO_44_PULLUP PULLUP_DISABLE
+#define GPIO_45_PULLUP PULLUP_DISABLE
+#define GPIO_46_PULLUP PULLUP_DISABLE
+#define GPIO_47_PULLUP PULLUP_DISABLE
+#define GPIO_48_PULLUP PULLUP_DISABLE
+#define GPIO_49_PULLUP PULLUP_DISABLE
+#define GPIO_50_PULLUP PULLUP_DISABLE
+#define GPIO_51_PULLUP PULLUP_DISABLE
+#define GPIO_52_PULLUP PULLUP_DISABLE
+#define GPIO_53_PULLUP PULLUP_DISABLE
+#define GPIO_54_PULLUP PULLUP_DISABLE
+#define GPIO_55_PULLUP PULLUP_DISABLE
+#define GPIO_56_PULLUP PULLUP_DISABLE
+#define GPIO_57_PULLUP PULLUP_DISABLE
+#define GPIO_58_PULLUP PULLUP_DISABLE
+#define GPIO_59_PULLUP PULLUP_DISABLE
+#define GPIO_60_PULLUP PULLUP_DISABLE
+#define GPIO_61_PULLUP PULLUP_DISABLE
+#define GPIO_62_PULLUP PULLUP_DISABLE
+#define GPIO_63_PULLUP PULLUP_DISABLE
+#define GPIO_64_PULLUP PULLUP_DISABLE
+#define GPIO_65_PULLUP PULLUP_DISABLE
+#define GPIO_66_PULLUP PULLUP_DISABLE
+#define GPIO_67_PULLUP PULLUP_DISABLE
+#define GPIO_68_PULLUP PULLUP_DISABLE
+#define GPIO_69_PULLUP PULLUP_DISABLE
+#define GPIO_70_PULLUP PULLUP_DISABLE
+#define GPIO_71_PULLUP PULLUP_DISABLE
+#define GPIO_72_PULLUP PULLUP_DISABLE
+#define GPIO_73_PULLUP PULLUP_DISABLE
+#define GPIO_74_PULLUP PULLUP_DISABLE
+#define GPIO_75_PULLUP PULLUP_DISABLE
+#define GPIO_76_PULLUP PULLUP_DISABLE
+#define GPIO_77_PULLUP PULLUP_DISABLE
+#define GPIO_78_PULLUP PULLUP_DISABLE
+#define GPIO_79_PULLUP PULLUP_DISABLE
+#define GPIO_80_PULLUP PULLUP_DISABLE
+#define GPIO_80_PULLUP PULLUP_DISABLE
+#define GPIO_81_PULLUP PULLUP_DISABLE
+#define GPIO_82_PULLUP PULLUP_DISABLE
+#define GPIO_83_PULLUP PULLUP_DISABLE
+#define GPIO_84_PULLUP PULLUP_DISABLE
+#define GPIO_85_PULLUP PULLUP_DISABLE
+#define GPIO_86_PULLUP PULLUP_DISABLE
+#define GPIO_87_PULLUP PULLUP_DISABLE
+#define GPIO_88_PULLUP PULLUP_DISABLE
+#define GPIO_89_PULLUP PULLUP_DISABLE
+#define GPIO_90_PULLUP PULLUP_DISABLE
+#define GPIO_91_PULLUP PULLUP_DISABLE
+#define GPIO_92_PULLUP PULLUP_DISABLE
+#define GPIO_93_PULLUP PULLUP_DISABLE
+#define GPIO_94_PULLUP PULLUP_DISABLE
+#define GPIO_95_PULLUP PULLUP_DISABLE
+#define GPIO_96_PULLUP PULLUP_DISABLE
+#define GPIO_97_PULLUP PULLUP_DISABLE
+#define GPIO_98_PULLUP PULLUP_DISABLE
+#define GPIO_99_PULLUP PULLUP_DISABLE
+#define GPIO_100_PULLUP PULLUP_DISABLE
+#define GPIO_101_PULLUP PULLUP_DISABLE
+#define GPIO_102_PULLUP PULLUP_DISABLE
+#define GPIO_103_PULLUP PULLUP_DISABLE
+#define GPIO_104_PULLUP PULLUP_DISABLE
+#define GPIO_105_PULLUP PULLUP_DISABLE
+#define GPIO_106_PULLUP PULLUP_DISABLE
+#define GPIO_107_PULLUP PULLUP_DISABLE
+#define GPIO_108_PULLUP PULLUP_DISABLE
+#define GPIO_109_PULLUP PULLUP_DISABLE
+#define GPIO_110_PULLUP PULLUP_DISABLE
+#define GPIO_111_PULLUP PULLUP_DISABLE
+#define GPIO_112_PULLUP PULLUP_DISABLE
+#define GPIO_113_PULLUP PULLUP_DISABLE
+#define GPIO_114_PULLUP PULLUP_DISABLE
+#define GPIO_115_PULLUP PULLUP_DISABLE
+#define GPIO_116_PULLUP PULLUP_DISABLE
+#define GPIO_117_PULLUP PULLUP_DISABLE
+#define GPIO_118_PULLUP PULLUP_ENABLE
+#define GPIO_119_PULLUP PULLUP_DISABLE
+#define GPIO_120_PULLUP PULLUP_DISABLE
+#define GPIO_121_PULLUP PULLUP_DISABLE
+#define GPIO_122_PULLUP PULLUP_DISABLE
+#define GPIO_123_PULLUP PULLUP_DISABLE
+#define GPIO_124_PULLUP PULLUP_DISABLE
+#define GPIO_125_PULLUP PULLUP_DISABLE
+#define GPIO_126_PULLUP PULLUP_DISABLE
+#define GPIO_127_PULLUP PULLUP_DISABLE
+#define GPIO_128_PULLUP PULLUP_DISABLE
+#define GPIO_129_PULLUP PULLUP_DISABLE
+#define GPIO_130_PULLUP PULLUP_DISABLE
+#define GPIO_131_PULLUP PULLUP_DISABLE
+#define GPIO_132_PULLUP PULLUP_DISABLE
+#define GPIO_133_PULLUP PULLUP_DISABLE
+#define GPIO_134_PULLUP PULLUP_DISABLE
+#define GPIO_135_PULLUP PULLUP_DISABLE
+#define GPIO_136_PULLUP PULLUP_DISABLE
+#define GPIO_137_PULLUP PULLUP_DISABLE
+#define GPIO_138_PULLUP PULLUP_DISABLE
+#define GPIO_139_PULLUP PULLUP_DISABLE
+#define GPIO_140_PULLUP PULLUP_DISABLE
+#define GPIO_141_PULLUP PULLUP_DISABLE
+#define GPIO_142_PULLUP PULLUP_DISABLE
+#define GPIO_143_PULLUP PULLUP_DISABLE
+#define GPIO_144_PULLUP PULLUP_DISABLE
+#define GPIO_145_PULLUP PULLUP_DISABLE
+#define GPIO_146_PULLUP PULLUP_DISABLE
+#define GPIO_147_PULLUP PULLUP_DISABLE
+#define GPIO_148_PULLUP PULLUP_DISABLE
+#define GPIO_149_PULLUP PULLUP_DISABLE
+#define GPIO_150_PULLUP PULLUP_DISABLE
+#define GPIO_151_PULLUP PULLUP_DISABLE
+#define GPIO_152_PULLUP PULLUP_DISABLE
+#define GPIO_153_PULLUP PULLUP_DISABLE
+#define GPIO_154_PULLUP PULLUP_DISABLE
+#define GPIO_155_PULLUP PULLUP_DISABLE
+#define GPIO_156_PULLUP PULLUP_DISABLE
+#define GPIO_157_PULLUP PULLUP_DISABLE
+#define GPIO_158_PULLUP PULLUP_DISABLE
+#define GPIO_159_PULLUP PULLUP_DISABLE
+#define GPIO_160_PULLUP PULLUP_DISABLE
+#define GPIO_161_PULLUP PULLUP_DISABLE
+#define GPIO_162_PULLUP PULLUP_DISABLE
+#define GPIO_163_PULLUP PULLUP_DISABLE
+#define GPIO_164_PULLUP PULLUP_DISABLE
+#define GPIO_165_PULLUP PULLUP_DISABLE
+#define GPIO_166_PULLUP PULLUP_DISABLE
+#define GPIO_167_PULLUP PULLUP_DISABLE
+#define GPIO_168_PULLUP PULLUP_DISABLE
+#define GPIO_169_PULLUP PULLUP_DISABLE
+#define GPIO_170_PULLUP PULLUP_DISABLE
+#define GPIO_171_PULLUP PULLUP_DISABLE
+#define GPIO_172_PULLUP PULLUP_DISABLE
+#define GPIO_173_PULLUP PULLUP_DISABLE
+#define GPIO_174_PULLUP PULLUP_DISABLE
+#define GPIO_175_PULLUP PULLUP_DISABLE
+#define GPIO_176_PULLUP PULLUP_DISABLE
+#define GPIO_177_PULLUP PULLUP_DISABLE
+#define GPIO_178_PULLUP PULLUP_DISABLE
+#define GPIO_179_PULLUP PULLUP_DISABLE
+#define GPIO_180_PULLUP PULLUP_DISABLE
+#define GPIO_180_PULLUP PULLUP_DISABLE
+#define GPIO_181_PULLUP PULLUP_DISABLE
+#define GPIO_182_PULLUP PULLUP_DISABLE
+#define GPIO_183_PULLUP PULLUP_DISABLE
+#define GPIO_184_PULLUP PULLUP_DISABLE
+#define GPIO_185_PULLUP PULLUP_DISABLE
+#define GPIO_186_PULLUP PULLUP_DISABLE
+#define GPIO_187_PULLUP PULLUP_DISABLE
+#define GPIO_188_PULLUP PULLUP_DISABLE
+#define GPIO_189_PULLUP PULLUP_DISABLE
+#define GPIO_190_PULLUP PULLUP_DISABLE
+#define GPIO_191_PULLUP PULLUP_DISABLE
+#define GPIO_192_PULLUP PULLUP_DISABLE
+#define GPIO_193_PULLUP PULLUP_DISABLE
+#define GPIO_194_PULLUP PULLUP_DISABLE
+#define GPIO_195_PULLUP PULLUP_DISABLE
+#define GPIO_196_PULLUP PULLUP_DISABLE
+#define GPIO_197_PULLUP PULLUP_DISABLE
+#define GPIO_198_PULLUP PULLUP_DISABLE
+#define GPIO_199_PULLUP PULLUP_DISABLE
+#define GPIO_200_PULLUP PULLUP_DISABLE
+#define GPIO_201_PULLUP PULLUP_DISABLE
+#define GPIO_202_PULLUP PULLUP_DISABLE
+#define GPIO_203_PULLUP PULLUP_DISABLE
+#define GPIO_204_PULLUP PULLUP_DISABLE
+#define GPIO_205_PULLUP PULLUP_DISABLE
+#define GPIO_206_PULLUP PULLUP_DISABLE
+#define GPIO_207_PULLUP PULLUP_DISABLE
+#define GPIO_208_PULLUP PULLUP_DISABLE
+#define GPIO_209_PULLUP PULLUP_DISABLE
+#define GPIO_210_PULLUP PULLUP_DISABLE
+#define GPIO_211_PULLUP PULLUP_DISABLE
+#define GPIO_212_PULLUP PULLUP_DISABLE
+#define GPIO_213_PULLUP PULLUP_DISABLE
+#define GPIO_214_PULLUP PULLUP_DISABLE
+#define GPIO_215_PULLUP PULLUP_DISABLE
+#define GPIO_216_PULLUP PULLUP_DISABLE
+#define GPIO_217_PULLUP PULLUP_DISABLE
+#define GPIO_218_PULLUP PULLUP_DISABLE
+#define GPIO_219_PULLUP PULLUP_DISABLE
+#define GPIO_220_PULLUP PULLUP_DISABLE
+#define GPIO_221_PULLUP PULLUP_DISABLE
+#define GPIO_222_PULLUP PULLUP_DISABLE
+#define GPIO_223_PULLUP PULLUP_DISABLE
+#define GPIO_224_PULLUP PULLUP_DISABLE
+#define GPIO_225_PULLUP PULLUP_DISABLE
+#define GPIO_226_PULLUP PULLUP_DISABLE
+#define GPIO_227_PULLUP PULLUP_DISABLE
+#define GPIO_228_PULLUP PULLUP_DISABLE
+#define GPIO_229_PULLUP PULLUP_DISABLE
+
+#define PULLDOWN_ENABLE (1<<4)
+#define PULLDOWN_DISABLE (0<<4)
+
+#define GPIO_00_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_01_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_02_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_03_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_04_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_05_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_06_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_07_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_08_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_09_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_10_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_11_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_12_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_13_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_14_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_15_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_16_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_17_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_18_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_19_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_20_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_21_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_22_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_23_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_24_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_25_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_26_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_27_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_28_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_29_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_30_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_31_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_32_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_33_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_34_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_35_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_36_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_37_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_38_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_39_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_40_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_41_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_42_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_43_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_44_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_45_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_46_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_47_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_48_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_49_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_50_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_51_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_52_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_53_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_54_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_55_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_56_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_57_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_58_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_59_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_60_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_61_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_62_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_63_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_64_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_65_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_66_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_67_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_68_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_69_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_70_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_71_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_72_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_73_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_74_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_75_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_76_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_77_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_78_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_79_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_80_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_80_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_81_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_82_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_83_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_84_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_85_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_86_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_87_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_88_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_89_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_90_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_91_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_92_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_93_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_94_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_95_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_96_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_97_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_98_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_99_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_100_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_101_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_102_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_103_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_104_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_105_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_106_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_107_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_108_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_109_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_110_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_111_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_112_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_113_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_114_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_115_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_116_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_117_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_118_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_119_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_120_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_121_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_122_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_123_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_124_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_125_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_126_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_127_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_128_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_129_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_130_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_131_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_132_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_133_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_134_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_135_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_136_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_137_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_138_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_139_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_140_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_141_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_142_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_143_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_144_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_145_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_146_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_147_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_148_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_149_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_150_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_151_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_152_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_153_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_154_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_155_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_156_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_157_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_158_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_159_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_160_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_161_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_162_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_163_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_164_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_165_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_166_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_167_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_168_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_169_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_170_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_171_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_172_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_173_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_174_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_175_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_176_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_177_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_178_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_179_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_180_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_180_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_181_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_182_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_183_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_184_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_185_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_186_PULLDOWN PULLDOWN_ENABLE
+#define GPIO_187_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_188_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_189_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_190_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_191_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_192_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_193_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_194_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_195_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_196_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_197_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_198_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_199_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_200_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_201_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_202_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_203_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_204_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_205_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_206_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_207_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_208_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_209_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_210_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_211_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_212_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_213_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_214_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_215_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_216_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_217_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_218_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_219_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_220_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_221_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_222_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_223_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_224_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_225_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_226_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_227_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_228_PULLDOWN PULLDOWN_DISABLE
+#define GPIO_229_PULLDOWN PULLDOWN_DISABLE
+
+#define EVENT_DISABLE 0
+#define EVENT_ENABLE 1
+
+#define GEVENT_00_EVENTENABLE EVENT_DISABLE
+#define GEVENT_01_EVENTENABLE EVENT_DISABLE
+#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP#
+#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI#
+#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT#
+#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN#
+#define GEVENT_06_EVENTENABLE EVENT_DISABLE
+#define GEVENT_07_EVENTENABLE EVENT_DISABLE
+#define GEVENT_08_EVENTENABLE EVENT_DISABLE
+#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO
+#define GEVENT_10_EVENTENABLE EVENT_DISABLE
+#define GEVENT_11_EVENTENABLE EVENT_DISABLE
+#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT#
+#define GEVENT_13_EVENTENABLE EVENT_DISABLE
+#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK#
+#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN#
+#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA
+#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN
+#define GEVENT_18_EVENTENABLE EVENT_DISABLE
+#define GEVENT_19_EVENTENABLE EVENT_DISABLE
+#define GEVENT_20_EVENTENABLE EVENT_DISABLE
+#define GEVENT_21_EVENTENABLE EVENT_DISABLE
+#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE#
+#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI#
+
+#define SCITRIG_LOW 0
+#define SCITRIG_HI 1
+
+#define GEVENT_00_SCITRIG SCITRIG_LOW
+#define GEVENT_01_SCITRIG SCITRIG_LOW
+#define GEVENT_02_SCITRIG SCITRIG_LOW
+#define GEVENT_03_SCITRIG SCITRIG_LOW
+#define GEVENT_04_SCITRIG SCITRIG_LOW
+#define GEVENT_05_SCITRIG SCITRIG_LOW
+#define GEVENT_06_SCITRIG SCITRIG_LOW
+#define GEVENT_07_SCITRIG SCITRIG_LOW
+#define GEVENT_08_SCITRIG SCITRIG_LOW
+#define GEVENT_09_SCITRIG SCITRIG_LOW
+#define GEVENT_10_SCITRIG SCITRIG_LOW
+#define GEVENT_11_SCITRIG SCITRIG_LOW
+#define GEVENT_12_SCITRIG SCITRIG_LOW
+#define GEVENT_13_SCITRIG SCITRIG_LOW
+#define GEVENT_14_SCITRIG SCITRIG_LOW
+#define GEVENT_15_SCITRIG SCITRIG_LOW
+#define GEVENT_16_SCITRIG SCITRIG_LOW
+#define GEVENT_17_SCITRIG SCITRIG_HI
+#define GEVENT_18_SCITRIG SCITRIG_LOW
+#define GEVENT_19_SCITRIG SCITRIG_LOW
+#define GEVENT_20_SCITRIG SCITRIG_LOW
+#define GEVENT_21_SCITRIG SCITRIG_LOW
+#define GEVENT_22_SCITRIG SCITRIG_LOW
+#define GEVENT_23_SCITRIG SCITRIG_LOW
+
+#define SCILEVEL_EDGE 0
+#define SCILEVEL_LEVEL 1
+
+#define GEVENT_00_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_01_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_02_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_03_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_04_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_05_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_06_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_07_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_08_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_09_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_10_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_11_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_12_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_13_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_14_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_15_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_16_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_17_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_18_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_19_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_20_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_21_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_22_SCILEVEL SCILEVEL_EDGE
+#define GEVENT_23_SCILEVEL SCILEVEL_EDGE
+
+#define SMISCI_DISABLE 0
+#define SMISCI_ENABLE 1
+
+#define GEVENT_00_SMISCIEN SMISCI_DISABLE
+#define GEVENT_01_SMISCIEN SMISCI_DISABLE
+#define GEVENT_02_SMISCIEN SMISCI_DISABLE
+#define GEVENT_03_SMISCIEN SMISCI_DISABLE
+#define GEVENT_04_SMISCIEN SMISCI_DISABLE
+#define GEVENT_05_SMISCIEN SMISCI_DISABLE
+#define GEVENT_06_SMISCIEN SMISCI_DISABLE
+#define GEVENT_07_SMISCIEN SMISCI_DISABLE
+#define GEVENT_08_SMISCIEN SMISCI_DISABLE
+#define GEVENT_09_SMISCIEN SMISCI_DISABLE
+#define GEVENT_10_SMISCIEN SMISCI_DISABLE
+#define GEVENT_11_SMISCIEN SMISCI_DISABLE
+#define GEVENT_12_SMISCIEN SMISCI_DISABLE
+#define GEVENT_13_SMISCIEN SMISCI_DISABLE
+#define GEVENT_14_SMISCIEN SMISCI_DISABLE
+#define GEVENT_15_SMISCIEN SMISCI_DISABLE
+#define GEVENT_16_SMISCIEN SMISCI_DISABLE
+#define GEVENT_17_SMISCIEN SMISCI_DISABLE
+#define GEVENT_18_SMISCIEN SMISCI_DISABLE
+#define GEVENT_19_SMISCIEN SMISCI_DISABLE
+#define GEVENT_20_SMISCIEN SMISCI_DISABLE
+#define GEVENT_21_SMISCIEN SMISCI_DISABLE
+#define GEVENT_22_SMISCIEN SMISCI_DISABLE
+#define GEVENT_23_SMISCIEN SMISCI_DISABLE
+
+#define SCIS0_DISABLE 0
+#define SCIS0_ENABLE 1
+
+#define GEVENT_00_SCIS0EN SCIS0_DISABLE
+#define GEVENT_01_SCIS0EN SCIS0_DISABLE
+#define GEVENT_02_SCIS0EN SCIS0_DISABLE
+#define GEVENT_03_SCIS0EN SCIS0_DISABLE
+#define GEVENT_04_SCIS0EN SCIS0_DISABLE
+#define GEVENT_05_SCIS0EN SCIS0_DISABLE
+#define GEVENT_06_SCIS0EN SCIS0_DISABLE
+#define GEVENT_07_SCIS0EN SCIS0_DISABLE
+#define GEVENT_08_SCIS0EN SCIS0_DISABLE
+#define GEVENT_09_SCIS0EN SCIS0_DISABLE
+#define GEVENT_10_SCIS0EN SCIS0_DISABLE
+#define GEVENT_11_SCIS0EN SCIS0_DISABLE
+#define GEVENT_12_SCIS0EN SCIS0_DISABLE
+#define GEVENT_13_SCIS0EN SCIS0_DISABLE
+#define GEVENT_14_SCIS0EN SCIS0_DISABLE
+#define GEVENT_15_SCIS0EN SCIS0_DISABLE
+#define GEVENT_16_SCIS0EN SCIS0_DISABLE
+#define GEVENT_17_SCIS0EN SCIS0_DISABLE
+#define GEVENT_18_SCIS0EN SCIS0_DISABLE
+#define GEVENT_19_SCIS0EN SCIS0_DISABLE
+#define GEVENT_20_SCIS0EN SCIS0_DISABLE
+#define GEVENT_21_SCIS0EN SCIS0_DISABLE
+#define GEVENT_22_SCIS0EN SCIS0_DISABLE
+#define GEVENT_23_SCIS0EN SCIS0_DISABLE
+
+#define GEVENT_SCIMASK 0x1F
+#define GEVENT_00_SCIMAP 0
+#define GEVENT_01_SCIMAP 1
+#define GEVENT_02_SCIMAP 2
+#define GEVENT_03_SCIMAP 3
+#define GEVENT_04_SCIMAP 4
+#define GEVENT_05_SCIMAP 5
+#define GEVENT_06_SCIMAP 6
+#define GEVENT_07_SCIMAP 7
+#define GEVENT_08_SCIMAP 8
+#define GEVENT_09_SCIMAP 9
+#define GEVENT_10_SCIMAP 10
+#define GEVENT_11_SCIMAP 11
+#define GEVENT_12_SCIMAP 12
+#define GEVENT_13_SCIMAP 13
+#define GEVENT_14_SCIMAP 14
+#define GEVENT_15_SCIMAP 15
+#define GEVENT_16_SCIMAP 16
+#define GEVENT_17_SCIMAP 17
+#define GEVENT_18_SCIMAP 18
+#define GEVENT_19_SCIMAP 19
+#define GEVENT_20_SCIMAP 20
+#define GEVENT_21_SCIMAP 21
+#define GEVENT_22_SCIMAP 22
+#define GEVENT_23_SCIMAP 23
+
+#define SMITRIG_LOW 0
+#define SMITRIG_HI 1
+
+#define GEVENT_00_SMITRIG SMITRIG_HI
+#define GEVENT_01_SMITRIG SMITRIG_HI
+#define GEVENT_02_SMITRIG SMITRIG_HI
+#define GEVENT_03_SMITRIG SMITRIG_HI
+#define GEVENT_04_SMITRIG SMITRIG_HI
+#define GEVENT_05_SMITRIG SMITRIG_HI
+#define GEVENT_06_SMITRIG SMITRIG_HI
+#define GEVENT_07_SMITRIG SMITRIG_HI
+#define GEVENT_08_SMITRIG SMITRIG_HI
+#define GEVENT_09_SMITRIG SMITRIG_HI
+#define GEVENT_10_SMITRIG SMITRIG_HI
+#define GEVENT_11_SMITRIG SMITRIG_HI
+#define GEVENT_12_SMITRIG SMITRIG_HI
+#define GEVENT_13_SMITRIG SMITRIG_HI
+#define GEVENT_14_SMITRIG SMITRIG_HI
+#define GEVENT_15_SMITRIG SMITRIG_HI
+#define GEVENT_16_SMITRIG SMITRIG_HI
+#define GEVENT_17_SMITRIG SMITRIG_HI
+#define GEVENT_18_SMITRIG SMITRIG_HI
+#define GEVENT_19_SMITRIG SMITRIG_HI
+#define GEVENT_20_SMITRIG SMITRIG_HI
+#define GEVENT_21_SMITRIG SMITRIG_HI
+#define GEVENT_22_SMITRIG SMITRIG_HI
+#define GEVENT_23_SMITRIG SMITRIG_HI
+
+#define SMICONTROL_MASK 3
+#define SMICONTROL_DISABLE 0
+#define SMICONTROL_SMI 1
+#define SMICONTROL_NMI 2
+#define SMICONTROL_IRQ13 3
+
+#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE
+#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE
+
+#define GPIO_RSVD_ZONE0_S GPIO_81
+#define GPIO_RSVD_ZONE0_E GPIO_95
+#define GPIO_RSVD_ZONE1_S GPIO_120
+#define GPIO_RSVD_ZONE1_E GPIO_127
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef enum _GPIO_COUNT
+{
+ GPIO_00=0,
+ GPIO_01,
+ GPIO_02,
+ GPIO_03,
+ GPIO_04,
+ GPIO_05,
+ GPIO_06,
+ GPIO_07,
+ GPIO_08,
+ GPIO_09,
+ GPIO_10,
+ GPIO_11,
+ GPIO_12,
+ GPIO_13,
+ GPIO_14,
+ GPIO_15,
+ GPIO_16,
+ GPIO_17,
+ GPIO_18,
+ GPIO_19,
+ GPIO_20,
+ GPIO_21,
+ GPIO_22,
+ GPIO_23,
+ GPIO_24,
+ GPIO_25,
+ GPIO_26,
+ GPIO_27,
+ GPIO_28,
+ GPIO_29,
+ GPIO_30,
+ GPIO_31,
+ GPIO_32,
+ GPIO_33,
+ GPIO_34,
+ GPIO_35,
+ GPIO_36,
+ GPIO_37,
+ GPIO_38,
+ GPIO_39,
+ GPIO_40,
+ GPIO_41,
+ GPIO_42,
+ GPIO_43,
+ GPIO_44,
+ GPIO_45,
+ GPIO_46,
+ GPIO_47,
+ GPIO_48,
+ GPIO_49,
+ GPIO_50,
+ GPIO_51,
+ GPIO_52,
+ GPIO_53,
+ GPIO_54,
+ GPIO_55,
+ GPIO_56,
+ GPIO_57,
+ GPIO_58,
+ GPIO_59,
+ GPIO_60,
+ GPIO_61,
+ GPIO_62,
+ GPIO_63,
+ GPIO_64,
+ GPIO_65,
+ GPIO_66,
+ GPIO_67,
+ GPIO_68,
+ GPIO_69,
+ GPIO_70,
+ GPIO_71,
+ GPIO_72,
+ GPIO_73,
+ GPIO_74,
+ GPIO_75,
+ GPIO_76,
+ GPIO_77,
+ GPIO_78,
+ GPIO_79,
+ GPIO_80,
+ GPIO_81,
+ GPIO_82,
+ GPIO_83,
+ GPIO_84,
+ GPIO_85,
+ GPIO_86,
+ GPIO_87,
+ GPIO_88,
+ GPIO_89,
+ GPIO_90,
+ GPIO_91,
+ GPIO_92,
+ GPIO_93,
+ GPIO_94,
+ GPIO_95,
+ GPIO_96,
+ GPIO_97,
+ GPIO_98,
+ GPIO_99,
+ GPIO_100,
+ GPIO_101,
+ GPIO_102,
+ GPIO_103,
+ GPIO_104,
+ GPIO_105,
+ GPIO_106,
+ GPIO_107,
+ GPIO_108,
+ GPIO_109,
+ GPIO_110,
+ GPIO_111,
+ GPIO_112,
+ GPIO_113,
+ GPIO_114,
+ GPIO_115,
+ GPIO_116,
+ GPIO_117,
+ GPIO_118,
+ GPIO_119,
+ GPIO_120,
+ GPIO_121,
+ GPIO_122,
+ GPIO_123,
+ GPIO_124,
+ GPIO_125,
+ GPIO_126,
+ GPIO_127,
+ GPIO_128,
+ GPIO_129,
+ GPIO_130,
+ GPIO_131,
+ GPIO_132,
+ GPIO_133,
+ GPIO_134,
+ GPIO_135,
+ GPIO_136,
+ GPIO_137,
+ GPIO_138,
+ GPIO_139,
+ GPIO_140,
+ GPIO_141,
+ GPIO_142,
+ GPIO_143,
+ GPIO_144,
+ GPIO_145,
+ GPIO_146,
+ GPIO_147,
+ GPIO_148,
+ GPIO_149,
+ GPIO_150,
+ GPIO_151,
+ GPIO_152,
+ GPIO_153,
+ GPIO_154,
+ GPIO_155,
+ GPIO_156,
+ GPIO_157,
+ GPIO_158,
+ GPIO_159,
+ GPIO_160,
+ GPIO_161,
+ GPIO_162,
+ GPIO_163,
+ GPIO_164,
+ GPIO_165,
+ GPIO_166,
+ GPIO_167,
+ GPIO_168,
+ GPIO_169,
+ GPIO_170,
+ GPIO_171,
+ GPIO_172,
+ GPIO_173,
+ GPIO_174,
+ GPIO_175,
+ GPIO_176,
+ GPIO_177,
+ GPIO_178,
+ GPIO_179,
+ GPIO_180,
+ GPIO_181,
+ GPIO_182,
+ GPIO_183,
+ GPIO_184,
+ GPIO_185,
+ GPIO_186,
+ GPIO_187,
+ GPIO_188,
+ GPIO_189,
+ GPIO_190,
+ GPIO_191,
+ GPIO_192,
+ GPIO_193,
+ GPIO_194,
+ GPIO_195,
+ GPIO_196,
+ GPIO_197,
+ GPIO_198,
+ GPIO_199,
+ GPIO_200,
+ GPIO_201,
+ GPIO_202,
+ GPIO_203,
+ GPIO_204,
+ GPIO_205,
+ GPIO_206,
+ GPIO_207,
+ GPIO_208,
+ GPIO_209,
+ GPIO_210,
+ GPIO_211,
+ GPIO_212,
+ GPIO_213,
+ GPIO_214,
+ GPIO_215,
+ GPIO_216,
+ GPIO_217,
+ GPIO_218,
+ GPIO_219,
+ GPIO_220,
+ GPIO_221,
+ GPIO_222,
+ GPIO_223,
+ GPIO_224,
+ GPIO_225,
+ GPIO_226,
+ GPIO_227,
+ GPIO_228,
+ GPIO_229,
+ MAX_GPIO_NO
+} GPIO_COUNT;
+
+typedef struct _GPIO_SETTINGS
+{
+ u8 select;
+ u8 type;
+ u8 value;
+ u8 NonGpioGevent;
+} GPIO_SETTINGS;
+
+GPIO_SETTINGS gpio_table[]=
+{
+ {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT},
+ {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT},
+ {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT},
+ {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT},
+ {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT},
+ {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT},
+ {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT},
+ {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT},
+ {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT},
+ {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT},
+ {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT},
+ {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT},
+ {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT},
+ {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT},
+ {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT},
+ {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT},
+ {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT},
+ {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT},
+ {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT},
+ {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT},
+ {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT},
+ {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT},
+ {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT},
+ {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT},
+ {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT},
+ {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT},
+ {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT},
+ {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT},
+ {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT},
+ {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT},
+ {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT},
+ {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT},
+ {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT},
+ {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT},
+ {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT},
+ {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT},
+ {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT},
+ {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT},
+ {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT},
+ {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT},
+ {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT},
+ {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT},
+ {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT},
+ {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT},
+ {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT},
+ {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT},
+ {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT},
+ {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT},
+ {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT},
+ {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT},
+ {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT},
+ {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT},
+ {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT},
+ {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT},
+ {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT},
+ {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT},
+ {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT},
+ {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT},
+ {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT},
+ {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT},
+ {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT},
+ {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT},
+ {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT},
+ {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT},
+ {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT},
+ {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT},
+ {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT},
+ {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT},
+ {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT},
+ {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT},
+ {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT},
+ {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT},
+ {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT},
+ {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT},
+ {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT},
+ {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT},
+ {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT},
+ {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT},
+ {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT},
+ {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT},
+ {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT},
+ {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT},
+ {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT},
+ {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT},
+ {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT},
+ {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT},
+ {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT},
+ {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT},
+ {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT},
+ {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT},
+ {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT},
+ {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT},
+ {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT},
+ {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT},
+ {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT},
+ {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT},
+ {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT},
+ {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT},
+ {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT},
+ {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT},
+ {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT},
+ {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT},
+ {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT},
+ {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT},
+ {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT},
+ {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT},
+ {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT},
+ {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT},
+ {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT},
+ {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT},
+ {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT},
+ {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT},
+ {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT},
+ {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT},
+ {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT},
+ {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT},
+ {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT},
+ {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT},
+ {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT},
+ {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT},
+ {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT},
+ {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT},
+ {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT},
+ {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT},
+ {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT},
+ {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT},
+ {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT},
+ {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT},
+ {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT},
+ {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT},
+ {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT},
+ {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT},
+ {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT},
+ {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT},
+ {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT},
+ {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT},
+ {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT},
+ {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT},
+ {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT},
+ {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT},
+ {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT},
+ {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT},
+ {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT},
+ {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT},
+ {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT},
+ {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT},
+ {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT},
+ {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT},
+ {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT},
+ {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT},
+ {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT},
+ {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT},
+ {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT},
+ {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT},
+ {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT},
+ {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT},
+ {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT},
+ {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT},
+ {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT},
+ {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT},
+ {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT},
+ {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT},
+ {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT},
+ {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT},
+ {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT},
+ {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT},
+ {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT},
+ {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT},
+ {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT},
+ {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT},
+ {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT},
+ {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT},
+ {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT},
+ {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT},
+ {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT},
+ {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT},
+ {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT},
+ {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT},
+ {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT},
+ {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT},
+ {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT},
+ {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT},
+ {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT},
+ {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT},
+ {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT},
+ {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT},
+ {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT},
+ {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT},
+ {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT},
+ {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT},
+ {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT},
+ {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT},
+ {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT},
+ {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT},
+ {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT},
+ {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT},
+ {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT},
+ {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT},
+ {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT},
+ {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT},
+ {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT},
+ {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT},
+ {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT},
+ {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT},
+ {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT},
+ {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT},
+ {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT},
+ {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT},
+ {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT},
+ {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT},
+ {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT},
+ {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT},
+ {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT},
+ {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT},
+ {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT},
+ {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT},
+ {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT},
+ {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT},
+ {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT},
+ {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT},
+ {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT},
+ {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT},
+ {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT},
+ {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT},
+ {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT},
+ {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT},
+ {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT},
+ {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT},
+ {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT},
+ {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT},
+};
+
+typedef enum _GEVENT_COUNT
+{
+ GEVENT_00=0x60,
+ GEVENT_01,
+ GEVENT_02,
+ GEVENT_03,
+ GEVENT_04,
+ GEVENT_05,
+ GEVENT_06,
+ GEVENT_07,
+ GEVENT_08,
+ GEVENT_09,
+ GEVENT_10,
+ GEVENT_11,
+ GEVENT_12,
+ GEVENT_13,
+ GEVENT_14,
+ GEVENT_15,
+ GEVENT_16,
+ GEVENT_17,
+ GEVENT_18,
+ GEVENT_19,
+ GEVENT_20,
+ GEVENT_21,
+ GEVENT_22,
+ GEVENT_23
+} GEVENT_COUNT;
+
+typedef struct _GEVENT_SETTINGS
+{
+ u8 EventEnable; // 0: Disable, 1: Enable
+ u8 SciTrig; // 0: Falling Edge, 1: Rising Edge
+ u8 SciLevl; // 0: Edge trigger, 1: Level Trigger
+ u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI
+ u8 SciS0En; // 0: Disable, 1: Enable
+ u8 SciMap; // 0000b->1111b
+ u8 SmiTrig; // 0: Active Low, 1: Active High
+ u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13
+} GEVENT_SETTINGS;
+
+GEVENT_SETTINGS gevent_table[] =
+{
+ {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL},
+ {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL},
+ {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL},
+ {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL},
+ {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL},
+ {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL},
+ {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL},
+ {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL},
+ {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL},
+ {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL},
+ {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL},
+ {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL},
+ {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL},
+ {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL},
+ {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL},
+ {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL},
+ {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL},
+ {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL},
+ {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL},
+ {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL},
+ {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL},
+ {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL},
+ {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL},
+ {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL},
+};
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif
diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c
new file mode 100755
index 0000000..f61f1e8
--- /dev/null
+++ b/src/mainboard/amd/torpedo/irq_tables.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+//#include <cpu/amd/amdfam10_sysconf.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sb900[2];
+extern unsigned long sbdn_sb900;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sb900[0];
+ pirq->rtr_devfn = ((sbdn_sb900 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sb900[0], ((sbdn_sb900 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+
+
+ slot_num++;
+
+
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
new file mode 100755
index 0000000..288798f
--- /dev/null
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb900/sb900.h>
+#include "chip.h"
+
+#define ONE_MB 0x100000
+//#define SMBUS_IO_BASE 0x6000
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+uint64_t uma_memory_base, uma_memory_size;
+
+/*************************************************
+* enable the dedicated function in torpedo board.
+*************************************************/
+static void torpedo_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard Torpedo Enable. dev=0x%p\n", dev);
+#if (CONFIG_GFXUMA == 1)
+ msr_t msr, msr2;
+ uint32_t sys_mem;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk
+ (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk
+ (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ /* refer to UMA Size Consideration in Family12h BKDG. */
+ /* Please reference MemNGetUmaSizeLN () */
+ /*
+ * Total system memory UMASize
+ * >= 2G 512M
+ * >=1G 256M
+ * <1G 64M
+ */
+ sys_mem = msr.lo;
+ sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size
+ if (sys_mem >= 2048 * ONE_MB) {
+ uma_memory_size = 512 * ONE_MB;
+ } else if (sys_mem >= 1024 * ONE_MB) {
+ uma_memory_size = 256 * ONE_MB;
+ } else {
+ uma_memory_size = 64 * ONE_MB;
+ }
+ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
+
+ /* TODO: TOP_MEM2 */
+#else
+ uma_memory_size = 0x10000000; /* 256M recommended UMA */
+ uma_memory_base = 0x30000000; /* 1GB system memory supported */
+#endif
+
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ /* UMA is removed from system memory in the northbridge code, but
+ * in some circumstances we want the memory mentioned as reserved.
+ */
+#if (CONFIG_GFXUMA == 1)
+ printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+ uma_memory_base, uma_memory_size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+ uma_memory_size);
+#endif
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD TORPEDO Mainboard")
+ .enable_dev = torpedo_enable,
+};
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
new file mode 100755
index 0000000..755b4a3
--- /dev/null
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -0,0 +1,252 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+
+//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
+#define IO_APIC_ID CONFIG_MAX_CPUS
+extern u8 bus_sb900[2];
+
+
+extern u32 bus_type[256];
+extern u32 sbdn_sb900;
+u32 apicid_sb900;
+
+u8 picr_data[] = {
+ 0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x0B,0x0B,0x0B,0x0B
+};
+u8 intr_data[] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ int boot_apic_id;
+ unsigned apic_version;
+ unsigned cpu_features;
+ unsigned cpu_feature_flags;
+ struct cpuid_result result;
+ unsigned long cpu_flag;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LAPIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ /*Inagua used dure core cpu with one die */
+ boot_apic_id = lapicid();
+ apic_version = lapic_read(LAPIC_LVR) & 0xff;
+ result = cpuid(1);
+ cpu_features = result.eax;
+ cpu_feature_flags = result.edx;
+ cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+ smp_write_processor(mc,
+ 0, apic_version,
+ cpu_flag, cpu_features, cpu_feature_flags
+ );
+
+ cpu_flag = MPC_CPU_ENABLED;
+ smp_write_processor(mc,
+ 1, apic_version,
+ cpu_flag, cpu_features, cpu_feature_flags
+ );
+
+ get_bus_conf();
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+
+ device_t dev;
+ u32 dword;
+ u8 byte;
+
+ dword = 0;
+ dword = pm_ioread(0x34) & 0xF0;
+ dword |= (pm_ioread(0x35) & 0xFF) << 8;
+ dword |= (pm_ioread(0x36) & 0xFF) << 16;
+ dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ /* Set IO APIC ID onto IO_APIC_ID */
+ write32 (dword, 0x00);
+ write32 (dword + 0x10, IO_APIC_ID << 24);
+ apicid_sb900 = IO_APIC_ID;
+ smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
+ /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
+
+ PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13);
+ PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14);
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum =
+ smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/torpedo/pmio.c b/src/mainboard/amd/torpedo/pmio.c
new file mode 100755
index 0000000..baded54
--- /dev/null
+++ b/src/mainboard/amd/torpedo/pmio.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h> /*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+ return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+ return pmio_read_index(PM2_INDEX, reg);
+}
+
diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h
new file mode 100755
index 0000000..207fdc2
--- /dev/null
+++ b/src/mainboard/amd/torpedo/pmio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX 0xCD6
+#define PM_DATA 0xCD7
+#define PM2_INDEX 0xCD0
+#define PM2_DATA 0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c
new file mode 100755
index 0000000..36bc6e0
--- /dev/null
+++ b/src/mainboard/amd/torpedo/reset.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h> /*inb, outb*/
+#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL 0x6C
+#define HTIC_BIOSR_Detect (1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+ u32 nodes;
+ u32 htic;
+ device_t dev;
+ int i;
+
+ nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+ for(i = 0; i < nodes; i++) {
+ dev = NODE_PCI(i, 0);
+ htic = pci_read_config32(dev, HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ }
+}
+
+void hard_reset(void)
+{
+ set_bios_reset();
+ /* Try rebooting through port 0xcf9 */
+ /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+ outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+ outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+ set_bios_reset();
+ /* link reset */
+ outb(0x06, 0x0cf9);
+}
+
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
new file mode 100755
index 0000000..317f697
--- /dev/null
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "agesawrapper.h"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "pc80/i8254.c"
+#include "pc80/i8259.c"
+#include "SbEarly.h"
+#include "SbPlatform.h"
+#include <arch/cpu.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ post_code(0x35);
+ val = agesawrapper_amdinitmmio();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ gpioEarlyInit();
+ sb_poweron_init();
+
+ post_code(0x31);
+
+ kbc1100_early_init(CONFIG_SIO_PORT);
+
+ post_code(0x32);
+ uart_init();
+ post_code(0x33);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ // Load MPB
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x36);
+ val = agesawrapper_amdinitreset();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+
+ post_code(0x37);
+ val = agesawrapper_amdinitearly ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+ post_code(0x38);
+ val = agesawrapper_amdinitpost ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+ post_code(0x39);
+ sb_before_pci_init ();
+ printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+
+ post_code(0x40);
+ val = agesawrapper_amdinitenv ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+ /* Initialize i8259 pic */
+ post_code(0x41);
+ setup_i8259 ();
+ printk(BIOS_DEBUG, "Got past setup_i8259\n");
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254 ();
+ printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
+ post_code(0x43);
+ copy_and_run(0);
+ printk(BIOS_DEBUG, "Got past copy_and_run\n");
+
+ post_code(0x44); // Should never see this post code.
+}
+
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