[coreboot] New patch to review: c8e2206 msrtool: added support for Intel CPUs
Anton kochkov (anton.kochkov@gmail.com)
gerrit at coreboot.org
Mon Jun 20 21:19:55 CEST 2011
Anton kochkov (anton.kochkov at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/50
-gerrit
commit c8e2206d38dd737e3c572202bfb0eb76a8ec8804
Author: Anton Kochkov <anton.kochkov at gmail.com>
Date: Mon Jun 20 23:14:22 2011 +0400
msrtool: added support for Intel CPUs
Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---
util/msrtool/intel_core1.c | 222 ++++++++++++++
util/msrtool/intel_core2_early.c | 237 +++++++++++++++
util/msrtool/intel_core2_later.c | 537 +++++++++++++++++++++++++++++++++
util/msrtool/intel_pentium3.c | 183 +++++++++++
util/msrtool/intel_pentium3_early.c | 258 ++++++++++++++++
util/msrtool/intel_pentium4_early.c | 570 +++++++++++++++++++++++++++++++++++
util/msrtool/intel_pentium4_later.c | 343 +++++++++++++++++++++
7 files changed, 2350 insertions(+), 0 deletions(-)
diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c
new file mode 100644
index 0000000..7cc52a6
--- /dev/null
+++ b/util/msrtool/intel_core1.c
@@ -0,0 +1,222 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_core1_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0x6 == id->family)&(0xe == id->model));
+}
+
+const struct msrdef intel_core1_msrs[] = {
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
+ { BITS_EOT }
+ }},
+ {0xce, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_VCC", "", {
+ { BITS_EOT }
+ }},
+ {0xe2, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_CST_CONFIG_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
+ { BITS_EOT }
+ }},
+ {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
+ { BITS_EOT }
+ }},
+ {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
+ { BITS_EOT }
+ }},
+ {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x15f, MSRTYPE_RDWR, MSR2(0,0), "DTS_CAL_CTRL", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ { BITS_EOT }
+ }},
+ {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ { BITS_EOT }
+ }},
+ {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x19d, MSRTYPE_RDWR, MSR2(0,0), "GV_THERM", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c
new file mode 100644
index 0000000..12c077c
--- /dev/null
+++ b/util/msrtool/intel_core2_early.c
@@ -0,0 +1,237 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_core2_early_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0x6 == id->family)&(0xf == id->model));
+}
+
+const struct msrdef intel_core2_early_msrs[] = {
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
+ { BITS_EOT }
+ }},
+ {0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", {
+ { BITS_EOT }
+ }},
+ {0xa9, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE1", "", {
+ { BITS_EOT }
+ }},
+ {0xaa, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE2", "", {
+ { BITS_EOT }
+ }},
+ {0xab, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE3", "", {
+ { BITS_EOT }
+ }},
+ {0xac, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE4", "", {
+ { BITS_EOT }
+ }},
+ {0xad, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE5", "", {
+ { BITS_EOT }
+ }},
+ {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
+ { BITS_EOT }
+ }},
+ {0xe2, MSRTYPE_RDWR, MSR2(0,0), "PMG_CST_CONFIG_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
+ { BITS_EOT }
+ }},
+ {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
+ { BITS_EOT }
+ }},
+ {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xe1, MSRTYPE_RDWR, MSR2(0,0), "SMM_CST_MISC_INFO", "", {
+ { BITS_EOT }
+ }},
+ {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
+ { BITS_EOT }
+ }},
+ {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ { BITS_EOT }
+ }},
+ {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c
new file mode 100644
index 0000000..7665b0f
--- /dev/null
+++ b/util/msrtool/intel_core2_later.c
@@ -0,0 +1,537 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_core2_later_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0x6 == id->family)&(0x17 == id->model));
+}
+
+const struct msrdef intel_core2_later_msrs[] = {
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", {
+ { 63, 11, RESERVED },
+ { 52, 3, RESERVED },
+ { 49, 37, RESERVED },
+ { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", PRESENT_DEC, {
+ { BITVAL_EOT }
+ }},
+ { 7, 8, RESERVED },
+ { BITS_EOT }
+ }},
+ { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", {
+ { 63, 41, RESERVED },
+ { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, {
+ { BITVAL_EOT }
+ }},
+ { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, {
+ { BITVAL_EOT }
+ }},
+ { 19, 1, RESERVED },
+ { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, {
+ { MSR1(0), "Integer ratio" },
+ { MSR1(1), "Non-integer ratio" },
+ { BITVAL_EOT }
+ }},
+ { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, {
+ { BITVAL_EOT }
+ }},
+ { 15, 1, RESERVED },
+ { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, {
+ { MSR1(0), "4 GBytes Power on Reset Vector" },
+ { MSR1(1), "1 Mbyte Power on Reset Vector" },
+ { BITVAL_EOT }
+ }},
+ { 13, 1, RESERVED },
+ { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, {
+ { MSR1(0), "BINIT# Observation disabled" },
+ { MSR1(1), "BINIT# Observation enabled" },
+ { BITVAL_EOT }
+ }},
+ { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, {
+ { MSR1(0), "Intel TXT Capable Chipset not present" },
+ { MSR1(1), "Intel TXT Capable Chipset present" },
+ { BITVAL_EOT }
+ }},
+ { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, {
+ { MSR1(0), "MCERR# Observation disabled" },
+ { MSR1(1), "MCERR# Observation enabled" },
+ { BITVAL_EOT }
+ }},
+ { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, {
+ { MSR1(0), "Execute BIST disabled" },
+ { MSR1(1), "Execute BIST enabled" },
+ { BITVAL_EOT }
+ }},
+ { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, {
+ { MSR1(0), "Output Tri-state disabled" },
+ { MSR1(1), "Output Tri-state enabled" },
+ { BITVAL_EOT }
+ }},
+ { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, {
+ { MSR1(0), "BINIT# Driver disabled" },
+ { MSR1(1), "BINIT# Driver enabled" },
+ { BITVAL_EOT }
+ }},
+ { 6, 2, RESERVED },
+ { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, {
+ { MSR1(0), "Address parity disabled" },
+ { MSR1(1), "Address parity enabled" },
+ { BITVAL_EOT }
+ }},
+ { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, {
+ { MSR1(0), "MCERR# Driver disabled" },
+ { MSR1(1), "MCERR# Driver enabled" },
+ { BITVAL_EOT }
+ }},
+ { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, {
+ { MSR1(0), "Response Error Checking disabled" },
+ { MSR1(1), "Response Error Checking enabled" },
+ { BITVAL_EOT }
+ }},
+ { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, {
+ { MSR1(0), "Data error checking disabled" },
+ { MSR1(1), "Data error checking enabled" },
+ { BITVAL_EOT }
+ }},
+ { 0, 1, RESERVED },
+ { BITS_EOT }
+ }},
+ {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", {
+ { BITS_EOT }
+ }},
+ {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+
+ // Per core msrs
+
+ {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
+ { BITS_EOT }
+ }},
+ {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", {
+ { BITS_EOT }
+ }},
+ {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
+ { BITS_EOT }
+ }},
+ {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", {
+ { BITS_EOT }
+ }},
+ {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", {
+ { BITS_EOT }
+ }},
+ {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", {
+ { BITS_EOT }
+ }},
+ {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", {
+ { BITS_EOT }
+ }},
+ {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
+ { BITS_EOT }
+ }},
+ {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
+ { BITS_EOT }
+ }},
+ {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
+ { BITS_EOT }
+ }},
+ {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", {
+ { BITS_EOT }
+ }},
+ {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ { BITS_EOT }
+ }},
+ {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ { BITS_EOT }
+ }},
+ {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ { BITS_EOT }
+ }},
+ {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "", {
+ { BITS_EOT }
+ }},
+ {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "", {
+ { BITS_EOT }
+ }},
+ {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "", {
+ { BITS_EOT }
+ }},
+ {0x345, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
+ { BITS_EOT }
+ }},
+ {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", "", {
+ { BITS_EOT }
+ }},
+ {0x38e, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x480, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_BASIC", "", {
+ { BITS_EOT }
+ }},
+ {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_PINBASED_CTLS", "", {
+ { BITS_EOT }
+ }},
+ {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_PROCBASED_CTLS", "", {
+ { BITS_EOT }
+ }},
+ {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", {
+ { BITS_EOT }
+ }},
+ {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", {
+ { BITS_EOT }
+ }},
+ {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x486, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED0", "", {
+ { BITS_EOT }
+ }},
+ {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", {
+ { BITS_EOT }
+ }},
+ {0x488, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED0", "", {
+ { BITS_EOT }
+ }},
+ {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", {
+ { BITS_EOT }
+ }},
+ {0x48a, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_VMCS_ENUM", "", {
+ { BITS_EOT }
+ }},
+ {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", {
+ { BITS_EOT }
+ }},
+ {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
+ { BITS_EOT }
+ }},
+ {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", {
+ { BITS_EOT }
+ }},
+ {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", {
+ { BITS_EOT }
+ }},
+ {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", {
+ { BITS_EOT }
+ }},
+ {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", {
+ { BITS_EOT }
+ }},
+ {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", {
+ { BITS_EOT }
+ }},
+ {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", {
+ { BITS_EOT }
+ }},
+ {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", {
+ { BITS_EOT }
+ }},
+ {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
+
+
diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c
new file mode 100644
index 0000000..3299808
--- /dev/null
+++ b/util/msrtool/intel_pentium3.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_pentium3_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0x6 == id->family)&((0xa == id->model)|(0xb == id->model)));
+}
+
+const struct msrdef intel_pentium3_msrs[] = {
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
+ { BITS_EOT }
+ }},
+ {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
+ { BITS_EOT }
+ }},
+ {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c
new file mode 100644
index 0000000..bae9500
--- /dev/null
+++ b/util/msrtool/intel_pentium3_early.c
@@ -0,0 +1,258 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_pentium3_early_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0x6 == id->family)&((0x7 == id->model)|(0x8 == id->model)));
+}
+
+const struct msrdef intel_pentium3_early_msrs[] = {
+ {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", {
+ { BITS_EOT }
+ }},
+ {0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", {
+ { BITS_EOT }
+ }},
+ {0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
+ { BITS_EOT }
+ }},
+ {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", {
+ { BITS_EOT }
+ }},
+ {0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", {
+ { BITS_EOT }
+ }},
+ {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+ { BITS_EOT }
+ }},
+ {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
+ { BITS_EOT }
+ }},
+ {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
+ { BITS_EOT }
+ }},
+ {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", {
+ { BITS_EOT }
+ }},
+ {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ { BITS_EOT }
+ }},
+ {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c
new file mode 100644
index 0000000..9b2165c
--- /dev/null
+++ b/util/msrtool/intel_pentium4_early.c
@@ -0,0 +1,570 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_pentium4_early_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0xf == id->family)&(0x2 == id->model));
+}
+
+const struct msrdef intel_pentium4_early_msrs[] = {
+ {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", {
+ { BITS_EOT }
+ }},
+ {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", {
+ { BITS_EOT }
+ }},
+ {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", {
+ { BITS_EOT }
+ }},
+ {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", {
+ { BITS_EOT }
+ }},
+ {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", {
+ { BITS_EOT }
+ }},
+ {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", {
+ { BITS_EOT }
+ }},
+ {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", {
+ { BITS_EOT }
+ }},
+ {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", {
+ { BITS_EOT }
+ }},
+ {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", {
+ { BITS_EOT }
+ }},
+ {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", {
+ { BITS_EOT }
+ }},
+ {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", {
+ { BITS_EOT }
+ }},
+ {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", {
+ { BITS_EOT }
+ }},
+ {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", {
+ { BITS_EOT }
+ }},
+ {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", {
+ { BITS_EOT }
+ }},
+ {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", {
+ { BITS_EOT }
+ }},
+ {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", {
+ { BITS_EOT }
+ }},
+ {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", {
+ { BITS_EOT }
+ }},
+ {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", {
+ { BITS_EOT }
+ }},
+ {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", {
+ { BITS_EOT }
+ }},
+ {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", {
+ { BITS_EOT }
+ }},
+ {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", {
+ { BITS_EOT }
+ }},
+ {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", {
+ { BITS_EOT }
+ }},
+ {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", {
+ { BITS_EOT }
+ }},
+ {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", {
+ { BITS_EOT }
+ }},
+ {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", {
+ { BITS_EOT }
+ }},
+ {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", {
+ { BITS_EOT }
+ }},
+ {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", {
+ { BITS_EOT }
+ }},
+ {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", {
+ { BITS_EOT }
+ }},
+ {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", {
+ { BITS_EOT }
+ }},
+ {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", {
+ { BITS_EOT }
+ }},
+ {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", {
+ { BITS_EOT }
+ }},
+ {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", {
+ { BITS_EOT }
+ }},
+ {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", {
+ { BITS_EOT }
+ }},
+ {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", {
+ { BITS_EOT }
+ }},
+ {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", {
+ { BITS_EOT }
+ }},
+ {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", {
+ { BITS_EOT }
+ }},
+ {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
+ { BITS_EOT }
+ }},
+ {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
+ { BITS_EOT }
+ }},
+ {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", {
+ { BITS_EOT }
+ }},
+ {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", {
+ { BITS_EOT }
+ }},
+ {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", {
+ { BITS_EOT }
+ }},
+ {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", {
+ { BITS_EOT }
+ }},
+ {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", {
+ { BITS_EOT }
+ }},
+ {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", {
+ { BITS_EOT }
+ }},
+ {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", {
+ { BITS_EOT }
+ }},
+ {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", {
+ { BITS_EOT }
+ }},
+ {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", {
+ { BITS_EOT }
+ }},
+ {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", {
+ { BITS_EOT }
+ }},
+ {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", {
+ { BITS_EOT }
+ }},
+ {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", {
+ { BITS_EOT }
+ }},
+ {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", {
+ { BITS_EOT }
+ }},
+ {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", {
+ { BITS_EOT }
+ }},
+ {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", {
+ { BITS_EOT }
+ }},
+ {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", {
+ { BITS_EOT }
+ }},
+ {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", {
+ { BITS_EOT }
+ }},
+ {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ { BITS_EOT }
+ }},
+ {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", {
+ { BITS_EOT }
+ }},
+ {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
+ { BITS_EOT }
+ }},
+ {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", {
+ { BITS_EOT }
+ }},
+ {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", {
+ { BITS_EOT }
+ }},
+ {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", {
+ { BITS_EOT }
+ }},
+ {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
+ { BITS_EOT }
+ }},
+ {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c
new file mode 100644
index 0000000..c94e47c
--- /dev/null
+++ b/util/msrtool/intel_pentium4_later.c
@@ -0,0 +1,343 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2008-2011 by coresystems GmbH
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov at gmail.com>`
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_pentium4_later_probe(const struct targetdef *target) {
+ struct cpuid_t *id = cpuid();
+ return ((0xf == id->family)&((0x3 == id->model)|(0x4 == id->model)));
+}
+
+const struct msrdef intel_pentium4_later_msrs[] = {
+ {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
+ { BITS_EOT }
+ }},
+ {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
+ { BITS_EOT }
+ }},
+ {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", {
+ { BITS_EOT }
+ }},
+ {0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", {
+ { BITS_EOT }
+ }},
+ {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ { BITS_EOT }
+ }},
+ {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ { BITS_EOT }
+ }},
+ {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ { BITS_EOT }
+ }},
+ {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ { BITS_EOT }
+ }},
+ {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ { BITS_EOT }
+ }},
+ {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ { BITS_EOT }
+ }},
+ {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ { BITS_EOT }
+ }},
+ {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ { BITS_EOT }
+ }},
+ {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ { BITS_EOT }
+ }},
+ {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ { BITS_EOT }
+ }},
+ {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ { BITS_EOT }
+ }},
+ {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ { BITS_EOT }
+ }},
+ {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ { BITS_EOT }
+ }},
+ {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ { BITS_EOT }
+ }},
+ {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ { BITS_EOT }
+ }},
+ {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ { BITS_EOT }
+ }},
+ {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ { BITS_EOT }
+ }},
+ {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ { BITS_EOT }
+ }},
+ {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ { BITS_EOT }
+ }},
+ {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ { BITS_EOT }
+ }},
+ {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ { BITS_EOT }
+ }},
+ {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ { BITS_EOT }
+ }},
+ {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ { BITS_EOT }
+ }},
+ {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ { BITS_EOT }
+ }},
+ {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", {
+ { BITS_EOT }
+ }},
+ {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", {
+ { BITS_EOT }
+ }},
+ {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", {
+ { BITS_EOT }
+ }},
+ {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", {
+ { BITS_EOT }
+ }},
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ { BITS_EOT }
+ }},
+ {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ { BITS_EOT }
+ }},
+ {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ { BITS_EOT }
+ }},
+ {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
+ { BITS_EOT }
+ }},
+ {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ { BITS_EOT }
+ }},
+ {0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ { BITS_EOT }
+ }},
+ {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
+ { BITS_EOT }
+ }},
+ {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
+ { BITS_EOT }
+ }},
+ {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
+ { BITS_EOT }
+ }},
+ {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ { BITS_EOT }
+ }},
+ {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", {
+ { BITS_EOT }
+ }},
+ {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", {
+ { BITS_EOT }
+ }},
+ {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", {
+ { BITS_EOT }
+ }},
+ {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", {
+ { BITS_EOT }
+ }},
+ {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", {
+ { BITS_EOT }
+ }},
+ {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", {
+ { BITS_EOT }
+ }},
+ {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", {
+ { BITS_EOT }
+ }},
+ {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", {
+ { BITS_EOT }
+ }},
+ {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", {
+ { BITS_EOT }
+ }},
+ {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", {
+ { BITS_EOT }
+ }},
+ {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", {
+ { BITS_EOT }
+ }},
+ {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", {
+ { BITS_EOT }
+ }},
+ {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", {
+ { BITS_EOT }
+ }},
+ {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", {
+ { BITS_EOT }
+ }},
+ {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", {
+ { BITS_EOT }
+ }},
+ {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", {
+ { BITS_EOT }
+ }},
+ {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", {
+ { BITS_EOT }
+ }},
+ {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", {
+ { BITS_EOT }
+ }},
+ {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", {
+ { BITS_EOT }
+ }},
+ {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ { BITS_EOT }
+ }},
+ {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
+ { BITS_EOT }
+ }},
+ {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ { BITS_EOT }
+ }},
+ {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ { BITS_EOT }
+ }},
+ {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
+ { BITS_EOT }
+ }},
+ {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
+ { BITS_EOT }
+ }},
+ {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", {
+ { BITS_EOT }
+ }},
+ {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
+ { BITS_EOT }
+ }},
+ {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
+ { BITS_EOT }
+ }},
+ {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
+ { BITS_EOT }
+ }},
+ { MSR_EOT }
+};
+
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