[coreboot] ASRock E350M1: Boot delay with debug enabled, system RAM reported incorrectly in Linux
peter at stuge.se
Sun Jun 19 22:05:49 CEST 2011
Scott Duplichan wrote:
> The real problem is that the asl code for \_SB.PCI0._CRS is using
> uninitialized variable TOM1. The default value of aaaaaaaa from
> from line 267 of family14/ssdt.asl is being used.
Good find. Many thanks Scott.
> Somehow the OS does need to know where the PCI hole can safely start.
> It can't start immediately after the end of low ram because of uma.
> \_SB.PCI0._CRS is one way to pass this information. This method
> requires passing data from coreboot to asl, which is a pain.
Is it neccessarily that bad? Rudolf has developed some functions to
build AML at coreboot run time. It sounds like they might help?
> I wonder if just reserving the uma range in the e820 map is
> sufficient? I will try to do some experiments tonight.
Maybe short term, but the only real solution is indeed to store the
correct value from coreboot processing into AML.
> If you can send me a binary or otherwise let me recreate the serial
> logging problem, I will take a look.
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