[coreboot] Patch merged into master: d22355c ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic

gerrit at coreboot.org gerrit at coreboot.org
Sun Jun 19 02:50:33 CEST 2011

the following patch was just integrated into master:
commit d22355cefabca65598a37ef8e0438d89c382174d
Author: Scott Duplichan <scott at notabs.org>
Date:   Sat Jun 18 10:46:45 2011 -0500

    ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
    Scott Duplichan's patch from the mailing list:
    sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
    once, after determining device 0x15 function enables.
    1) Update the asrock e350m1 devicetree.cb to match the hardware.
    2) Change the way the sb800 cimx wrapper code works. The original
    cimx code calls sb800 cimx function sbBeforePciInit() once. When
    ported to coreboot, the gpp component of this function was called
    once for each gpp port, as the gpp port's enable/disable state
    became known. A 05/15/2011 change makes the early gpp code run
    only once, triggered by processing the 4th gpp port. This method
    is not general enough because the 4th gpp port is not enabled on
    all boards. With the current change, the early gpp code runs when
    the first gpp port is processed. If any gpp ports are enabled, the
    first must be enabled. Tested with Win7 and linux on asrock e350m1.
    This change will also affect amd inagua, and has not been tested
    on that board.
    Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
    Signed-off-by: Scott Duplichan <scott at notabs.org>
    Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>

See http://review.coreboot.org/44 for details.


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