[coreboot] [PATCH] asrock e350m1: configure sb800 gpp ports to support onboard pcie nic

Scott Duplichan scott at notabs.org
Sat Jun 18 06:26:05 CEST 2011

The attached patch allows the asrock e350m1 onboard nic to work.
1) Update the asrock e350m1 devicetree.cb to match the hardware.
2) Change the way the sb800 cimx wrapper code works. The original
cimx code calls sb800 cimx function sbBeforePciInit() once. When
ported to coreboot, the gpp component of this function was called
once for each gpp port, as the gpp port's enable/disable state
became known. A 05/15/2011 change makes the early gpp code run 
only once, triggered by processing the 4th gpp port. This method
is not general enough because the 4th gpp port is not enabled on
all boards. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.

Signed-off-by: Scott Duplichan <scott at notabs.org>

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