[coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1

Stefan Reinauer stefan.reinauer at coreboot.org
Sat Jun 4 18:12:26 CEST 2011


* repository service <svn at coreboot.org> [110604 17:44]:
> Author: stuge
> Date: Sat Jun  4 17:44:31 2011
> New Revision: 6625
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
> 
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:14 2011	(r6624)
> +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
> @@ -47,6 +47,19 @@
>    u32 val;
>    u8 reg8;
>  
> +  // early enable of SPI 33 MHz fast mode read
> +  if (boot_cpu())
> +    {
> +    volatile u32 *spiBase = (void *) 0xa0000000;
> +    u32 save;
> +    __outdword (0xcf8, 0x8000a3a0);

what's the reason to not use pci_read_config32() here?

> +    save = __indword (0xcfc);
> +    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
> +    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
> +    spiBase [0] |= 1 << 18; // fast read enable
> +    __outdword (0xcfc, save); // clear temp base
> +    }
> +
>    if (!cpu_init_detectedx && boot_cpu()) {
>      post_code(0x30);
>      sb_poweron_init();
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 




More information about the coreboot mailing list