[coreboot] New patch to review: ba66858 Add xhcbios and ahcibios rom handling
Frank Vibrans III (efdesign98@gmail.com)
gerrit at coreboot.org
Sat Jul 16 02:11:53 CEST 2011
Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/109
-gerrit
commit ba66858bbb5708c1add2aab61f70106154132b4e
Author: efdesign98 <efdesign98 at gmail.com>
Date: Fri Jul 15 17:10:43 2011 -0700
Add xhcbios and ahcibios rom handling
This change adds to the arch/x86 Makefile.inc, handling
for xhci and ahci bios roms that is similar to the handling
of vgabios roms. It also correct a comment in the lapic_
cpu)init.c file.
Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
src/arch/x86/Makefile.inc | 10 ++++++++++
src/cpu/x86/lapic/lapic_cpu_init.c | 33 ++++++++++++++++++++++++++++++++-
2 files changed, 42 insertions(+), 1 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
old mode 100644
new mode 100755
index e9c00de..cf41055
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -25,6 +25,11 @@ subdirs-y += boot
subdirs-y += lib
subdirs-y += smp
+stripped_xhcbios_id = $(call strip_quotes,$(CONFIG_XHC_BIOS_ID))
+cbfs-files-$(CONFIG_XHC_BIOS) += pci$(stripped_xhcbios_id).rom
+pci$(stripped_xhcbios_id).rom-file := $(call strip_quotes,$(CONFIG_XHC_BIOS_FILE))
+pci$(stripped_xhcbios_id).rom-type := optionrom
+
OPTION_TABLE_H:=
ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
cbfs-files-y += cmos_layout.bin
@@ -115,6 +120,11 @@ cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom
pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))
pci$(stripped_vgabios_id).rom-type := optionrom
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+
cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin
mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))
mbi.bin-type := mbi
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
old mode 100644
new mode 100755
index 53bbe79..53ea60d
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -262,7 +262,7 @@ int start_cpu(device_t cpu)
if (result) {
result = 0;
- /* Wait 1s or until the new the new cpu calls in */
+ /* Wait 1s or until the new cpu calls in */
for(count = 0; count < 100000 ; count++) {
if (secondary_stack == 0) {
result = 1;
@@ -338,6 +338,26 @@ void stop_this_cpu(void)
}
#endif
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr4"
+ :
+ : "a" (Data)
+ );
+}
+#endif
+
/* C entry point of secondary cpus */
void secondary_cpu_init(void)
{
@@ -347,6 +367,17 @@ void secondary_cpu_init(void)
spin_lock(&start_cpu_lock);
#endif
#endif
+
+#ifdef __SSE3__
+ /*
+ * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+ * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+ */
+ u32 cr4_val;
+ cr4_val = readcr4();
+ cr4_val |= (1 << 9 | 1 << 10);
+ writecr4(cr4_val);
+#endif
cpu_initialize();
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
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