[coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock

Pete Batard pete at akeo.ie
Fri Jul 15 01:35:39 CEST 2011


> On 2011.07.12 02:38, Scott Duplichan wrote:
>> I tried the
>> sample on ASRock E350M1 and it did not work. One reason is needed LPC
>> clock initialization (http://permalink.gmane.org/gmane.linux.bios/67229).

Hi Scott,

With my apologies for the delay, I have just pushed an updated version 
of ubrx to svn. It includes SB8x0 48 MHz Clk1 init, the ability to 
provide of SIO base, type and UART LDN, as well as additional DIAG codes 
to help with the troubleshooting.

If you want to give it a try again, you can fetch it from:
   svn checkout http://akeo.googlecode.com/svn/ubrx ubrx
or just update if you already checked out.

The options of interest to you should be at the top of bios.S.
First of all, you will need to enable SB800_48MHZ_INIT (set it to 1) for 
your platform.

I will also invite you to uncomment and set the 
SUPERIO_BASE/UART_LDN/TYPE values according to your board, as well as 
disable VMWARE_SUPPORT, so that we can get relevant diagnostic values. 
Note that not all checks are disabled, when providing base/type/LDN, 
especially the full 16550 check still occurs. However, the extra POST 
codes should tell us which test is failing.

As you may also see from the code, the MMIO mapping for the Misc. 
Register is done using address 0008_0000h as a base (page 8000h), which 
I would expect to be and not mapped to anything else after reset in real 
mode, but that you can try to change if you see 0xFE as a POST code. If 
you can't get past the 0xFE POST code, that means there's either a bug 
or a design issue with my current MMIO mapping for SB8x0.

Any testing you can perform will be much appreciated!

Regards,

/Pete




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