[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
buurin at gmail.com
Mon Jan 31 18:53:05 CET 2011
On Fri, Jan 14, 2011 at 3:47 AM, Roger <rogerx.oss at gmail.com> wrote:
> On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
>>Here is the new L2 cache patch. Sign-off in the patch itself. Still
>>very juicy and tasty at 25k. :D
>>Also done is including cpu/intel/model_68x again in slot_1. Otherwise
>>it will die with a Coppermine P3 installed.
>>My boot log on P2B-LS and a Katmai 600MHz attached.
>>I have optimized it some more, and added more information and
>>meaningful constants as I cross checked the code with Intel's
>>documentation. Some debugging messages are different too. Give this a
> Acked-by: Roger Zauner <rogerx.oss at gmail.com>
> Wondering if people are still waiting for acked-by. ... acked it, code compiles
> for my "Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host
> bridge", but have Coppermine CPU's so the code is ignored.
Also wondering the status of this.
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