[coreboot] [patch] AMDMCT DDR3 fix Dual rank + high mem frequency.

[Bao, Zheng]

For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao at amd.com>

Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(revision 6275)
+++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(working copy)
@@ -306,7 +306,7 @@
 				if (!(pDCTstat->Status & (1 <<
SB_Registered)))
 					break; /* For UDIMM, only send
MR commands once per channel */
 		}
-		if (pDCTstat->LogicalCPUID & (AMD_DR_Cx/* | AMD_RB_C0
*/)) /* We dont support RB_C0 now. need to be added and tested. */
+		if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0
*/)) /* We dont support RB_C0 now. need to be added and tested. */
 			if (!(pDCTstat->Status & (1 << SB_Registered)))
 				MrsChipSel ++;
 	}
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