[coreboot] [commit] r6237 - in trunk/src/southbridge/amd/cimx_wrapper: . sb800
repository service
svn at coreboot.org
Sun Jan 2 00:36:04 CET 2011
Author: uwe
Date: Sun Jan 2 00:36:03 2011
New Revision: 6237
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6237
Log:
src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified:
trunk/src/southbridge/amd/cimx_wrapper/Kconfig
trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc
trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h
trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
Modified: trunk/src/southbridge/amd/cimx_wrapper/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:30:37 2011 (r6236)
+++ trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:36:03 2011 (r6237)
@@ -16,14 +16,15 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-#
+
config SOUTHBRIDGE_AMD_CIMX_WRAPPER
- bool
- default n
+ bool
+ default n
config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
- bool
- select IOAPIC
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER
+ bool
+ select IOAPIC
+ select SOUTHBRIDGE_AMD_CIMX_WRAPPER
source src/southbridge/amd/cimx_wrapper/sb800/Kconfig
+
Modified: trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:30:37 2011 (r6236)
+++ trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:36:03 2011 (r6237)
@@ -16,4 +16,6 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800
+
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:30:37 2011 (r6236)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:36:03 2011 (r6237)
@@ -1,375 +1,375 @@
-/*****************************************************************************
- * AMD Generic Encapsulated Software Architecture */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA/CIMx core interface
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Include
- * @e \$Revision:$ @e \$Date:$
- */
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-// AGESA Types and Definitions
-
-#ifndef NULL
- #define NULL 0
-#endif
-
-#define LAST_ENTRY 0xFFFFFFFF
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-#define IN
-#define OUT
-#define IMAGE_SIGNATURE 'DMA$'
-
-typedef UINTN AGESA_STATUS;
-
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
-#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
-#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
-#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
-#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
-#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
-#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
-
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
- PreMemHeap = 0, ///< Create heap in cache.
- PostMemDram, ///< Create heap in memory.
- ByHost ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
- AccessWidth8 = 1, ///< Access width is 8 bits.
- AccessWidth16, ///< Access width is 16 bits.
- AccessWidth32, ///< Access width is 32 bits.
- AccessWidth64, ///< Access width is 64 bits.
-
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
- AccessS3SaveWidth16, ///< Save 16 bits data.
- AccessS3SaveWidth32, ///< Save 32 bits data.
- AccessS3SaveWidth64, ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-typedef struct _AMD_CONFIG_PARAMS {
- IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
- IN UINT32 Func; ///< The service desired, @sa dispatch.h.
- IN UINT32 AltImageBasePtr; ///< Alternate Image location
- IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured.
- union { ///< Callback pointer
- IN UINT64 PlaceHolder; ///< Place holder
- IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
- } CALLBACK;
- IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-
-/// AGESA Binary module header structure
-typedef struct _AMD_IMAGE_HEADER {
- IN UINT32 Signature; ///< Binary Signature
- IN CHAR8 CreatorID[8]; ///< 8 characters ID
- IN CHAR8 Version[12]; ///< 12 characters version
- IN UINT32 ModuleInfoOffset; ///< Offset of module
- IN UINT32 EntryPointAddress; ///< Entry address
- IN UINT32 ImageBase; ///< Image base
- IN UINT32 RelocTableOffset; ///< Relocate Table offset
- IN UINT32 ImageSize; ///< Size
- IN UINT16 Checksum; ///< Checksum
- IN UINT8 ImageType; ///< Type
- IN UINT8 V_Reserved; ///< Reserved
-} AMD_IMAGE_HEADER;
-
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
- IN UINT32 ModuleHeaderSignature; ///< Module signature
- IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
- IN CHAR8 ModuleVersion[12]; ///< 12 characters version
- IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
- IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
-} AMD_MODULE_HEADER;
-
-#define FUNC_0 0 // bit-placed for PCI address creation
-#define FUNC_1 1
-#define FUNC_2 2
-#define FUNC_3 3
-#define FUNC_4 4
-#define FUNC_5 5
-#define FUNC_6 6
-#define FUNC_7 7
-
-// SBDFO - Segment Bus Device Function Offset
-// 31:28 Segment (4-bits)
-// 27:20 Bus (8-bits)
-// 19:15 Device (5-bits)
-// 14:12 Function (3-bits)
-// 11:00 Offset (12-bits)
-
-#if 0
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
- (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off)))
-#endif
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
- IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
- IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
- IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
- IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
-} SB_CPUID_DATA;
-
-#define WARM_RESET 1
-#define COLD_RESET 2 // Cold reset
-#define RESET_CPU 4 // Triggers a CPU reset
-
-/// HT frequency for external callbacks
-typedef enum {
- HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
- HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
- HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
- HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
- HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
-} HT_FREQUENCIES;
-
-#ifndef BIT0
- #define BIT0 0x0000000000000001ull
-#endif
-#ifndef BIT1
- #define BIT1 0x0000000000000002ull
-#endif
-#ifndef BIT2
- #define BIT2 0x0000000000000004ull
-#endif
-#ifndef BIT3
- #define BIT3 0x0000000000000008ull
-#endif
-#ifndef BIT4
- #define BIT4 0x0000000000000010ull
-#endif
-#ifndef BIT5
- #define BIT5 0x0000000000000020ull
-#endif
-#ifndef BIT6
- #define BIT6 0x0000000000000040ull
-#endif
-#ifndef BIT7
- #define BIT7 0x0000000000000080ull
-#endif
-#ifndef BIT8
- #define BIT8 0x0000000000000100ull
-#endif
-#ifndef BIT9
- #define BIT9 0x0000000000000200ull
-#endif
-#ifndef BIT10
- #define BIT10 0x0000000000000400ull
-#endif
-#ifndef BIT11
- #define BIT11 0x0000000000000800ull
-#endif
-#ifndef BIT12
- #define BIT12 0x0000000000001000ull
-#endif
-#ifndef BIT13
- #define BIT13 0x0000000000002000ull
-#endif
-#ifndef BIT14
- #define BIT14 0x0000000000004000ull
-#endif
-#ifndef BIT15
- #define BIT15 0x0000000000008000ull
-#endif
-#ifndef BIT16
- #define BIT16 0x0000000000010000ull
-#endif
-#ifndef BIT17
- #define BIT17 0x0000000000020000ull
-#endif
-#ifndef BIT18
- #define BIT18 0x0000000000040000ull
-#endif
-#ifndef BIT19
- #define BIT19 0x0000000000080000ull
-#endif
-#ifndef BIT20
- #define BIT20 0x0000000000100000ull
-#endif
-#ifndef BIT21
- #define BIT21 0x0000000000200000ull
-#endif
-#ifndef BIT22
- #define BIT22 0x0000000000400000ull
-#endif
-#ifndef BIT23
- #define BIT23 0x0000000000800000ull
-#endif
-#ifndef BIT24
- #define BIT24 0x0000000001000000ull
-#endif
-#ifndef BIT25
- #define BIT25 0x0000000002000000ull
-#endif
-#ifndef BIT26
- #define BIT26 0x0000000004000000ull
-#endif
-#ifndef BIT27
- #define BIT27 0x0000000008000000ull
-#endif
-#ifndef BIT28
- #define BIT28 0x0000000010000000ull
-#endif
-#ifndef BIT29
- #define BIT29 0x0000000020000000ull
-#endif
-#ifndef BIT30
- #define BIT30 0x0000000040000000ull
-#endif
-#ifndef BIT31
- #define BIT31 0x0000000080000000ull
-#endif
-#ifndef BIT32
- #define BIT32 0x0000000100000000ull
-#endif
-#ifndef BIT33
- #define BIT33 0x0000000200000000ull
-#endif
-#ifndef BIT34
- #define BIT34 0x0000000400000000ull
-#endif
-#ifndef BIT35
- #define BIT35 0x0000000800000000ull
-#endif
-#ifndef BIT36
- #define BIT36 0x0000001000000000ull
-#endif
-#ifndef BIT37
- #define BIT37 0x0000002000000000ull
-#endif
-#ifndef BIT38
- #define BIT38 0x0000004000000000ull
-#endif
-#ifndef BIT39
- #define BIT39 0x0000008000000000ull
-#endif
-#ifndef BIT40
- #define BIT40 0x0000010000000000ull
-#endif
-#ifndef BIT41
- #define BIT41 0x0000020000000000ull
-#endif
-#ifndef BIT42
- #define BIT42 0x0000040000000000ull
-#endif
-#ifndef BIT43
- #define BIT43 0x0000080000000000ull
-#endif
-#ifndef BIT44
- #define BIT44 0x0000100000000000ull
-#endif
-#ifndef BIT45
- #define BIT45 0x0000200000000000ull
-#endif
-#ifndef BIT46
- #define BIT46 0x0000400000000000ull
-#endif
-#ifndef BIT47
- #define BIT47 0x0000800000000000ull
-#endif
-#ifndef BIT48
- #define BIT48 0x0001000000000000ull
-#endif
-#ifndef BIT49
- #define BIT49 0x0002000000000000ull
-#endif
-#ifndef BIT50
- #define BIT50 0x0004000000000000ull
-#endif
-#ifndef BIT51
- #define BIT51 0x0008000000000000ull
-#endif
-#ifndef BIT52
- #define BIT52 0x0010000000000000ull
-#endif
-#ifndef BIT53
- #define BIT53 0x0020000000000000ull
-#endif
-#ifndef BIT54
- #define BIT54 0x0040000000000000ull
-#endif
-#ifndef BIT55
- #define BIT55 0x0080000000000000ull
-#endif
-#ifndef BIT56
- #define BIT56 0x0100000000000000ull
-#endif
-#ifndef BIT57
- #define BIT57 0x0200000000000000ull
-#endif
-#ifndef BIT58
- #define BIT58 0x0400000000000000ull
-#endif
-#ifndef BIT59
- #define BIT59 0x0800000000000000ull
-#endif
-#ifndef BIT60
- #define BIT60 0x1000000000000000ull
-#endif
-#ifndef BIT61
- #define BIT61 0x2000000000000000ull
-#endif
-#ifndef BIT62
- #define BIT62 0x4000000000000000ull
-#endif
-#ifndef BIT63
- #define BIT63 0x8000000000000000ull
-#endif
-
-#endif
+/*****************************************************************************
+ * AMD Generic Encapsulated Software Architecture */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA/CIMx core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision:$ @e \$Date:$
+ */
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+// AGESA Types and Definitions
+
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+#define IMAGE_SIGNATURE 'DMA$'
+
+typedef UINTN AGESA_STATUS;
+
+#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+typedef struct _AMD_CONFIG_PARAMS {
+ IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
+ IN UINT32 Func; ///< The service desired, @sa dispatch.h.
+ IN UINT32 AltImageBasePtr; ///< Alternate Image location
+ IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured.
+ union { ///< Callback pointer
+ IN UINT64 PlaceHolder; ///< Place holder
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ } CALLBACK;
+ IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version
+ IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function (3-bits)
+// 11:00 Offset (12-bits)
+
+#if 0
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+ (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off)))
+#endif
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+ IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
+ IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
+ IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
+ IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+
+#define WARM_RESET 1
+#define COLD_RESET 2 // Cold reset
+#define RESET_CPU 4 // Triggers a CPU reset
+
+/// HT frequency for external callbacks
+typedef enum {
+ HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
+ HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
+ HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
+ HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
+ HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
+ HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
+ HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
+ HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
+ HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
+ HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
+ HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
+ HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
+ HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
+ HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
+ HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
+ HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+
+#endif
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:30:37 2011 (r6236)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:36:03 2011 (r6237)
@@ -1,174 +1,174 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_SB_LIB_H_
-#define _AMD_SB_LIB_H_
-
-typedef CHAR8 *va_list;
-#ifndef _INTSIZEOF
- #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
-#endif
-
-// Also support coding convention rules for var arg macros
-#ifndef va_start
- #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )
-#endif
-#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
-#define va_end(ap) ( ap = (va_list)0 )
-
-#pragma pack (push, 1)
-
-#define IMAGE_ALIGN 32*1024
-#define NUM_IMAGE_LOCATION 32
-
-//Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
-
-//Hook Call
-
-typedef struct _CIMFILEHEADER
-{
- UINT32 AMDLogo;
- UINT64 CreatorID;
- UINT32 Version1;
- UINT32 Version2;
- UINT32 Version3;
- UINT32 ModuleInfoOffset;
- UINT32 EntryPoint;
- UINT32 ImageBase;
- UINT32 RelocTableOffset;
- UINT32 ImageSize;
- UINT16 CheckSum;
- UINT8 ImageType;
- UINT8 Reserved2;
-} CIMFILEHEADER;
-
-#ifndef BIT0
- #define BIT0 (1 << 0)
-#endif
-#ifndef BIT1
- #define BIT1 (1 << 1)
-#endif
-#ifndef BIT2
- #define BIT2 (1 << 2)
-#endif
-#ifndef BIT3
- #define BIT3 (1 << 3)
-#endif
-#ifndef BIT4
- #define BIT4 (1 << 4)
-#endif
-#ifndef BIT5
- #define BIT5 (1 << 5)
-#endif
-#ifndef BIT6
- #define BIT6 (1 << 6)
-#endif
-#ifndef BIT7
- #define BIT7 (1 << 7)
-#endif
-#ifndef BIT8
- #define BIT8 (1 << 8)
-#endif
-#ifndef BIT9
- #define BIT9 (1 << 9)
-#endif
-#ifndef BIT10
- #define BIT10 (1 << 10)
-#endif
-#ifndef BIT11
- #define BIT11 (1 << 11)
-#endif
-#ifndef BIT12
- #define BIT12 (1 << 12)
-#endif
-#ifndef BIT13
- #define BIT13 (1 << 13)
-#endif
-#ifndef BIT14
- #define BIT14 (1 << 14)
-#endif
-#ifndef BIT15
- #define BIT15 (1 << 15)
-#endif
-#ifndef BIT16
- #define BIT16 (1 << 16)
-#endif
-#ifndef BIT17
- #define BIT17 (1 << 17)
-#endif
-#ifndef BIT18
- #define BIT18 (1 << 18)
-#endif
-#ifndef BIT19
- #define BIT19 (1 << 19)
-#endif
-#ifndef BIT20
- #define BIT20 (1 << 20)
-#endif
-#ifndef BIT21
- #define BIT21 (1 << 21)
-#endif
-#ifndef BIT22
- #define BIT22 (1 << 22)
-#endif
-#ifndef BIT23
- #define BIT23 (1 << 23)
-#endif
-#ifndef BIT24
- #define BIT24 (1 << 24)
-#endif
-#ifndef BIT25
- #define BIT25 (1 << 25)
-#endif
-#ifndef BIT26
- #define BIT26 (1 << 26)
-#endif
-#ifndef BIT27
- #define BIT27 (1 << 27)
-#endif
-#ifndef BIT28
- #define BIT28 (1 << 28)
-#endif
-#ifndef BIT29
- #define BIT29 (1 << 29)
-#endif
-#ifndef BIT30
- #define BIT30 (1 << 30)
-#endif
-#ifndef BIT31
- #define BIT31 (1 << 31)
-#endif
-
-#pragma pack (pop)
-
-typedef enum
-{
- AccWidthUint8 = 0,
- AccWidthUint16,
- AccWidthUint32,
-} ACC_WIDTH;
-
-#define S3_SAVE 0x80
-
-#endif
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SB_LIB_H_
+#define _AMD_SB_LIB_H_
+
+typedef CHAR8 *va_list;
+#ifndef _INTSIZEOF
+ #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+ #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )
+#endif
+#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+
+#pragma pack (push, 1)
+
+#define IMAGE_ALIGN 32*1024
+#define NUM_IMAGE_LOCATION 32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+
+//Hook Call
+
+typedef struct _CIMFILEHEADER
+{
+ UINT32 AMDLogo;
+ UINT64 CreatorID;
+ UINT32 Version1;
+ UINT32 Version2;
+ UINT32 Version3;
+ UINT32 ModuleInfoOffset;
+ UINT32 EntryPoint;
+ UINT32 ImageBase;
+ UINT32 RelocTableOffset;
+ UINT32 ImageSize;
+ UINT16 CheckSum;
+ UINT8 ImageType;
+ UINT8 Reserved2;
+} CIMFILEHEADER;
+
+#ifndef BIT0
+ #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+ #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+ #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+ #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+ #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+ #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+ #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+ #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+ #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+ #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+ #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+ #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+ #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+ #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+ #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+ #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+ #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+ #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+ #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+ #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+ #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+ #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+ #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+ #define BIT23 (1 << 23)
+#endif
+#ifndef BIT24
+ #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+ #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+ #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+ #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+ #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+ #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+ #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+ #define BIT31 (1 << 31)
+#endif
+
+#pragma pack (pop)
+
+typedef enum
+{
+ AccWidthUint8 = 0,
+ AccWidthUint16,
+ AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE 0x80
+
+#endif
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:30:37 2011 (r6236)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:36:03 2011 (r6237)
@@ -1,153 +1,153 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_SBPLATFORM_H_
-#define _AMD_SBPLATFORM_H_
-
-#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>
-typedef UINT64 PLACEHOLDER;
-#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>
-#include <southbridge/amd/cimx_wrapper/sb800/Amd.h>
-#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper
-#include <vendorcode/amd/cimx/sb800/SB800.h>
-#include <vendorcode/amd/cimx/sb800/SBTYPE.h>
-#include <vendorcode/amd/cimx/sb800/ACPILIB.h>
-#include <vendorcode/amd/cimx/sb800/SBDEF.h>
-#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
-#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>
-#include <vendorcode/amd/cimx/sb800/OEM.h>
-
-#ifdef NULL
- #undef NULL
-#endif
-#define NULL 0
-
-#ifndef SBOEM_ACPI_RESTORE_SWSMI
- #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
- #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
-#endif
-
-#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
-
-/// Extended PCI Address
-typedef struct _EXT_PCI_ADDR {
- UINT32 Reg :16; ///< / PCI Register
- UINT32 Func:3; ///< / PCI Function
- UINT32 Dev :5; ///< / PCI Device
- UINT32 Bus :8; ///< / PCI Address
-} EXT_PCI_ADDR;
-
-/// PCI Address
-typedef union _PCI_ADDR {
- UINT32 ADDR; ///< / 32 bit Address
- EXT_PCI_ADDR Addr; ///< / Extended PCI Address
-} PCI_ADDR;
-#endif
-
-#define FIXUP_PTR(ptr) ptr
-
-//------------------------------------------------------------------------------------------------------------------------//
-/**
- * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
- * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
- * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
- * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
- * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
- * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
- * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
- * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
- * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
- * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
- * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
- * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
- * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
- * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
- * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
- * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
- * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
- * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
- * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
- * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
- * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
- * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
- * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
- * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
- * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
- * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
- * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
- * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
- * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
- * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
- * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
- * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
- * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
- * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
- * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
- * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
- */
-#define SB_CIMx_PARAMETER 0x02
-
-// Generic
-#define cimSpreadSpectrumDefault TRUE
-#define cimSpreadSpectrumTypeDefault 0x00 // Normal
-#define cimHpetTimerDefault TRUE
-#define cimHpetMsiDisDefault FALSE // Enable
-#define cimIrConfigDefault 0x00 // Disable
-#define cimSpiFastReadEnableDefault 0x00 // Disable
-#define cimSpiFastReadSpeedDefault 0x00 // NULL
-// GPP/AB Controller
-#define cimNbSbGen2Default TRUE
-#define cimAlinkPhyPllPowerDownDefault TRUE
-#define cimResetCpuOnSyncFloodDefault TRUE
-#define cimGppGen2Default FALSE
-#define cimGppMemWrImproveDefault TRUE
-#define cimGppPortAspmDefault FALSE
-#define cimGppLaneReversalDefault FALSE
-#define cimGppPhyPllPowerDownDefault TRUE
-// USB Controller
-#define cimUsbPhyPowerDownDefault FALSE
-// GEC Controller
-#define cimSBGecDebugBusDefault FALSE
-#define cimSBGecPwrDefault 0x03
-// Sata Controller
-#define cimSataSetMaxGen2Default 0x00
-#define cimSATARefClkSelDefault 0x10
-#define cimSATARefDivSelDefault 0x80
-#define cimSataAggrLinkPmCapDefault TRUE
-#define cimSataPortMultCapDefault TRUE
-#define cimSataPscCapDefault 0x00 // Enable
-#define cimSataSscCapDefault 0x00 // Enable
-#define cimSataFisBasedSwitchingDefault FALSE
-#define cimSataCccSupportDefault FALSE
-#define cimSataClkAutoOffDefault FALSE
-#define cimNativepciesupportDefault FALSE
-// Fusion Related
-#define cimAcDcMsgDefault FALSE
-#define cimTimerTickTrackDefault FALSE
-#define cimClockInterruptTagDefault FALSE
-#define cimOhciTrafficHandingDefault FALSE
-#define cimEhciTrafficHandingDefault FALSE
-#define cimFusionMsgCMultiCoreDefault FALSE
-#define cimFusionMsgCStageDefault FALSE
-
-#endif // _AMD_SBPLATFORM_H_
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
+
+#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>
+typedef UINT64 PLACEHOLDER;
+#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>
+#include <southbridge/amd/cimx_wrapper/sb800/Amd.h>
+#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper
+#include <vendorcode/amd/cimx/sb800/SB800.h>
+#include <vendorcode/amd/cimx/sb800/SBTYPE.h>
+#include <vendorcode/amd/cimx/sb800/ACPILIB.h>
+#include <vendorcode/amd/cimx/sb800/SBDEF.h>
+#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
+#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>
+#include <vendorcode/amd/cimx/sb800/OEM.h>
+
+#ifdef NULL
+ #undef NULL
+#endif
+#define NULL 0
+
+#ifndef SBOEM_ACPI_RESTORE_SWSMI
+ #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+#endif
+
+#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
+
+/// Extended PCI Address
+typedef struct _EXT_PCI_ADDR {
+ UINT32 Reg :16; ///< / PCI Register
+ UINT32 Func:3; ///< / PCI Function
+ UINT32 Dev :5; ///< / PCI Device
+ UINT32 Bus :8; ///< / PCI Address
+} EXT_PCI_ADDR;
+
+/// PCI Address
+typedef union _PCI_ADDR {
+ UINT32 ADDR; ///< / 32 bit Address
+ EXT_PCI_ADDR Addr; ///< / Extended PCI Address
+} PCI_ADDR;
+#endif
+
+#define FIXUP_PTR(ptr) ptr
+
+//------------------------------------------------------------------------------------------------------------------------//
+/**
+ * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
+ * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
+ * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
+ * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
+ * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
+ * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
+ * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
+ * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
+ * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
+ * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
+ * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
+ * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
+ * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
+ * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
+ */
+#define SB_CIMx_PARAMETER 0x02
+
+// Generic
+#define cimSpreadSpectrumDefault TRUE
+#define cimSpreadSpectrumTypeDefault 0x00 // Normal
+#define cimHpetTimerDefault TRUE
+#define cimHpetMsiDisDefault FALSE // Enable
+#define cimIrConfigDefault 0x00 // Disable
+#define cimSpiFastReadEnableDefault 0x00 // Disable
+#define cimSpiFastReadSpeedDefault 0x00 // NULL
+// GPP/AB Controller
+#define cimNbSbGen2Default TRUE
+#define cimAlinkPhyPllPowerDownDefault TRUE
+#define cimResetCpuOnSyncFloodDefault TRUE
+#define cimGppGen2Default FALSE
+#define cimGppMemWrImproveDefault TRUE
+#define cimGppPortAspmDefault FALSE
+#define cimGppLaneReversalDefault FALSE
+#define cimGppPhyPllPowerDownDefault TRUE
+// USB Controller
+#define cimUsbPhyPowerDownDefault FALSE
+// GEC Controller
+#define cimSBGecDebugBusDefault FALSE
+#define cimSBGecPwrDefault 0x03
+// Sata Controller
+#define cimSataSetMaxGen2Default 0x00
+#define cimSATARefClkSelDefault 0x10
+#define cimSATARefDivSelDefault 0x80
+#define cimSataAggrLinkPmCapDefault TRUE
+#define cimSataPortMultCapDefault TRUE
+#define cimSataPscCapDefault 0x00 // Enable
+#define cimSataSscCapDefault 0x00 // Enable
+#define cimSataFisBasedSwitchingDefault FALSE
+#define cimSataCccSupportDefault FALSE
+#define cimSataClkAutoOffDefault FALSE
+#define cimNativepciesupportDefault FALSE
+// Fusion Related
+#define cimAcDcMsgDefault FALSE
+#define cimTimerTickTrackDefault FALSE
+#define cimClockInterruptTagDefault FALSE
+#define cimOhciTrafficHandingDefault FALSE
+#define cimEhciTrafficHandingDefault FALSE
+#define cimFusionMsgCMultiCoreDefault FALSE
+#define cimFusionMsgCStageDefault FALSE
+
+#endif // _AMD_SBPLATFORM_H_
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