[coreboot] [commit] r6403 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht

[repository service]

Author: mjones
Date: Mon Feb 28 04:12:00 2011
New Revision: 6403
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6403

Log:
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add to init_fidvid_stage2 some step for my CPU (rev C3)
mentioned in BKDG 2.4.2.6 (5) that was missing

Signed-off-by: Xavi Drudis Ferran <xdrudis at tinet.cat>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/model_10xxx/fidvid.c
   trunk/src/northbridge/amd/amdht/AsPsDefs.h

Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 04:08:06 2011	(r6402)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 04:12:00 2011	(r6403)
@@ -65,6 +65,25 @@
 		       dword);
 	}
 }
+static void enableNbPState1( device_t dev ) {
+  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
+  if (cpuRev & AMD_FAM10_C3) {
+    u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
+    if ( nbPState){
+      u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
+      u32 i;
+      for (i = nbPState; i < NM_PS_REG; i++) {
+         msr_t msr =  rdmsr(PS_REG_BASE + i);
+         if (msr.hi &  PS_EN_MASK ) {
+            msr.hi |= NB_DID_M_ON;
+            msr.lo &= NB_VID_MASK_OFF;
+	    msr.lo |= ( nbVid1 << NB_VID_POS);
+	    wrmsr(PS_REG_BASE + i, msr);
+	 }
+      }
+    }
+  }
+}
 
 static void setVSRamp(device_t dev) {
 	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSRampTime]
@@ -800,6 +819,7 @@
 	dtemp |= PLLLOCK_DFT_L;
 	pci_write_config32(dev, 0xA0, dtemp);
 
+        enableNbPState1(dev);
 	finalPstateChange();
 
 	/* Set TSC to tick at the P0 ndfid rate */

Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/AsPsDefs.h	Mon Feb 28 04:08:06 2011	(r6402)
+++ trunk/src/northbridge/amd/amdht/AsPsDefs.h	Mon Feb 28 04:12:00 2011	(r6403)
@@ -153,6 +153,8 @@
 #define PS_2 0x00020000		/* P-state 2 */
 #define PS_CPU_DID_1 0x40		/* Cpu Did 1 */
 
+#define NB_VID1_MASK  0x00003f80      /* F3x1F4[NbVid1]*/
+#define NB_VID1_SHIFT  7      /* F3x1F4[NbVid1] */