[coreboot] [commit] r6396 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct
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Mon Feb 28 01:18:47 CET 2011
Author: mjones
Date: Mon Feb 28 01:18:43 2011
New Revision: 6396
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6396
Log:
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.
Signed-off-by: Xavi Drudis Ferran <xdrudis at tinet.cat>
Acked-by: Marc Jones <marcj303 at gmail.com>
Modified:
trunk/src/cpu/amd/model_10xxx/defaults.h
trunk/src/cpu/amd/model_10xxx/fidvid.c
trunk/src/northbridge/amd/amdfam10/Kconfig
trunk/src/northbridge/amd/amdht/AsPsDefs.h
trunk/src/northbridge/amd/amdmct/amddefs.h
Modified: trunk/src/cpu/amd/model_10xxx/defaults.h
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/defaults.h Mon Feb 28 01:10:37 2011 (r6395)
+++ trunk/src/cpu/amd/model_10xxx/defaults.h Mon Feb 28 01:18:43 2011 (r6396)
@@ -68,7 +68,7 @@
1 << 24, 0x00000000,
1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
- { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL,
+ { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
0 << 1, 0x00000000,
1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
@@ -261,8 +261,11 @@
{ 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
- { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */
+ { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
+ 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */
+
+ { 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
+ 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */
/* Reported Temp Control Register */
{ 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:10:37 2011 (r6395)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:18:43 2011 (r6396)
@@ -275,19 +275,18 @@
}
-static void config_power_ctrl_misc_reg(device_t dev) {
+static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
/* check PVI/SVI */
u32 dword = pci_read_config32(dev, 0xA0);
+
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
+ /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
- dword &= VID_SLAM_OFF | PLLLOCK_OFF;
- dword |= PLLLOCK_DFT_L;
- pci_write_config32(dev, 0xA0, dword);
+ dword &= VID_SLAM_OFF ;
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
- dword &= PLLLOCK_OFF;
- dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
- pci_write_config32(dev, 0xA0, dword);
+ dword |= VID_SLAM_ON;
u32 dtemp = dword;
@@ -299,7 +298,27 @@
else
dword &= PWR_PLN_OFF;
pci_write_config32(dev, 0xD8, dword);
+
+ dword = dtemp;
+ }
+ /* set the rest of A0 since we're at it... */
+
+ if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
+ dword |= NB_PSTATE_FORCE_ON;
+ } // else should we clear it ?
+
+
+ if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
+ dword |= BP_INS_TRI_EN_ON ;
}
+
+ /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
+ #if CONFIG_SVI_HIGH_FREQ
+ if (cpuRev & AMD_FAM10_C3) {
+ dword |= SVI_HIGH_FREQ_ON;
+ }
+ #endif
+ pci_write_config32(dev, 0xA0, dword);
}
static void config_nb_syn_ptr_adj(device_t dev) {
@@ -344,8 +363,7 @@
config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
- config_power_ctrl_misc_reg(dev);
-
+ config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
config_nb_syn_ptr_adj(dev);
config_acpi_pwr_state_ctrl_regs(dev);
Modified: trunk/src/northbridge/amd/amdfam10/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/Kconfig Mon Feb 28 01:10:37 2011 (r6395)
+++ trunk/src/northbridge/amd/amdfam10/Kconfig Mon Feb 28 01:18:43 2011 (r6396)
@@ -112,4 +112,12 @@
endif
endif
+config SVI_HIGH_FREQ
+ bool
+ default n
+ depends on NORTHBRIDGE_AMD_AMDFAM10
+ help
+ Select this for boards with a Voltage Regulator able to operate
+ at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
+
source src/northbridge/amd/amdfam10/root_complex/Kconfig
Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:10:37 2011 (r6395)
+++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:18:43 2011 (r6396)
@@ -198,11 +198,19 @@
#define PVI_MODE 0x100 /* PviMode bit mask */
#define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */
#define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */
+#define NB_PSTATE_FORCE_ON 0x010000000 /* set Northbridge P-state
+ force on next LDTSTOP
+ assertion on, in F3xA0 */
+#define BP_INS_TRI_EN_ON 0x00004000 /* breakpoint pins tristate
+ enable in F3xA0 */
#define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */
#define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */
#define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */
-/* P-state Specification register base in PCI sapce */
+#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for
+ 3.4 MHz SVI in rev. C3 */
+
+/* P-state Specification register base in PCI space */
#define PS_SPEC_REG 0x1e0 /* PS Spec register base address */
#define PCI_REG_LEN 4 /* PCI register length */
#define NB_DID_MASK 0x10000 /* NbDid bit mask */
Modified: trunk/src/northbridge/amd/amdmct/amddefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:10:37 2011 (r6395)
+++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:18:43 2011 (r6396)
@@ -64,7 +64,9 @@
#define AMD_DR_ALL (AMD_DR_Bx)
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
-#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3)
+#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
+#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
+#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
#define AMD_DR_Dx (AMD_HY_D0)
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
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