[coreboot] [commit] r6390 - trunk/src/cpu/amd/model_10xxx

[repository service]

Author: mjones
Date: Mon Feb 28 00:50:30 2011
New Revision: 6390
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6390

Log:
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
Northbridge/core synchronization FIFO pointer adjust, to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis at tinet.cat>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/model_10xxx/fidvid.c

Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 00:47:57 2011	(r6389)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 00:50:30 2011	(r6390)
@@ -258,6 +258,17 @@
 	}
 }
 
+            
+static void config_nb_syn_ptr_adj(device_t dev) {
+	/* Note the following settings are additional from the ported
+	 * function setFidVidRegs()
+	 */
+	u32 dword = pci_read_config32(dev, 0xDc);
+	dword |= 0x5 << 12;	/* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
+	pci_write_config32(dev, 0xdc, dword);
+
+}
+
 static void prep_fid_change(void)
 {
         u32 dword;
@@ -281,13 +292,8 @@
 		config_clk_power_ctrl_reg0(i);
 
                 config_power_ctrl_misc_reg(dev);
-             
-		/* Note the following settings are additional from the ported
-		 * function setFidVidRegs()
-		 */
-		dword = pci_read_config32(dev, 0xDc);
-		dword |= 0x5 << 12;	/* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
-		pci_write_config32(dev, 0xdc, dword);
+
+ 		config_nb_syn_ptr_adj(dev);
 
 		/* Rev B settings - FIXME: support other revs. */
 		dword = 0xA0E641E6;