[coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1

[Stefan Reinauer]

* Scott Duplichan <scott at notabs.org> [110225 02:02]:
> Stefan Reinauer wrote: 
> 
> ]> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> 
> ]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
> ]in romstage.c. Is there a chance to remove it from Kconfig instead?
> 
> Certainly the two occurrences of 2e is not ideal. This change works:
> 
> -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
 
That would work. Or leave the first version and we try to get rid of the
Kconfig variable later on...

Anyways
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

> I believe most SIOs have a strap option for 4e, so presumably this
> address needs to be project selectable by some method. Phoenix
> legacy BIOS actually figures it out at runtime. That method seems
> dangerous to me and makes stepping through the code tedious.

You can certainly detect where it lives and what kind of device it is
(though I have not seen Phoenix do that during runtime on intel systems,
according to SerialICE) .. The one thing I think you can not probe is
how the ports are wired up (i.e. if you have two Super I/O chips, is the
one serial port connected to the first or second chip)

> If we remove it from kconfig, would it just be local to romstage.c?
> I suppose this would be a separate patch, given the number of projects
> affected.

There's always at least another occurence in devicetree.cb. But that is
not used in romstage, only in ramstage.

Maybe it is time to think about extending the devicetree.cb so it can be
used by romstage, too? But that's for another mail.