[coreboot] 870 attempt
Jonathan A. Kollasch
jakllsch at kollasch.net
Thu Feb 24 15:23:20 CET 2011
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
> Hi,
>
> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
> board. Raminit seems to go okay, as does the first bits of ramstage.
> However, ramstage fails after the first two passes through
> rs780_enable(). It stalls in get_vid_did() reading PCI config space
> of device 2 (or 4). Also, the rs780 HT init code thinks the link should
> run at 200MHz, maybe that's related.
Attached is the diff, and console output there from.
(Mainboard directory is a svn cp of bimini_fam10.)
Jonathan Kollasch
-------------- next part --------------
Index: src/southbridge/amd/rs780/rs780.c
===================================================================
--- src/southbridge/amd/rs780/rs780.c (revision 6378)
+++ src/southbridge/amd/rs780/rs780.c (working copy)
@@ -109,7 +109,11 @@
static u32 get_vid_did(device_t dev)
{
- return pci_read_config32(dev, 0);
+ u32 vdid;
+ printk(BIOS_INFO, "gvd");
+ vdid = pci_read_config32(dev, 0);
+ printk(BIOS_INFO, "%08x\n", vdid);
+ return vdid;
}
static void rs780_nb_pci_table(device_t nb_dev)
Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig (revision 6378)
+++ src/mainboard/asus/Kconfig (working copy)
@@ -37,6 +37,8 @@
bool "M4A785-M"
config BOARD_ASUS_M4A78_EM
bool "M4A78-EM"
+config BOARD_ASUS_M4A87TD_USB3
+ bool "M4A87TD/USB3"
config BOARD_ASUS_MEW_AM
bool "MEW-AM"
config BOARD_ASUS_MEW_VM
@@ -64,6 +66,7 @@
source "src/mainboard/asus/m2v-mx_se/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
source "src/mainboard/asus/m4a78-em/Kconfig"
+source "src/mainboard/asus/m4a87td-usb3/Kconfig"
source "src/mainboard/asus/mew-am/Kconfig"
source "src/mainboard/asus/mew-vm/Kconfig"
source "src/mainboard/asus/p2b/Kconfig"
Index: src/mainboard/asus/m4a87td-usb3/Kconfig
===================================================================
--- src/mainboard/asus/m4a87td-usb3/Kconfig (revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/Kconfig (working copy)
@@ -1,9 +1,9 @@
-if BOARD_AMD_BIMINI_FAM10
+if BOARD_ASUS_M4A87TD_USB3
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_AMD_SOCKET_ASB2
+ select CPU_AMD_SOCKET_AM3
select DIMM_DDR3
select DIMM_REGISTERED
# TODO: Enable QRANK_DIMM_SUPPORT? Was commented in the Kconfig file,
@@ -24,16 +24,16 @@
select SERIAL_CPU_INIT
select AMDMCT
select GENERATE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_2048
+ select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
- select GFXUMA
+ #select GFXUMA
select HAVE_DEBUG_CAR
select SET_FIDVID
config MAINBOARD_DIR
string
- default amd/bimini_fam10
+ default asus/m4a87td-usb3
config APIC_ID_OFFSET
hex
@@ -41,7 +41,7 @@
config MAINBOARD_PART_NUMBER
string
- default "Bimini (Fam10)"
+ default "M4A87TD/USB3"
config HW_MEM_HOLE_SIZEK
hex
@@ -93,14 +93,10 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0x3060
+ default 0x8432
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x1022
-
config RAMBASE
hex
default 0x200000
-endif #BOARD_AMD_BIMINI_FAM10
+endif #BOARD_ASUS_M4A87TD_USB3
Index: src/mainboard/asus/m4a87td-usb3/devicetree.cb
===================================================================
--- src/mainboard/asus/m4a87td-usb3/devicetree.cb (revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/devicetree.cb (working copy)
@@ -1,7 +1,7 @@
# sample config for amd/bimini_fam10
chip northbridge/amd/amdfam10/root_complex
device lapic_cluster 0 on
- chip cpu/amd/socket_ASB2 #L1 and DDR3
+ chip cpu/amd/socket_AM3 #L1 and DDR3
device lapic 0 on end
end
end
@@ -10,17 +10,17 @@
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
- device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
+ #device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b
device pci 4.0 on end # PCIE P2P bridge 0x9604
- device pci 5.0 on end # PCIE P2P bridge 0x9605
- device pci 6.0 on end # PCIE P2P bridge 0x9606
- device pci 7.0 on end # PCIE P2P bridge 0x9607
+ device pci 5.0 off end # PCIE P2P bridge 0x9605
+ device pci 6.0 off end # PCIE P2P bridge 0x9606
+ device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
device pci 9.0 on end #
- device pci a.0 off end #
- register "gppsb_configuration" = "4" # Configuration E
+ device pci a.0 on end #
+ register "gppsb_configuration" = "1" # Configuration E
register "gpp_configuration" = "2" # Configuration C
register "port_enable" = "0x6fc"
register "gfx_dev2_dev3" = "1"
@@ -53,7 +53,24 @@
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on end # LPC 0x439d
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8718f
+ device pnp 2e.0 off end
+ device pnp 2e.1 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end
+ device pnp 2e.3 off end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.8 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a off end
+ end #superio/ite/it8718f
+ end #LPC
device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.5 on end # USB 2
device pci 14.6 on end # Gec
Index: src/mainboard/asus/m4a87td-usb3/romstage.c
===================================================================
--- src/mainboard/asus/m4a87td-usb3/romstage.c (revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/romstage.c (working copy)
@@ -69,6 +69,7 @@
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
+#include "superio/ite/it8718f/early_serial.c"
#define RC00 0
#define RC01 1
@@ -109,6 +110,7 @@
enable_rs780_dev8();
sb800_lpc_init();
+ it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
Index: src/mainboard/asus/m4a87td-usb3/mainboard.c
===================================================================
--- src/mainboard/asus/m4a87td-usb3/mainboard.c (revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/mainboard.c (working copy)
@@ -122,6 +122,7 @@
}
#endif /* get_ide_dma66() */
+#if 0
/*************************************************
* enable the dedicated function in bimini board.
* This function called early than rs780_enable.
@@ -178,6 +179,7 @@
enable_int_gfx();
/* get_ide_dma66(); */
}
+#endif
int add_mainboard_resources(struct lb_memory *mem)
{
@@ -195,5 +197,5 @@
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Bimini Mainboard")
- .enable_dev = bimini_enable,
+ //.enable_dev = bimini_enable,
};
-------------- next part --------------
coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 starting...
BSP Family_Model: 00100f43
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f24
F3xD8: 03001716
F3xDC: 00005336
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
started ap apicid: cccoororerexe:xx :: ------- --{ {{ AAAPPPIIICICCDIIDD === 01002 3 N ONNOODDDEEEIIDID D = = =0 00000 C COCORORERIEEDII DD= == 00102}3} }- --------
* mAimmPcii cc0rrr1ooosccctoooadddreeet::e : de e
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D
F:0-20-0
SMBus controller enabled, sb revision is A12
sb800_devices_por_init(): IDE Device, BDF:0-20-1
sb800_devices_por_init(): LPC Device, BDF:0-20-3
sb800_devices_por_init(): P2P Bridge, BDF:0-20-4
sb800_devices_por_init(): SATA Device, BDF:0-18-0
Begin FIDVID MSR 0xc0010071 0x30bc00d3 0x40036c40
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 2
readback = 2010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 3
readback = 3010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
End FIDVIDMSR 0xc0010071 0x30bc00d3 0x40036c40
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
...WARM RESET...
coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 starting...
BSP Family_Model: 00100f43
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f26
F3xD8: 03001716
F3xDC: 00005336
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
started ap apicid: ccocoorrereex:xx:: - ------ -- { {{ AAPAPPIICICCIIDIDD = == 010023 N NONOODEDDEEIIDIDD = == 00000 0C COCOORRREIEEIDI DD = == 0 0013}2}} -------
--
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(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A12
sb800_devices_por_init(): IDE Device, BDF:0-20-1
sb800_devices_por_init(): LPC Device, BDF:0-20-3
sb800_devices_por_init(): P2P Bridge, BDF:0-20-4
sb800_devices_por_init(): SATA Device, BDF:0-18-0
Begin FIDVID MSR 0xc0010071 0x30bc00d3 0x40033440
End FIDVIDMSR 0xc0010071 0x30bc00d3 0x4000340e
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=f
DIMMPresence: DIMMPresent=f
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=f
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=f
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=4
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=2
DIMMPresence: DATAload[1]=4
DIMMPresence: MAload[1]=20
DIMMPresence: MAdimms[1]=2
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent f
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent f
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 1ffffff BottomIO: e00000
Node: 00 base: 03 limit: 21fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:e00000
CPUMemTyping: Bottom32bIO:e00000
CPUMemTyping: Bottom40bIO:2200000
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1100
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1100
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1100
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading image.
Check CBFS header at fffffcae
magic is 4f524243
Found CBFS header at fffffcae
Check cmos_layout.bin
CBFS: follow chain: fff00000 + 28 + 6ef + align -> fff00740
Check fallback/romstage
CBFS: follow chain: fff00740 + 38 + 1751c + align -> fff17cc0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1179648 bytes), entry @ 0x200000
Stage: done loading.
Jumping to image.
coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 0
PCI: 00:14.5: enabled 1
PCI: 00:14.6: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 0
PCI: 00:14.5: enabled 1
PCI: 00:14.6: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=3
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
gvdPCI: Using configuration type 1
59571002
rs780_enable: dev=002198bc, VID_DID=0x59571002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1002/5957] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
gvd59571002
rs780_enable: dev=002198bc, VID_DID=0x59571002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1002/5957] enabled
gvd
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