[coreboot] [PATCH] add SPD address mapping to i945

[Sven Schnelle]

The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.

For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.

This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
---
 src/mainboard/getac/p470/romstage.c       |    2 +-
 src/mainboard/ibase/mb899/romstage.c      |    2 +-
 src/mainboard/intel/d945gclf/romstage.c   |    2 +-
 src/mainboard/kontron/986lcd-m/romstage.c |    2 +-
 src/mainboard/lenovo/x60/romstage.c       |    3 +-
 src/mainboard/roda/rk886ex/romstage.c     |    2 +-
 src/northbridge/intel/i945/raminit.c      |   75 +++++++++++++++--------------
 src/northbridge/intel/i945/raminit.h      |    3 +-
 8 files changed, 47 insertions(+), 44 deletions(-)

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