[coreboot] Code organization question Re: Next target: ASUS TUSI-M (Cont'd)

[Keith Hui]

Hit send too soon... My questions continues below...

On Wed, Feb 16, 2011 at 11:52 PM, Keith Hui <buurin at gmail.com> wrote:
> Hi Joseph,
>
> Okay, now I probably can use some help, at least in how to organize
> the code. Below is what I understand up to this point, but feel free
> to stop and correct me.
>
> SIS630 is just one chip. All the chipsets we have so far seems to
> always have a "northbridge" plus a "southbridge", at least that's how
> the coreboot source tree is organized. Northbridge has raminit.c for
> initializing (S)DRAM, a chip.h where some stuff got declared - but not
> 100% sure what, northbridge.c as a "driver" for ramstage for detecting
> and enabling PCI resources, as well as building a memory table, and
> debug.c with functions needed for CONFIG_DEBUG_RAM_SETUP.
>
> Southbridge has...
> bootblock.c for code required to make the whole ROM chip accessible
> all ACPI stuff (will be a while before I can get to that)
> one ramstage "driver" for each PCI device the bridge supports eg. IDE, USB, LAN
> romstage smbus access code for reading SPD
>
> Mainboard has...
devicetree.cb for describing the board's devices
chip.h declaring the board's name
irq_tables.c that maps interrupt routing and we get it with getpir
romstage.c to do early serial port init, board specific init to make
SPD accessible, then call northbridge's raminit code
and cmos.layout.

>
> Here are my questions. If the answer can be found in a certain file in
> the tree, tell me - I'll read it.
>
> For this single chip chipset, should I put everything into
> northbridge, or keep only RAM init and bus scan stuff in
> src/northbridge, and put IDE/USB/LAN/SMBus/LPC/ISA etc. in
> src/southrbidge? In this scheme where would VGA fit?
>
> SIS630 and my board has onboard VGA that shares memory with main. I
> have the VGA BIOS extracted. Do I still need to write code to
> initialize it? If so, where in the coreboot tree?
>
> What is the relationship between devicetree.cb, sconfig, parameters
> available to be included in cmos.layout, northbridge and southbridge
> drivers? Say I need to have add a setting in cmos.layout to
> enable/disable the built in LAN, in how many places do I have to
> declare this setting? My factory bios writes some known values into
> various superio LDNs during early initialization. Can I declare them
> in devicetree.cb or I have to write them in C into some early init
> code? Also, should I declare devices that can be enabled/disabled
> either in software or by jumper?
>
> In declaring devices in devicetree.cb, does "device pci_domain 1..."
> means PCI bus 1, like the AGP slot on a 440BX?
>
> The IDE, USB and LAN devices on SIS chipsets so often share the same
> PCI IDs and probably the same initialization sequence. There is
> currently only one other SIS southbridge in the tree (the 966) but its
> IDE has the same 1039:5513 ID as that on the 630. Any way I can share
> this code, or I still have to duplicate it? Any chance I can factor it
> out like Sil3114?
>
> In the ramstage driver model, what is the relationships between chip.h,
the xxx_ops structs, the xxx_config structs, and the various function
pointers in them?

>
> Looking at my factory BIOS disassembly and what coreboot v1 had done,
> I am going to have to write some known values into known registers,
> both in the northbridge device, "southbridge device", and superio.
> Where usually is this done? bootblock_northbridge_init() for
> tinybootblock, in the mainboard romstage main(), in raminit.c before
> actually doing RAM init? I figure the first option is the earliest and
> best opportunity, following factory bios' lead.
>
> I had a long chat the other night with Idwer helping him port coreboot
> to intel 865. Figures it's about time I get some help for myself.
>
Thanks.
Keith

>
> On Wed, Jan 5, 2011 at 5:55 AM, Joseph Smith <joe at settoplinux.org> wrote:
>>
>>
>> On Wed, 5 Jan 2011 00:06:29 -0500, Keith Hui <buurin at gmail.com> wrote:
>>> This is the next board I want to port coreboot to. And the three logs
>>> are attached. "Sissy" is what I name the machine the board is in,
>>> after SiS. :D
>>>
>>> The flash chip i know for sure is SST 39SF020A. It needs a board
>>> enable, for which I have figured out 3 of the 5 operations involved,
>>> thanks to Luc's slides up at Phoronix.
>>>
>>> It used a soldered PLCC32 flash chip. I soldered a socket on myself,
>>> and the chip miraclously survived. But I have not been able to get
>>> another of the same chip for backup. All my 3 spares are DIP32.
>>>
>>> Super I/O is IT8705F, already supported. So it looks like all that's
>>> needed is porting SiS630 from coreboot v1. I think I would also be the
>>> first to port a single chip chipset to v4.
>>>
>>> Thanks to a previous thread on this list, I got the '630 datasheet,
>>> but I don't know for sure what is different between it (the 630) and
>>> my chip (630ET).
>>>
>>> Appreciate all the help I can get for this one.
>>
>> Sweet! I have a bunch of SIS 630 boards laying around, anything I can do to
>> help just let me know :-)
>>
>> --
>> Thanks,
>> Joseph Smith
>> Set-Top-Linux
>> www.settoplinux.org
>>
>>
>