[coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 3 of 8.

[Rudolf Marek]

Hi Frank,

> 	case 0:
> +		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
> +		break;

I think I know why. Most likely the wideIO port is too wide. I created some 
patches recently to fix it in sb700 code + sb800 and sb600.

http://tracker.coreboot.org/trac/coreboot/changeset/6343

Maybe this is the reason. For the curiosity what port is put there? With the 
patch I introduced it starts to decode smaller region making things sane.
The patch would need some tunes in direction of LegacyFree parameter. Maybe we 
will need to unset it and do similar LPC stuff init as we do already in the 
bootblock. (this file does |= instead of cleaning up regs first, so we might 
prepare some sane register values in advance).

Thanks,
Rudolf

PS: thank you and AMD for your contribution.