[coreboot] [commit] r6360 - in trunk/src/mainboard: . lenovo lenovo/x60
repository service
svn at coreboot.org
Mon Feb 14 21:02:47 CET 2011
Author: stuge
Date: Mon Feb 14 21:02:47 2011
New Revision: 6360
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6360
Log:
Lenovo ThinkPad X60 / X60s Support
Adds support for Lenovo X60 series ThinkPads. So far, only X60s
(Model 1703) has been tested.
It's a basic patch without SMI and ACPI, as this makes it easier to
review. SMI and ACPI patches will follow.
Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>
Added:
trunk/src/mainboard/lenovo/
trunk/src/mainboard/lenovo/Kconfig
trunk/src/mainboard/lenovo/x60/
- copied from r6357, trunk/src/mainboard/roda/rk886ex/
Modified:
trunk/src/mainboard/Kconfig
trunk/src/mainboard/lenovo/x60/Kconfig
trunk/src/mainboard/lenovo/x60/chip.h
trunk/src/mainboard/lenovo/x60/devicetree.cb
trunk/src/mainboard/lenovo/x60/irq_tables.c
trunk/src/mainboard/lenovo/x60/mainboard.c
trunk/src/mainboard/lenovo/x60/mptable.c
trunk/src/mainboard/lenovo/x60/romstage.c
Modified: trunk/src/mainboard/Kconfig
==============================================================================
--- trunk/src/mainboard/Kconfig Mon Feb 14 20:26:22 2011 (r6359)
+++ trunk/src/mainboard/Kconfig Mon Feb 14 21:02:47 2011 (r6360)
@@ -68,6 +68,8 @@
bool "Kontron"
config VENDOR_LANNER
bool "Lanner"
+config VENDOR_LENOVO
+ bool "Lenovo"
config VENDOR_LIPPERT
bool "Lippert"
config VENDOR_MITAC
@@ -147,6 +149,7 @@
source "src/mainboard/jetway/Kconfig"
source "src/mainboard/kontron/Kconfig"
source "src/mainboard/lanner/Kconfig"
+source "src/mainboard/lenovo/Kconfig"
source "src/mainboard/lippert/Kconfig"
source "src/mainboard/mitac/Kconfig"
source "src/mainboard/msi/Kconfig"
Added: trunk/src/mainboard/lenovo/Kconfig
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/lenovo/Kconfig Mon Feb 14 21:02:47 2011 (r6360)
@@ -0,0 +1,22 @@
+if VENDOR_LENOVO
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_LENOVO_X60
+ bool "ThinkPad X60 / X60s"
+ help
+ The following X60 series ThinkPad machines have been verified to
+ work correctly:
+
+ ThinkPad X60s (Model 1703)
+
+endchoice
+
+source "src/mainboard/lenovo/x60/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Lenovo"
+
+endif # VENDOR_LENOVO
Modified: trunk/src/mainboard/lenovo/x60/Kconfig
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/Kconfig Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/Kconfig Mon Feb 14 21:02:47 2011 (r6360)
@@ -1,4 +1,4 @@
-if BOARD_RODA_RK886EX
+if BOARD_LENOVO_X60
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -7,28 +7,35 @@
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
- select SOUTHBRIDGE_TI_PCI7420
- select SUPERIO_SMSC_LPC47N227
- select SUPERIO_RENESAS_M3885X
+ select SOUTHBRIDGE_RICOH_RL5C476
+ select SUPERIO_NSC_PC87382
+ select SUPERIO_NSC_PC87392
+ select EC_LENOVO_PMH7
select EC_ACPI
select BOARD_HAS_FADT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select MMCONF_SUPPORT
- select HAVE_SMI_HANDLER
- select HAVE_ACPI_TABLES
- select HAVE_ACPI_RESUME
- select BOARD_ROMSIZE_KB_1024
+ select GFXUMA
+ select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR
string
- default roda/rk886ex
+ default lenovo/x60
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
config MAINBOARD_PART_NUMBER
string
- default "RK886EX"
+ default "ThinkPad X60 / X60s"
config MMCONF_BASE_ADDRESS
hex
@@ -40,18 +47,10 @@
config MAX_CPUS
int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
default 2
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0x6886
-
-config MAXIMUM_SUPPORTED_FREQUENCY
+config MAX_PHYSICAL_CPUS
int
- default 400
+ default 1
-endif # BOARD_RODA_RK886EX
+endif
Modified: trunk/src/mainboard/lenovo/x60/chip.h
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/chip.h Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/chip.h Mon Feb 14 21:02:47 2011 (r6360)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/devicetree.cb Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Feb 14 21:02:47 2011 (r6360)
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
@@ -29,18 +30,15 @@
device pci_domain 0 on
device pci 00.0 on end # host bridge
- # auto detection:
- #device pci 01.0 off end # i945 PCIe root port
- #device pci 02.0 on end # vga controller
- #device pci 02.1 on end # display controller
-
+ device pci 02.0 on end # vga controller
+ device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
@@ -48,72 +46,85 @@
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
- register "gpi13_routing" = "2"
- register "gpi8_routing" = "1"
- register "gpi7_routing" = "2"
- register "gpe0_en" = "0x20800007"
-
- register "ide_legacy_combined" = "0x1"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
+ register "gpi13_routing" = "2"
+ register "gpi12_routing" = "2"
+ register "gpi8_routing" = "2"
+
register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
- device pci 1c.1 on end # PCIe
- device pci 1c.2 on end # PCIe
- #device pci 1c.3 off end # PCIe port 4
- #device pci 1c.4 off end # PCIe port 5
- #device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.3 on end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on
- chip southbridge/ti/pci7420
- register "smartcard_enabled" = "0x0"
- device pci 3.0 on end
- device pci 3.1 on end
- device pci 3.2 on end
- device pci 3.3 off end # smartcard
- end
- end # PCI bridge
- #device pci 1e.2 off end # AC'97 Audio
- #device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47n227
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 5
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 off # Keyboard+Mouse
- # io 0x60 = 0x60
- # io 0x62 = 0x64
- # irq 0x70 = 1
- # irq 0x72 = 12
- end
- end
- chip superio/renesas/m3885x
- device pnp ff.1 on # dummy address
+ register "gpe0_en" = "0x11000006"
+
+ device pci 1b.0 on end # Audio Controller
+ device pci 1c.0 on end # Ethernet
+ device pci 1c.1 on end # Atheros WLAN
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1f.0 on # PCI-LPC bridge
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
end
end
chip ec/acpi
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+ end
+ chip superio/nsc/pc87382
+ device pnp 164e.2 on # IR
+ io 0x60 = 0x2f8
+ end
+
+ device pnp 164e.3 off # Serial Port
+ io 0x60 = 0x3f8
+ end
+
+ device pnp 164e.7 on # GPIO
+ io 0x60 = 0x1680
+ end
+
+ device pnp 164e.19 on # DLPC
+ io 0x60 = 0x164c
+ end
end
- end
- #device pci 1f.1 off end # IDE
+ chip superio/nsc/pc87392
+ device pnp 2e.0 off #FDC
+ end
+
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x3bc
+ irq 0x70 = 7
+ end
+
+ device pnp 2e.2 off # Serial Port / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.3 on # Serial Port
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x1620
+ end
+
+ device pnp 2e.a off # WDT
+ end
+ end
+ end
+ device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
- #device pci 1f.4 off end # Realtek ID Codec
- end
- end
+ end
+ chip southbridge/ricoh/rl5c476
+ end
+ end
end
Modified: trunk/src/mainboard/lenovo/x60/irq_tables.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/irq_tables.c Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/irq_tables.c Mon Feb 14 21:02:47 2011 (r6360)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -22,37 +22,36 @@
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*18, /* There can be total 18 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x27b0, /* Device */
- 0, /* miniport */
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 15, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x122e, /* Device */
+ 0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xf, /* u8 checksum. */
+ 0xf5, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
- {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
- {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
- {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
- {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
- {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
- {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
- {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
- {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
- {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
- {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
- {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
- {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
- {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
- {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
- {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */
+ {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */
+ {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */
+ {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */
+ {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */
+ {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */
+ {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */
+ {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */
+ {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */
+ {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */
+ {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */
+ {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */
+ {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */
+ {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */
}
};
@@ -60,4 +59,3 @@
{
return copy_pirq_routing_table(addr);
}
-
Modified: trunk/src/mainboard/lenovo/x60/mainboard.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/mainboard.c Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Feb 14 21:02:47 2011 (r6360)
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -24,118 +25,59 @@
#include <arch/io.h>
#include <boot/tables.h>
#include <delay.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
#include <arch/coreboot_tables.h>
#include "chip.h"
-
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
#include <ec/acpi/ec.h>
-#include "m3885.h"
-
-#define DUMP_RUNTIME_REGISTERS 0
static void backlight_enable(void)
{
-#if 0
-// Disabled, don't let the X9511 burn out
- int i;
-
- /* P56 is Brightness Up, and it needs a Pulse instead of a
- * Level
- */
- for (i=0; i < 28; i++) {
- //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
- m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
- }
-#endif
- printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f));
+ pmh7_register_set_bit(0x50, 5);
}
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
+static void trackpoint_enable(void)
{
- u8 display_id;
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f40: /* Boot Panel Type */
- /* LCD panel type is SIO GPIO40-43 */
- // display_id = inb(0x60f) & 0x0f;
- display_id = 3;
- // M.x86.R_AX = 0x015f; // Supported but failed
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = display_id;
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
+ ec_write(0x0b, 0x03);
}
-static void int15_install(void)
+static void wlan_enable(void)
{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
+ ec_write(0x3a, 0x20);
}
-#endif
-
-#if DUMP_RUNTIME_REGISTERS
-static void dump_runtime_registers(void)
-{
- int i;
-
- printk(BIOS_DEBUG, "SuperIO runtime register block:\n");
- for (i=0; i<0x10; i++)
- printk(BIOS_DEBUG, "%02x ", i);
- printk(BIOS_DEBUG, "\n");
- for (i=0; i<0x10; i++)
- printk(BIOS_DEBUG, "%02x ", inb(0x600 +i));
- printk(BIOS_DEBUG, "\n");
-}
-#endif
static void mainboard_enable(device_t dev)
{
- /* Configure the MultiKey controller */
- // m3885_configure_multikey();
-
- /* Enable LCD Backlight */
backlight_enable();
-
- /* Disable Dummy DCC -> GP45 = 1 */
- outb(inb(0x60f) | (1 << 5), 0x60f);
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
-#if DUMP_RUNTIME_REGISTERS
- dump_runtime_registers();
-#endif
+ trackpoint_enable();
+ /* FIXME: this should be ACPI's task
+ * but for now, enable it here */
+ wlan_enable();
+
+ /* enable ACPI events */
+ ec_write(0x00, 0xa6);
+ ec_write(0x01, 0x05);
+
+ ec_write(0x02, 0xa0);
+ ec_write(0x03, 0x05);
+
+ /* set mask of enabled beeps */
+ ec_write(0x04, 0xfe);
+ ec_write(0x05, 0x96);
+
+ /* Unknown, but required for hotkeys
+ Maybe a mask for enabled keys? */
+
+ ec_write(0x12, 0xff);
+ ec_write(0x13, 0xff);
+ ec_write(0x14, 0xf4);
+ ec_write(0x15, 0x3c);
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("Roda Computer GmbH RK886EX Rugged Notebook (ROCKY3+)")
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
.enable_dev = mainboard_enable,
};
Modified: trunk/src/mainboard/lenovo/x60/mptable.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/mptable.c Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/mptable.c Mon Feb 14 21:02:47 2011 (r6360)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -46,35 +46,29 @@
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
-
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */
+
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
- /* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Modified: trunk/src/mainboard/lenovo/x60/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Feb 14 20:24:37 2011 (r6357)
+++ trunk/src/mainboard/lenovo/x60/romstage.c Mon Feb 14 21:02:47 2011 (r6360)
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -36,80 +37,146 @@
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
-#include "option_table.h"
void setup_ich7_gpios(void)
{
printk(BIOS_DEBUG, " GPIOS...");
- /* General Registers */
- outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
- // ------------------------------------------------------------
- // 0 - GPO6 - Enable power of SATA channel 0
- // 0 - GPO9 - Wireless LAN power on
- // 0 - GPO15 - FAN on
- // 1 - GPO22 - FWH WP
- // 1 - GPO24 - GPS on
- // 0 - GPO25 - External Antenna Mux on
- // 0 - GPO26 - BT on
- // 0 - GPO27 - GSM on
- outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
- // ------------------------------------------------------------
+
+ /* X60 GPIO:
+ 1: HDD_PRESENCE#
+ 6: Unknown (Pulled high by R215 to VCC3B)
+ 7: BDC_PRESENCE#
+ 8: H8_WAKE#
+ 9: RTC_BAT_IN#
+ 10: Unknown (Pulled high by R700 to VCC3M
+ 12: H8SCI#
+ 13: SLICE_ON_3M#
+ 14: Unknown (Pulled high by R321 to VCC3)
+ 15: Unknown (Pulled high by R258 to VCC3)
+ 19: Unknown (Pulled low by R594)
+ 21: Unknown (Pulled high by R145 to VCC3)
+ 22: FWH_WP#
+ 25: MDC_KILL#
+ 33: HDD_PRESENCE_2#
+ 35: CLKREQ_SATA#
+ 36: PLANARID0
+ 37: PLANARID1
+ 38: PLANARID2
+ 39: PLANARID3
+ 48: FWH_TBL#
+ */
+
+ outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xfbf6ddfd, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
/* Output Control Registers */
- outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */
- outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
- outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
- // ------------------------------------------------------------
- // 1 - GPO48 - FWH TBL#
- outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
- // ------------------------------------------------------------
+ outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000100f2, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+ outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
}
static void ich7_enable_lpc(void)
{
- int lpt_en = 0;
- if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
- lpt_en = 1<<2; // enable LPT
- }
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
- // Enable 0x02e0
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
- // COM3 decode
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
- // COM4 decode
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+
+ /* range 0x1600 - 0x167f */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+
+ /* range 0x15e0 - 0x10ef */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+
+ /* range 0x1680 - 0x169f */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
}
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_write_register(device_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
- outb(0x55, port);
+ outb(reg, port);
+ outb(val, port+1);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void dock_write_register(int reg, int value)
{
- unsigned int port = dev >> 8;
- outb(0xaa, port);
+ outb(reg, 0x164e);
+ outb(value, 0x164f);
+ /* original software reads the chip id after every
+ I/O operation. Not sure if they are doing it for
+ some code switching depending on hardware or just
+ to have a delay after every operation.
+
+ Do it the same way for now, we may remove it later
+ if it isn't needed
+ */
+ outb(0x20, 0x164e);
+ inb(0x164f);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void dock_dlpc_init(void)
{
- unsigned int port = dev >> 8;
- outb(reg, port);
- outb(val, port+1);
+ /* Select DLPC module */
+ dock_write_register(0x07, 0x19);
+ /* DLPC Base Address 0x164c */
+ dock_write_register(0x60, 0x16);
+ dock_write_register(0x61, 0x4c);
+ /* Activate DLPC */
+ dock_write_register(0x30, 0x01);
+ outb(0x07, 0x164c);
+
+ while(!(inb(0x164c) & 8))
+ udelay(100 * 100);
+}
+
+static void dock_gpio_set_mode(int port, int mode)
+{
+ dock_write_register(0xf0, port);
+ dock_write_register(0xf1, mode);
+
+}
+
+static void dock_gpio_init(void)
+{
+ /* Select GPIO module */
+ dock_write_register(0x07, 0x07);
+ /* GPIO Base Address 0x1680 */
+ dock_write_register(0x60, 0x16);
+ dock_write_register(0x61, 0x80);
+
+ /* Activate GPIO */
+ dock_write_register(0x30, 0x01);
+
+ dock_gpio_set_mode(0x00, 3);
+ dock_gpio_set_mode(0x01, 3);
+ dock_gpio_set_mode(0x02, 0);
+ dock_gpio_set_mode(0x03, 3);
+ dock_gpio_set_mode(0x04, 4);
+ dock_gpio_set_mode(0x20, 4);
+ dock_gpio_set_mode(0x21, 4);
+ dock_gpio_set_mode(0x23, 4);
+}
+
+static void connect_dock(void)
+{
+ /* Enable 14.318MHz CLK on CLKIN */
+ dock_write_register(0x29, 0x00);
+ dock_write_register(0x29, 0xa0);
+ dock_gpio_init();
+ /* Assert D_PLTRST# */
+ outb(0xfe, 0x1680);
+ dock_dlpc_init();
+ /* Deassert D_PLTRST# */
+ outb(0xff, 0x1680);
}
static void early_superio_config(void)
@@ -117,53 +184,36 @@
device_t dev;
dev=PNP_DEV(0x2e, 0x00);
+ pnp_write_register(dev, 0x29, 0x06);
- pnp_enter_ext_func_mode(dev);
- pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
- pnp_write_register(dev, 0x02, 0x88); // UART power on
- pnp_write_register(dev, 0x03, 0x72); // Floppy
- pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
- pnp_write_register(dev, 0x14, 0x03); // Floppy
- pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
- pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
- pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
- pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
- pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
- pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
- pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
- /* These are the SMI status registers in the SIO: */
- pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
-
- pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
- pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
- pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
- pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
- pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
- pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
- pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
- pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
- pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
-
- pnp_exit_ext_func_mode(dev);
+ /* Enable COM1 */
+ pnp_write_register(dev, 0x07, 0x03);
+ pnp_write_register(dev, 0x60, 0x03);
+ pnp_write_register(dev, 0x61, 0xf8);
+ pnp_write_register(dev, 0x30, 0x01);
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
- //RCBA32(0x0014) = 0x80000001;
- //RCBA32(0x001c) = 0x03128010;
+ RCBA32(0x0014) = 0x80000001;
+ RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
+ RCBA32(0x3100) = 0x00001230;
+ RCBA32(0x3108) = 0x40004321;
+
+ /* PCIe Interrupts */
+ RCBA32(0x310c) = 0x00004321;
+ /* HD Audio Interrupt */
+ RCBA32(0x3110) = 0x00000002;
/* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
+ RCBA16(0x3140) = 0x1007;
+ RCBA16(0x3142) = 0x0076;
+ RCBA16(0x3144) = 0x3210;
+ RCBA16(0x3146) = 0x7654;
+ RCBA16(0x3148) = 0x0010;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
@@ -172,22 +222,8 @@
RCBA32(0x3400) = (1 << 2);
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
- FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
+ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
-
- /* Enable PCIe Root Port Clock Gate */
- // RCBA32(0x341c) = 0x00000001;
-
- /* This should probably go into the ACPI OS Init trap */
-
- /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
- RCBA32(0x1e84) = 0x00020001;
- RCBA32(0x1e80) = 0x0000fe01;
-
- /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
- RCBA32(0x1e9c) = 0x000200f0;
- RCBA32(0x1e98) = 0x000c0801;
}
static void early_ich7_init(void)
@@ -244,13 +280,6 @@
RCBA32(0x2034) = reg32;
}
-static void init_artec_dongle(void)
-{
- // Enable 4MB decoding
- outb(0xf1, 0x88);
- outb(0xf4, 0x88);
-}
-
#include <cbmem.h>
void main(unsigned long bist)
@@ -267,6 +296,9 @@
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
+
+ connect_dock();
+
early_superio_config();
/* Set up the console */
@@ -293,9 +325,6 @@
*/
i945_early_initialization();
- /* This has to happen after i945_early_initialization() */
- init_artec_dongle();
-
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
@@ -377,4 +406,6 @@
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
}
#endif
+ /* Set legacy Brightness control to full brightness */
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
}
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