[coreboot] coreboot.rom

[Marc Jones]

On Wed, Feb 9, 2011 at 6:35 AM, ali hagigat <hagigatali at gmail.com> wrote:
> How the file coreboot.rom is written on BIOS chip logically? Suppose
> our BIOS chip is 1 mega bytes. We should read first byte from the
> beginning of the file and write it to the address zero of BIOS chip
> and continue this way?
>
> I checked the content of build/coreboot.rom and the last byte was
> 0x0a!! Which is written probably on the top of our EEPROM. Right?
> but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
> SECTIONS {
>        _ROMTOP = 0xfffffff0;
>        . = _ROMTOP;
>        .resetvector . : {
>                *(.reset)
>                . = 15 ;
>                BYTE(0x00);
>        }
> }

x86 systems start executing 0xFFFFFFF0, the reset vector.

http://en.wikipedia.org/wiki/Reset_vector

The first instruction is a far jump down to the stackless init code.

This wiki is for V3, but all the details are there:
http://www.coreboot.org/Coreboot_v3#How_coreboot_starts_after_Reset

Marc



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