[coreboot] [commit] r6340 - in trunk/src: cpu/amd/model_fxx northbridge/amd/amdk8

[repository service]

Author: oxygene
Date: Thu Feb 10 08:51:51 2011
New Revision: 6340
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6340

Log:
Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek at assembler.cz> 
Josef Kellermann <seppk at arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c
   trunk/src/northbridge/amd/amdk8/coherent_ht.c

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Feb 10 08:48:07 2011	(r6339)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Feb 10 08:51:51 2011	(r6340)
@@ -411,33 +411,35 @@
 	msr.hi |= 1 << (43 - 32);
 	wrmsr_amd(BU_CFG_MSR, msr);
 
+	/* Erratum 110 */
+	/* This erratum applies to D0 thru E6 revisions
+	 * Revision F and later are unaffected. There are two fixes
+	 * depending on processor revision.
+	 */
 	if (is_cpu_d0()) {
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
 	}
-#endif
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
 	if (!is_cpu_pre_e0())
-#endif
 	{
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
-	
+#endif
+
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
-		/* I can't touch this msr on early buggy cpus */
+	/* I can't touch this msr on early buggy cpus */
 	if (!is_cpu_pre_b3())
 #endif
 	{
-
-		/* Erratum 89 ... */
 		msr = rdmsr(NB_CFG_MSR);
-		msr.lo |= 1 << 3;
+		
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
 			/* D0 later don't need it */
@@ -448,6 +450,18 @@
 			msr.hi |= 1 << (36 - 32);
 		}
 #endif
+		/* Erratum 89 ... */
+		/* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
+		 * It is correctly labeled as 89 on page 49 of the document
+		 * and in AMD pub#33610
+		 */
+		msr.lo |= 1 << 3;
+		/* Erratum 169 */
+		/* This supersedes erratum 131; 131 should not be applied with 169 
+		 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
+		 */
+		msr.hi |= 1;
+		
 		wrmsr(NB_CFG_MSR, msr);
 	}
 	/* Erratum 122 */
@@ -455,12 +469,6 @@
 	msr.lo |= 1 << 6;
 	wrmsr(HWCR_MSR, msr);
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
-	/* Erratum 131... */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.lo |= 1 << 20;
-	wrmsr(NB_CFG_MSR, msr);
-#endif
 
 }
 

Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Feb 10 08:48:07 2011	(r6339)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Feb 10 08:51:51 2011	(r6340)
@@ -1662,10 +1662,10 @@
 	unsigned node;
 	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1708,6 +1708,20 @@
 			}
 		}
 #endif
+
+		
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+		if (!is_cpu_pre_b3())
+#endif
+		{
+			/* Errata 169 */
+			/* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+			cmd = pci_read_config32(dev, 0x68);
+			cmd &= ~(1 << 22);
+			cmd |= (1 << 21);
+			pci_write_config32(dev, 0x68, cmd);
+		}
 	}
 	return needs_reset;
 }