[coreboot] Patch set updated for coreboot: 166bbb0 Add support for RAM-less multi-processor init
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Dec 6 15:12:01 CET 2011
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454
-gerrit
commit 166bbb0ae0b1b378b1a10b87c586f4bf4c007cfa
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Dec 6 15:53:38 2011 +0200
Add support for RAM-less multi-processor init
For a hyper-threading processor, enabling cache requires that both the
BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
implementation, partial multi-processor initialisation precedes
raminit and AP CPUs' 16bit entry must be run from ROM.
The AP CPU can only start execute real-mode code at a 4kB aligned
address below 1MB. The protected mode entry code for AP is identical
with the BSP code, which is already located at the top of bootblock.
This patch takes the simplest approach and aligns the bootblock
16 bit entry at highest possible 4kB boundary below 1MB.
Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/init/ldscript_failover.lb | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb3..5340c0f 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,18 @@ MEMORY {
TARGET(binary)
SECTIONS
{
- /* Align .rom to next 4 byte boundary so no pad byte appears
- * between _rom and _start.
+ /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+ * with Startup IPI message without RAM.
*/
.bogus ROMLOC_MIN : {
- . = ALIGN(4);
+ . = ALIGN(4096);
ROMLOC = .;
} >rom = 0xff
/* This section might be better named .setup */
.rom ROMLOC : {
_rom = .;
+ ap_sipi_vector = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
@@ -51,7 +52,7 @@ SECTIONS
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
/DISCARD/ : {
*(.comment)
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