[coreboot] ASRock E350M1: enable superio hardware monitor access
perh52 at runbox.com
perh52 at runbox.com
Wed Aug 17 02:40:17 CEST 2011
>Thanks for the patch. Should this be done in romstage per mainboard?
>Maybe add new CONFIG_SB option instead of overloading the SIO config.
>
>Kerry,
>
>Is there already CIMx setup option for this?
>
>
>Thanks,
>Marc
Thanks for your suggestions Marc. I modified the patch so that it fits in
better with existing cimx code. It can now be enabled for each mainboard
by setting CONFIG_SB_SUPERIO_HWM_PORT.
There is currently only one other mainboard in the tree which has an SB800
and a w83627hf family superio: the Advansus a785e-i. Perhaps someone who
has one could test it.
Signed-off-by: Per Hansen <perh52 at runbox.com>
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index e6153c0..2d0e753 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -51,6 +51,11 @@ config AMD_CIMX_SB800
bool
default y
+config SB_SUPERIO_HWM_PORT
+ bool
+ default y
+ depends on SOUTHBRIDGE_AMD_CIMX_SB800
+
config MAINBOARD_DIR
string
default asrock/e350m1
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 93e1c31..899801f 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -118,6 +118,7 @@ typedef union _PCI_ADDR {
#define cimIrConfigDefault 0x00 // Disable
#define cimSpiFastReadEnableDefault 0x01 // Enable
#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
+#define cimSioHwmPortEnableDefault FALSE
// GPP/AB Controller
#define cimNbSbGen2Default TRUE
#define cimAlinkPhyPllPowerDownDefault TRUE
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 0a09e11..efc6fe9 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -48,6 +48,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+ sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS;
sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
@@ -92,6 +93,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+ /* LPC */
+ // SuperIO hardware monitor register access
+ sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM_PORT;
+
/*
* GPP. default configure only enable port0 with 4 lanes,
* configure in devicetree.cb would overwrite the default configuration
diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h
index 6ca4271..5b3ac5c 100644
--- a/src/vendorcode/amd/cimx/sb800/OEM.h
+++ b/src/vendorcode/amd/cimx/sb800/OEM.h
@@ -85,6 +85,14 @@
#endif
/**
+ * SIO_HWM_BASE_ADDRESS - Super IO HWM base address
+ *
+ */
+#ifndef SIO_HWM_BASE_ADDRESS
+ #define SIO_HWM_BASE_ADDRESS 0x290
+#endif
+
+/**
* SPI_BASE_ADDRESS - SPI controller (ROM) base address
*
*/
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
index 33d09d6..517a353 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c
@@ -144,6 +144,7 @@ sbPowerOnInit (
UINT8 cimSataMode;
UINT8 cimSpiFastReadEnable;
UINT8 cimSpiFastReadSpeed;
+ UINT8 cimSioHwmPortEnable;
UINT8 SataPortNum;
cimNbSbGen2 = pConfig->NbSbGen2;
@@ -155,12 +156,14 @@ sbPowerOnInit (
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
}
cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+ cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
#if SB_CIMx_PARAMETER == 0
cimNbSbGen2 = cimNbSbGen2Default;
cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+ cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
#endif
// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
@@ -200,6 +203,12 @@ sbPowerOnInit (
// Set Build option into SB
WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+ if ( cimSioHwmPortEnable ) {
+ // Use Wide IO Port 1 to provide access to the superio HWM registers.
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
+ }
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
@@ -354,4 +363,4 @@ sbPowerOnInit (
// Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
-}
\ No newline at end of file
+}
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index ea3e6f6..9ce4490 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -156,6 +156,10 @@ typedef struct _BUILDPARAM {
* @par
* SIO PME BASE Address
*/
+ unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress
+ * @par
+ * SIO HWM BASE Address
+ */
unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
* @par
* Watch Dog Timer Address
@@ -912,6 +916,8 @@ typedef struct _AMDSBCFG {
/** MiscDummy - Reserved */
unsigned int MiscDummy:2; //31:30
+ unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
+
//DebugOptions //offset 4 bytes (146-149)
/** PcibAutoClkCtrlLow - Debug function Reserved */
unsigned int PcibAutoClkCtrlLow:16;
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