[coreboot] New patch to review: 425e650 AMD CIMx changes to support F14 RevC0 cpus
Frank Vibrans III (frank.vibrans@amd.com)
gerrit at coreboot.org
Thu Aug 4 21:48:02 CEST 2011
Frank Vibrans III (frank.vibrans at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/132
-gerrit
commit 425e6501bb65c1d24e737dbe01c70def9d739872
Author: efdesign98 <efdesign98 at gmail.com>
Date: Thu Aug 4 13:47:18 2011 -0600
AMD CIMx changes to support F14 RevC0 cpus
This change is associated with the AMD Family 14 rev C0
update. It is mostly warning fixes. It encompasses both the
SB800 and SB900 southbridges.
Change-Id: I31ad13bb92509228b89921561c340c95e5136370
Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 3 ++-
src/vendorcode/amd/cimx/sb800/EC.c | 4 ++--
src/vendorcode/amd/cimx/sb800/SATA.c | 4 ++--
src/vendorcode/amd/cimx/sb800/SBTYPE.h | 8 ++++----
src/vendorcode/amd/cimx/sb900/Makefile.inc | 2 ++
5 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
index 83722d8..6c92227 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
+++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
@@ -113,5 +113,6 @@ unsigned int ReadIo32(IN unsigned short Address);
void WriteIo8(IN unsigned short Address, IN unsigned char Data);
void WriteIo16(IN unsigned short Address, IN unsigned short Data);
void WriteIo32(IN unsigned short Address, IN unsigned int Data);
-void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
unsigned char ReadNumberOfCpuCores(void);
diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c
index 633d251..34f82bb 100644
--- a/src/vendorcode/amd/cimx/sb800/EC.c
+++ b/src/vendorcode/amd/cimx/sb800/EC.c
@@ -71,7 +71,7 @@ ecPowerOnInit (
RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
- if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
+ if ( pConfig->BuildParameters.EcKbd == CIMX_ENABLED) {
//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
@@ -83,7 +83,7 @@ ecPowerOnInit (
RWEC8 (0x30, 0x00, 0x01);
}
- if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
+ if ( pConfig->BuildParameters.EcChannel0 == CIMX_ENABLED) {
//Logical device 0x03
RWEC8 (0x07, 0x00, 0x03);
RWEC8 (0x60, 0x00, 0x00);
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 1c0e7e6..1c59d08 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -470,7 +470,7 @@ sataInitAfterPciEnum (
if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
// RIAD or AHCI
- if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+ if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_DISABLED) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@ sataInitLatePost (
//Enable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
-// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_DISABLED) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
// }
sataBar5setting (pConfig, &ddBar5);
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index ea3e6f6..da6c43e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -1093,13 +1093,13 @@ typedef unsigned int CIM_STATUS;
#pragma pack (pop)
/**
- * CIMX_OPTION_DISABLED - Define disable in module
+ * CIMX_DISABLED - Define disable in module
*/
-#define CIMX_OPTION_DISABLED 0
+#define CIMX_DISABLED 0
/**
- * CIMX_OPTION_ENABLED - Define enable in module
+ * CIMX_ENABLED - Define enable in module
*/
-#define CIMX_OPTION_ENABLED 1
+#define CIMX_ENABLED 1
// mov al, code
// out 80h, al
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
index 76b610f..6d79739 100755
--- a/src/vendorcode/amd/cimx/sb900/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc
@@ -20,6 +20,8 @@
# CIMX Root directory
CIMX_ROOT = $(src)/vendorcode/amd/cimx
+#CIMX_INC = -I$(src)/southbridge/amd/cimx/sb900
+#CIMX_INC += -I$(src)/mainboard/$(MAINBOARDDIR)
CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
CIMX_INC += -I$(src)/southbridge/amd/cimx/sb900
CIMX_INC += -I$(CIMX_ROOT)/sb900
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