[coreboot] libpci accesses in CAR, I need a suggestion

[Tadas Slotkus]

Hi, thank you both for the answers. I have studied libpci from
libpayload and removed that device list generation with mallocs. Done a
bunch of trial-error cleanup and now chipset enable and probing for
flash works in ramstage's top of hardwaremain function with this line
included:
	x86_setup_mtrrs(36); //from cpu init routine
see attached log: ramstage_with_mtrr.txt.
Also attaching nonworking logs in romstage and ramstage.

Now the question is how these mtrrs should be set in cache_as_ram.inc or
maybe I'm totally wrong? :)

Thanks,
Tadas
-------------- next part --------------
coreboot-4.0-r6637 Mon Aug  1 21:55:46 EEST 2011 starting...
Loading image.
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 6840 + align -> fffc6880
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r6637 Mon Aug  1 21:55:46 EEST 2011 booting...

Setting fixed MTRRs(0-88) Type: UC
DONE fixed MTRRs
call enable_fixed_mtrr()
Zero-sized MTRR range @0KB
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
flashrom is free software, get the source code at http://www.flashrom.org

Initializing internal programmer
chipset enable :)Found chipset "Intel PIIX4/4E/4M", enabling flash write... chipset PCI ID is 8086:7110, enablef0
enablef1
enablef2
OK.
Probing for Winbond W29C020(C)/W29C022, 256 kB: clocks_per_usec: 402
probe_jedec_common: id1 0xda, id2 0x45
Found chip "Winbond W29C020(C)/W29C022" (256 kB, bustype :) .
-------------- next part --------------
coreboot-4.0-r6637 Mon Aug  1 21:47:20 EEST 2011 starting...
Loading image.
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 6840 + align -> fffc6880
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r6637 Mon Aug  1 21:47:20 EEST 2011 booting...
flashrom is free software, get the source code at http://www.flashrom.org

Initializing internal programmer
chipset enable :)Found chipset "Intel PIIX4/4E/4M", enabling flash write... chipset PCI ID is 8086:7110, enablef0
enablef1
enablef2
OK.
Probing for Winbond W29C020(C)/W29C022, 256 kB: clocks_per_usec: 402
probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
-------------- next part --------------
coreboot-4.0-r6637 Mon Aug  1 21:40:30 EEST 2011 starting...
flashrom is free software, get the source code at http://www.flashrom.org

Initializing internal programmer
chipset enable :)Found chipset "Intel PIIX4/4E/4M", enabling flash write... chipset PCI ID is 8086:7110, enablef0
enablef1
enablef2
OK.
Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Loading image.
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 6840 + align -> fffc6880
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000