[coreboot] Update AMD Persimmon project to support Windows 7, XP, linux

Scott Duplichan scott at notabs.org
Thu Apr 21 21:10:09 CEST 2011

I have a set of AMD persimmon patches for improved OS support.
The changes should easily port to ASRock E350M1 and AMD Inagua.

These operating systems were tested and can install from a DVD and boot from hard disk:
1) Windows 7 with SP1 and latest AMD video driver
2) ubuntu-11.04-beta2-dvd-amd64.iso
3) Windows Server 2003 x64 SP2
4) Windows XP x64 SP2

Live CD test only:
1) linuxmint-9
2) slax 6.12
3) nimblex 2010 beta

Here is a summary of the changes. Change #1 is essential, but it is a work around
and not a true fix. Before submitting the patches, we should decide what to do
about item #1. Here is a past discussion of the problem. While the past problem
occurred only when a PCI video card was added, the current problem happens with
no added cards:

Here is the work around I am testing with. It limits device memory
allocation to the area below MMCONF_BASE. The method works, but
wastes address space:
Index: src/devices/pci_device.c
--- src/devices/pci_device.c  (revision 6483)
+++ src/devices/pci_device.c  (working copy)
@@ -259,6 +259,7 @@
      if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
         /* 32bit limit. */
         resource->limit = 0xffffffffUL;
+        resource->limit = CONFIG_MMCONF_BASE_ADDRESS - 1;
      } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
         /* 1MB limit. */
         resource->limit = 0x000fffffUL;

1) Work around coreboot resource allocation problem that causes
overlap of PCIe MMIO space and graphics MMIO space.
2) Add device allocation for AP cores so that they will be reported and used by OS.
3) Change cimx wrapper code so that OS shutdown function will work.
4) Fix problems that cause incorrect programming and incorrect reporting of I/O APIC ID.
5) Fix code that ignores MMCONF_BUS_NUMBER value and always uses 256.
6) Change coreboot ACPI code to not report RTC as PIIX4 compatible.
7) Add coreboot ACPI code to report PS/2 KB and mouse (ASRock only).
8) Change coreboot ACPI code to report memory range A0000-Bffff as used.
9) Change coreboot ACPI code to report proper FADT revision.
10) Correct MP table reporting of APIC version.
11) Program SB800 MiscCntrl earlier so first serial output is not garbled.
12) Enable cache early to decrease coreboot execution time.
13) Remove some unused HT code. Remove other unneeded code.
14) Change seabios to use DMA instead of PIO for disk reads.


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