[coreboot] [PATCH] add ThinkPad T60

Stefan Reinauer stefan.reinauer at coreboot.org
Mon Apr 18 21:32:15 CEST 2011

* Sven Schnelle <svens at stackframe.org> [110418 10:00]:
> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
> > Can you please put these in a .c or .h file in the mainboard
> > directory? I don't think we should add configuration variables
> > for single registers in Kconfig.
> Actually i've copied that from another Board using the pci1x2x cardbus
> controller, and was quite surprised that these settings are located in
> Kconfig. IMHO they should be configured in devicetree.cb via chip.h config.
> What do you think about this solution? Maybe we should do that in an
> extra patch, which moves those setting to chip config and converts all
> pci1x2x users?
Oh, that sounds like a much better thing to do. 

> >     -       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus   5:00.0 */
> >     -       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire  5:00.1 */
> >     -       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC      5:00.2 */
> >     +       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus   5:00.0 */
> >      
> >             smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
> >             smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
> >
> > In general it would be better to look for the appropriate devices in the system, because someone might plug in a device with a bridge on the
> > lower buses, effectively rendering your mptable useless.
> >
> > MP table automation ftw!
> Hmm, have to look how to do automatic generation of mptable. Thanks
> for the hint.

Well, there is this (unimplemented) idea of adding the IO Apics to the
device tree (ie. let each southbridge create an extra device) and then
create proper mp tables and pirq tables by walking the device tree.

However, as a quick fix you can look at the kontron 986lcd-m. It probes
for certain bridges and fixes up the bus numbers according to their
subordinate buses.

Anyways, with the pci1x2x fix in place, the code is
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Everything else will possibly need another round of thoughts/patches.


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