[coreboot] Super I/O: Winbond LPC Super I/O WPCN381U

Jeremy Moles cubicool at gmail.com
Thu Apr 7 17:34:33 CEST 2011

On Thu, 2011-04-07 at 17:27 +0200, Peter Stuge wrote:
> Peter Stuge wrote:
> > > specifically the PC87381 Super I/O device? Perhaps there's some code
> > > in coreboot demonstrating how GPIO ports are manipulated?
> > 
> > Look at what superiotool does
> To clarify, superiotool has functions internally for writing to
> registers in superios, because they are needed by the program.
> There's just no user interface for writing, and there hasn't been
> much discussion on how it would look.

Okay, thanks. :)

As a further question: as I mentioned in the first post, the information
given to me (which is all we can get under our current NDA) is that to
"power up" this device (unfortunately, the person giving us this
information was certainly not a Linux engineer) we should manipulate the
GPIO03 port.

Aren't these pins that simply accept a single bit (I see the terms
HIGH/LOW used frequently in GPIO documentation). This means I will need
to find whatever register corresponds to GPIO03 and set just that
particular HIGH bit?

(Other keywords in their email were things like "GPIO:0x2" and
GPIO:0x18", but I haven't been able to get any additional clarification
from them...)

At any rate, thanks for your help. Hopefully I can use isaset, and if
not I'll try using regwrite() in superiotool directrly (which just wraps
OUTB anyways)...

> //Peter

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