[coreboot] AMD cache setup is broken
scott at notabs.org
Wed Sep 15 20:51:38 CEST 2010
]From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Marc Jones
]Sent: Wednesday, September 15, 2010 01:32 PM
]To: Scott Duplichan
]Cc: Arne Georg Gleditsch; coreboot at coreboot.org
]Subject: Re: [coreboot] AMD cache setup is broken
]On Mon, Sep 13, 2010 at 9:15 PM, Scott Duplichan <scott at notabs.org> wrote:
]> ]-----Original Message-----
]> ]From: coreboot-bounces+scott=notabs.org at coreboot.org [mailto:coreboot-]]bounces+scott=notabs.org at coreboot.org] On Behalf Of Arne
]> Georg Gleditsch
]> ]Sent: Monday, September 13, 2010 03:51 AM
]> ]To: Scott Duplichan
]> ]Cc: 'Marc Jones'; coreboot at coreboot.org
]> ]Subject: Re: [coreboot] AMD cache setup is broken
]> ]"Scott Duplichan" <scott at notabs.org> writes:
]> ]> I think it would be best to clear bit 35 of msr c001_102a in the AP
]> ]> cores as well as the BSP core. Otherwise, the OS might see AP cores
]> ]> having slightly lower performance than the BSP core. This bit affects
]> ]> family 10h revC and newer (45 nm).
]> ]Ok, so here's a patch adding this. Clearing bit 35 is done
]> ]unconditionally for all fam10 cpus, is that ok? Setting is done based
]> ]on processor type in defaults.h, as before.
]> Thanks. This looks correct to me. I used simnow/tilapia to confirm bit
]> 35 gets cleared in all cores. I found bit 35 never actually gets set.
]> I submitted a patch to correct that. Once that patch is applied, I can
]> see bit 35 gets set in all cores, then gets cleared in all cores.
]Can you Acked-by: if this is working for you.
Thanks Marc. Here you go..
Acked-by: Scott Duplichan <scott at notabs.org>
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