[coreboot] [PATCH] Add support for Asus M4A785-M, with build instructions

Myles Watson mylesgw at gmail.com
Mon Sep 13 22:31:51 CEST 2010

On Mon, Sep 13, 2010 at 1:35 PM, Arne Georg Gleditsch
<arne.gleditsch at numascale.com> wrote:
> Myles Watson <mylesgw at gmail.com> writes:
>> So even though there are PCI resources located at 0xc0000000, RAM gets
>> used for UMA at 0xd0000000 and tables get placed at 0xcfff0000.
> PCI resources at 0xd0000000?  Doesn't this conflict with the setting of
> NV_BottomIO in src/northbridge/amd/amdmct/wrappers/mcti_d.c?

That could be.  I'm totally ignorant of the fam10 code oustside of

Looking at the boot log, it doesn't seem unreasonable to have PCI
resources from starting at 0xc0000000.

It seems like we have a couple of options:
1. Reclaim the area used for MMCONF on this board
2. Move NV_BottomIO

Probably 2 is the best.  It's too bad to have that hard coded.


More information about the coreboot mailing list