[coreboot] AMD cache setup is broken

Arne Georg Gleditsch arne.gleditsch at numascale.com
Mon Sep 6 12:49:41 CEST 2010

Stefan Reinauer <stefan.reinauer at coresystems.de> writes:
>> Can you see if the patches posted in
>> http://article.gmane.org/gmane.linux.bios/57707 make any difference for
>> you?
> Did we ever figure out what is causing this?

The last time I really dug into this, it was fairly obvious that it was
caused by instruction fetch thrashing towards the ROM.  I tried to amend
this with MTRR settings, but I was unable to make that work correctly.
For some reason it seemed like the HT requests were sublty changed when
the MTRR was applied, and didn't hit the legacy southbridge properly.

> The patch would require 4KB more stack on all supported systems, so if
> we can we should do things differently.

It doesn't have to be stack, but it is nice to have it memory mananged
in some way.  The unrv2b patch I posted addressing the same problem was
even more kludgy.

> Also, it's not really guaranteed that the code works from the new
> location since we don't compile coreboot with -fPIC (and as far as I
> understand the GCC guys, even that would not help), so I am a bit
> hesitant to check this in.

Agreed, it is a bit icky.  Not sure what the best way to handle that is,
though.  On the pro side, I assume breakage here is going to be obvious,
and (supposing these patches actually help Nick) this is an issue people
are running into with some regularity.


More information about the coreboot mailing list