[coreboot] [PATCH] [serialice] Add Truxton dev kit mainboard to serialice

[Dustin Harrison]

  On 17/10/2010 11:18 PM, Warren Turkal wrote:
> I am going to take your word that the code works. Have you tested this 
> on real
> hardware?
>
Yes this has been hardware tested, however I am not using a Truxton dev 
kit.  I am using an EP80579 based system, which should be sufficient as 
the code is only CPU dependent.


Repost of patch with fixed comment.

Signed-off-by: Dustin Harrison <dustin.harrison at sutus.com>

Index: Kconfig
===================================================================
--- Kconfig     (revision 107)
+++ Kconfig     (working copy)
@@ -39,6 +39,9 @@
  config BOARD_RODA_RK886EX
         bool "Roda RK886EX"

+config BOARD_INTEL_EP80579
+       bool "Truxton"
+
  config BOARD_INTEL_D945GCLF
         bool "Intel D945GCLF"

@@ -110,6 +113,7 @@
         default "tyan_s2895.c" if BOARD_TYAN_S2895
         default "tyan_s2912.c" if BOARD_TYAN_S2912
         default "hp_dl165_g6.c" if BOARD_HP_DL165_G6
+       default "ep80579.c" if BOARD_INTEL_EP80579
  choice
         prompt "Target communication"

Index: mainboard/ep80579.c
===================================================================
--- mainboard/ep80579.c (revision 0)
+++ mainboard/ep80579.c (revision 0)
@@ -0,0 +1,101 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH (all other code)
+ * Copyright (C) 2008 Arastra, Inc. (i3100 functions)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  
02110-1301 USA
+ */
+
+
+/*
+ * This will initialize an EP80579 (Tolapai) based system
+ * using code copied directly from the coreboot project.
+ */
+
+const char boardname[33]="Truxton Dev Kit                 ";
+
+/* Hardware specific functions */
+
+#define RCBA   0xfed1c000
+#define   GCS  0x3410
+#define RCBA32(x) *((volatile u32 *)(RCBA + x))
+
+#define I3100_SUPERIO_CONFIG_PORT 0x4e
+#define I3100_SP1 0x04
+
+
+static void southbridge_init(void)
+{
+       u16 reg16;
+       u32 reg32;
+
+       // Set up RCBA
+       pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
+
+    /* Enable decoding of I/O locations for SuperIO devices */
+    pci_write_config16(PCI_ADDR(0x0, 0x1f, 0x0, 0x80), 0x0010);
+    pci_write_config16(PCI_ADDR(0x0, 0x1f, 0x0, 0x82), 0x340f);
+
+    /* Enable the SERIRQs (start pulse width is 8 clock cycles) */
+    pci_write_config8(PCI_ADDR(0x0, 0x1f, 0x0, 0x64), 0xD2);
+
+       // Disable watchdog
+#define PMBASE 0x500
+#define TCOBASE (PMBASE + 0x60)
+       pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
+       pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
+       reg16 = inw(TCOBASE + 0x08);
+       reg16 |= (1 << 11);
+       outw(reg16, TCOBASE + 0x08);
+       outw(0x0008, TCOBASE + 0x04);
+       outw(0x0002, TCOBASE + 0x06);
+}
+
+static void i3100_sio_write(u8 port, u8 ldn, u8 index,
+                u8 value)
+{
+    outb(0x07, port);
+    outb(ldn, port + 1);
+    outb(index, port);
+    outb(value, port + 1);
+}
+
+static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
+{
+    /* Enter configuration state */
+    outb(0x80, port);
+    outb(0x86, port);
+
+    /* Enable serial port */
+    i3100_sio_write(port, ldn, 0x30, 0x01);
+
+    /* Set serial port IO region */
+    i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
+    i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
+
+    /* Enable device interrupts, set UART_CLK predivide to 26 */
+    i3100_sio_write(port, 0x00, 0x29, 0x0b);
+
+    /* Exit configuration state */
+    outb(0x68, port);
+    outb(0x08, port);
+}
+
+static void chipset_init(void)
+{
+       southbridge_init();
+       i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, 0x3f8);
+}
+