[coreboot] pci resource allocation overlaps config_mmconf_base_address

Arne Georg Gleditsch arne.gleditsch at numascale.com
Mon Oct 18 21:11:59 CEST 2010

Myles Watson <mylesgw at gmail.com> writes:
> On Mon, Oct 18, 2010 at 6:48 AM, Arne Georg Gleditsch
> <arne.gleditsch at numascale.com> wrote:
>> On a similar note: I'm looking at a southbridge that has its own notion
>> of what constitutes TOP_OF_DRAM.  Apparently, the IOMMU aperture needs
>> to be below this boundary, or DMA transactions towards the aperture are
>> terminated with master abort.  From the CPU's side, though, the IOMMU
>> aperture should be above TOP_OF_MEM, in order to avoid wasting the DRAM
>> behind it, no?  So, as well as being able to allocate posted and
>> non-posted memory resources in separate hunks: in this instance it would
>> be good to be able to allocate the GART aperture in a third hunk that
>> was placed below the other two, so that the SB TOM register could be
>> programmed to include it when needed.
>> Is this feasible, or should I approach this from a different angle?
> It sounds like overkill to include this as a special case for the
> resource allocator.  At first glance, the code would seem to be very
> simple for that register.  Is this a one-time, one-resource problem?
> Are there other hunks that need to be allocated together with it?

I'm not aware of any others, so arranging for a full "resource group"
might be overkill.  But as for very simple, I'm afraid I don't really
see it.  To be clear, I'm talking about the GART aperture that's
allocated in
src/northbridge/amd/amdfam10/misc_control.c:mcf3_read_resources.  What
would be the easy way to make sure this resource is allocated at the
lowest possible address in the IO hole (for this board)?


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