[coreboot] [commit] r5942 - in trunk/src: cpu/amd/car cpu/intel/car cpu/via/car include/cpu/amd
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Tue Oct 12 08:13:41 CEST 2010
Author: wt
Date: Tue Oct 12 08:13:40 2010
New Revision: 5942
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5942
Log:
Reduce duplicate definition in CAR code.
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.
I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.
Signed-off-by: Warren Turkal <wt at penguintechs.org>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified:
trunk/src/cpu/amd/car/cache_as_ram.inc
trunk/src/cpu/intel/car/cache_as_ram.inc
trunk/src/cpu/via/car/cache_as_ram.inc
trunk/src/include/cpu/amd/mtrr.h
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942)
@@ -155,7 +155,7 @@
/* Clear all MTRRs. */
xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
@@ -396,23 +396,48 @@
post_code(0xaf) /* Should never see this POST code. */
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+ /* fixed MTRR MSRs */
+ .long MTRRfix64K_00000_MSR
+ .long MTRRfix16K_80000_MSR
+ .long MTRRfix16K_A0000_MSR
+ .long MTRRfix4K_C0000_MSR
+ .long MTRRfix4K_C8000_MSR
+ .long MTRRfix4K_D0000_MSR
+ .long MTRRfix4K_D8000_MSR
+ .long MTRRfix4K_E0000_MSR
+ .long MTRRfix4K_E8000_MSR
+ .long MTRRfix4K_F0000_MSR
+ .long MTRRfix4K_F8000_MSR
+
+ /* var MTRR MSRs */
+ .long MTRRphysBase_MSR(0)
+ .long MTRRphysMask_MSR(0)
+ .long MTRRphysBase_MSR(1)
+ .long MTRRphysMask_MSR(1)
+ .long MTRRphysBase_MSR(2)
+ .long MTRRphysMask_MSR(2)
+ .long MTRRphysBase_MSR(3)
+ .long MTRRphysMask_MSR(3)
+ .long MTRRphysBase_MSR(4)
+ .long MTRRphysMask_MSR(4)
+ .long MTRRphysBase_MSR(5)
+ .long MTRRphysMask_MSR(5)
+ .long MTRRphysBase_MSR(6)
+ .long MTRRphysMask_MSR(6)
+ .long MTRRphysBase_MSR(7)
+ .long MTRRphysMask_MSR(7)
+
+ /* Variable IORR MTRR MSRs */
+ .long IORRBase_MSR(0)
+ .long IORRMask_MSR(0)
+ .long IORRBase_MSR(1)
+ .long IORRMask_MSR(1)
+
+ /* Top of memory MTRR MSRs */
+ .long TOP_MEM_MSR
+ .long TOP_MEM2_MSR
-var_iorr_msr:
- .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
-
-mem_top:
- .long 0xC001001A, 0xC001001D
.long 0x000 /* NULL, end of table */
cache_as_ram_setup_out:
Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942)
@@ -115,7 +115,7 @@
/* Clear all MTRRs. */
xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
@@ -128,17 +128,38 @@
jmp clear_fixed_var_mtrr
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+ /* fixed MTRR MSRs */
+ .long MTRRfix64K_00000_MSR
+ .long MTRRfix16K_80000_MSR
+ .long MTRRfix16K_A0000_MSR
+ .long MTRRfix4K_C0000_MSR
+ .long MTRRfix4K_C8000_MSR
+ .long MTRRfix4K_D0000_MSR
+ .long MTRRfix4K_D8000_MSR
+ .long MTRRfix4K_E0000_MSR
+ .long MTRRfix4K_E8000_MSR
+ .long MTRRfix4K_F0000_MSR
+ .long MTRRfix4K_F8000_MSR
+
+ /* var MTRR MSRs */
+ .long MTRRphysBase_MSR(0)
+ .long MTRRphysMask_MSR(0)
+ .long MTRRphysBase_MSR(1)
+ .long MTRRphysMask_MSR(1)
+ .long MTRRphysBase_MSR(2)
+ .long MTRRphysMask_MSR(2)
+ .long MTRRphysBase_MSR(3)
+ .long MTRRphysMask_MSR(3)
+ .long MTRRphysBase_MSR(4)
+ .long MTRRphysMask_MSR(4)
+ .long MTRRphysBase_MSR(5)
+ .long MTRRphysMask_MSR(5)
+ .long MTRRphysBase_MSR(6)
+ .long MTRRphysMask_MSR(6)
+ .long MTRRphysBase_MSR(7)
+ .long MTRRphysMask_MSR(7)
+
.long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out:
Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941)
+++ trunk/src/cpu/via/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942)
@@ -47,7 +47,7 @@
/* Clear all MTRRs. */
xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
@@ -60,17 +60,38 @@
jmp clear_fixed_var_mtrr
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+ /* fixed MTRR MSRs */
+ .long MTRRfix64K_00000_MSR
+ .long MTRRfix16K_80000_MSR
+ .long MTRRfix16K_A0000_MSR
+ .long MTRRfix4K_C0000_MSR
+ .long MTRRfix4K_C8000_MSR
+ .long MTRRfix4K_D0000_MSR
+ .long MTRRfix4K_D8000_MSR
+ .long MTRRfix4K_E0000_MSR
+ .long MTRRfix4K_E8000_MSR
+ .long MTRRfix4K_F0000_MSR
+ .long MTRRfix4K_F8000_MSR
+
+ /* var MTRR MSRs */
+ .long MTRRphysBase_MSR(0)
+ .long MTRRphysMask_MSR(0)
+ .long MTRRphysBase_MSR(1)
+ .long MTRRphysMask_MSR(1)
+ .long MTRRphysBase_MSR(2)
+ .long MTRRphysMask_MSR(2)
+ .long MTRRphysBase_MSR(3)
+ .long MTRRphysMask_MSR(3)
+ .long MTRRphysBase_MSR(4)
+ .long MTRRphysMask_MSR(4)
+ .long MTRRphysBase_MSR(5)
+ .long MTRRphysMask_MSR(5)
+ .long MTRRphysBase_MSR(6)
+ .long MTRRphysMask_MSR(6)
+ .long MTRRphysBase_MSR(7)
+ .long MTRRphysMask_MSR(7)
+
.long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out:
Modified: trunk/src/include/cpu/amd/mtrr.h
==============================================================================
--- trunk/src/include/cpu/amd/mtrr.h Tue Oct 12 08:12:00 2010 (r5941)
+++ trunk/src/include/cpu/amd/mtrr.h Tue Oct 12 08:13:40 2010 (r5942)
@@ -21,12 +21,13 @@
#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
-#define IORR0_BASE 0xC0010016
-#define IORR0_MASK 0xC0010017
-#define IORR1_BASE 0xC0010018
-#define IORR1_MASK 0xC0010019
-#define TOP_MEM 0xC001001A
-#define TOP_MEM2 0xC001001D
+#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
+#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
+
+#define TOP_MEM_MSR 0xC001001A
+#define TOP_MEM2_MSR 0xC001001D
+#define TOP_MEM TOP_MEM_MSR
+#define TOP_MEM2 TOP_MEM2_MSR
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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