[coreboot] [commit] r6127 - in trunk/src: mainboard/asus/p2b northbridge/intel/i440bx/acpi southbridge/intel/i82371eb southbridge/intel/i82371eb/acpi

Stefan Reinauer stepan at coreboot.org
Tue Nov 30 23:31:04 CET 2010


* Tobias Diedrich <ranma+coreboot at tdiedrich.de> [101128 11:43]:
> Stefan Reinauer wrote:
> > On 11/27/10 1:40 AM, repository service wrote:
> > > +++ trunk/src/mainboard/asus/p2b/dsdt.asl	Sat Nov 27 10:40:16 2010	(r6127)
> > > @@ -0,0 +1,101 @@
> > ...
> > > +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
> > > +{
> > > +	/* Define the main processor.*/
> > > +	Scope (\_PR)
> > > +	{
> > > +		/* Looks like the P_CNT field can't be a method or name
> > > +		 * and has to be hardcoded to 0xe410 or generated in SSDT */
> > > +		Processor (CPU0, 0x01, 0xe410, 0x06) {}
> > > +	}
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
> 
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10

Oh, I think that's even worse... ;)

1) DEFAULT_PMBASE must be lower than 0x1000 to avoid conflicts with the
   resource allocator.

2) The IO address in the Processor field should be configured
   in the MSR PMG_IO_BASE_ADDR (0xe3).

Stefan





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