[coreboot] [PATCH] ASUS P2B ACPI sleep 1/3 v2
Tobias Diedrich
ranma+coreboot at tdiedrich.de
Tue Nov 30 11:14:17 CET 2010
Add acpi_get_sleep_type() to i82371eb and P2B.
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.
Patch 2/3 and 3/3 follow later.
Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
Index: src/arch/i386/boot/acpi.c
===================================================================
--- src/arch/i386/boot/acpi.c.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/arch/i386/boot/acpi.c 2010-11-30 01:15:39.000000000 +0100
@@ -481,7 +481,8 @@
static int acpi_is_wakeup(void)
{
- return (acpi_slp_type == 3);
+ /* Both resume from S2 and resume from S3 restart at CPU reset */
+ return (acpi_slp_type == 3 || acpi_slp_type == 2);
}
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp)
@@ -567,9 +568,11 @@
return wake_vec;
}
+#if CONFIG_SMP
extern char *lowmem_backup;
extern char *lowmem_backup_ptr;
extern int lowmem_backup_size;
+#endif
#define WAKEUP_BASE 0x600
@@ -588,12 +591,14 @@
return;
}
+#if CONFIG_SMP
// FIXME: This should go into the ACPI backup memory, too. No pork saussages.
/*
* Just restore the SMP trampoline and continue with wakeup on
* assembly level.
*/
memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
+#endif
/* Copy wakeup trampoline in place. */
memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
Index: src/southbridge/intel/i82371eb/Kconfig
===================================================================
--- src/southbridge/intel/i82371eb/Kconfig.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/southbridge/intel/i82371eb/Kconfig 2010-11-30 01:15:39.000000000 +0100
@@ -1,6 +1,7 @@
config SOUTHBRIDGE_INTEL_I82371EB
bool
select TINY_BOOTBLOCK
+ select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-11-30 01:15:39.000000000 +0100
@@ -31,6 +31,11 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
+#if CONFIG_HAVE_ACPI_RESUME == 1
+extern u8 acpi_slp_type;
+int acpi_get_sleep_type(void);
+#endif
+
static void pwrmgt_enable(struct device *dev)
{
struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@@ -87,7 +92,13 @@
outw(0xffff, DEFAULT_PMBASE + GLBSTS);
outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
- /* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ /* this reads PMCNTRL, so we have to call it before writing the
+ * default value */
+ acpi_slp_type = acpi_get_sleep_type();
+#endif
+
+ /* set PMCNTRL default */
outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
}
Index: src/lib/cbmem.c
===================================================================
--- src/lib/cbmem.c.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/lib/cbmem.c 2010-11-30 01:15:39.000000000 +0100
@@ -198,8 +198,10 @@
void cbmem_initialize(void)
{
#if CONFIG_HAVE_ACPI_RESUME
- if (acpi_slp_type == 3) {
+ printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type);
+ if (acpi_slp_type == 3 || acpi_slp_type == 2) {
if (!cbmem_reinit(high_tables_base)) {
+ printk(BIOS_DEBUG, "cbmem_reinit failed\n");
/* Something went wrong, our high memory area got wiped */
acpi_slp_type = 0;
cbmem_init(high_tables_base, high_tables_size);
Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c 2010-11-30 01:15:39.000000000 +0100
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+int acpi_get_sleep_type(void);
+
+/*
+ * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+ *
+ * 0: soft off/suspend to disk S5
+ * 1: suspend to ram S3
+ * 2: powered on suspend, context lost S2
+ * Note: 'context lost' means the CPU restarts at the reset
+ * vector
+ * 3: powered on suspend, CPU context lost S1
+ * Note: Looks like 'CPU context lost' does _not_ mean the
+ * CPU restarts at the reset vector. Most likely only
+ * caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * 4: powered on suspend, context maintained S1
+ * 5: working (clock control) S0
+ * 6: reserved
+ * 7: reserved
+ */
+static const u8 acpi_sus_to_slp_typ[8] = {
+ 5, 3, 2, 1, 1, 0, 0, 0
+};
+
+int acpi_get_sleep_type(void)
+{
+ u16 reg, result;
+
+ reg = inw(DEFAULT_PMBASE + PMCNTRL);
+ result = acpi_sus_to_slp_typ[(reg >> 10) & 7];
+
+ printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg);
+
+ return result;
+}
Index: src/southbridge/intel/i82371eb/Makefile.inc
===================================================================
--- src/southbridge/intel/i82371eb/Makefile.inc.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/southbridge/intel/i82371eb/Makefile.inc 2010-11-30 01:15:44.000000000 +0100
@@ -26,6 +26,7 @@
driver-y += i82371eb_reset.c
driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
+driver-$(CONFIG_HAVE_ACPI_RESUME) += i82371eb_wakeup.c
romstage-y += i82371eb_early_pm.c
romstage-y += i82371eb_early_smbus.c
Index: src/mainboard/asus/p2b/dsdt.asl
===================================================================
--- src/mainboard/asus/p2b/dsdt.asl.orig 2010-11-30 01:15:37.000000000 +0100
+++ src/mainboard/asus/p2b/dsdt.asl 2010-11-30 01:15:39.000000000 +0100
@@ -30,27 +30,51 @@
Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {}
}
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
-
- /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
/*
- 000b / 0x0: soft off/suspend to disk (soff/std) s5
- 001b / 0x1: suspend to ram (str) s3
- 010b / 0x2: powered on suspend, context lost (poscl) s1
- 011b / 0x3: powered on suspend, cpu context lost (posccl) s2
- 100b / 0x4: powered on suspend, context maintained (pos) s4
- 101b / 0x5: working (clock control) s0
- 110b / 0x6: reserved
- 111b / 0x7: reserved
- */
+ * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+ *
+ * 0: soft off/suspend to disk S5
+ * 1: suspend to ram S3
+ * 2: powered on suspend, context lost S2
+ * Note: 'context lost' means the CPU restarts at the reset
+ * vector
+ * 3: powered on suspend, CPU context lost S1
+ * Note: Looks like 'CPU context lost' does _not_ mean the
+ * CPU restarts at the reset vector. Most likely only
+ * caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * 4: powered on suspend, context maintained S1
+ * 5: working (clock control) S0
+ * 6: reserved
+ * 7: reserved
+ */
Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
+ OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
+ Field (SIO1, ByteAcc, NoLock, Preserve)
+ {
+ FANP, 1, /* CPU/case fan power */
+ Offset (0x01),
+ PLED, 1,
+ }
+
+ Method (\_PTS, 1, NotSerialized)
+ {
+ /* Disable fan, blink power led */
+ Store (Zero, FANP)
+ Store (Zero, PLED)
+ }
+
+ Method (\_WAK, 1, NotSerialized)
+ {
+ /* Re-enable fan, stop power led blinking */
+ Store (One, FANP)
+ Store (One, PLED)
+ /* wake OK */
+ Return(Package(0x02){0x00, 0x00})
+ }
+
/* Root of the bus hierarchy */
Scope (\_SB)
{
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