[coreboot] [commit] r6058 - in trunk/src: mainboard/intel/eagleheights mainboard/intel/mtarvon mainboard/intel/truxton superio/intel/i3100
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Wed Nov 10 19:22:12 CET 2010
Author: uwe
Date: Wed Nov 10 19:22:11 2010
New Revision: 6058
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6058
Log:
Restructure i3100 Super I/O driver to match the rest of the codebase.
- i3100_early_serial.c:
- Split out enter/exit functions as the other Super I/Os do.
- Make i3100_enable_serial() take a device_t as usual, and convert
it to use the standard pnp_* function instead of open-coding
the same functionality by hand.
- Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
we do the same in various other Super I/Os, e.g. ITE ones.
- Add some #defines for register / bit values and some comments.
- Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
marked as "READ ONLY, WRITES IGNORED" in the datasheet.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>
Modified:
trunk/src/mainboard/intel/eagleheights/romstage.c
trunk/src/mainboard/intel/mtarvon/romstage.c
trunk/src/mainboard/intel/truxton/romstage.c
trunk/src/superio/intel/i3100/i3100.h
trunk/src/superio/intel/i3100/i3100_early_serial.c
Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c Wed Nov 10 15:53:36 2010 (r6057)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c Wed Nov 10 19:22:11 2010 (r6058)
@@ -91,6 +91,8 @@
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
static void early_config(void)
{
u32 gcs, rpc, fd;
@@ -157,7 +159,9 @@
/* Setup the console */
i3100_enable_superio();
- i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+ i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
uart_init();
console_init();
Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c Wed Nov 10 15:53:36 2010 (r6057)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c Wed Nov 10 19:22:11 2010 (r6058)
@@ -40,6 +40,8 @@
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
static inline int spd_read_byte(u16 device, u8 address)
{
return smbus_read_byte(device, address);
@@ -75,9 +77,12 @@
}
#endif
}
+
/* Set up the console */
i3100_enable_superio();
- i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
+ i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
uart_init();
console_init();
Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c Wed Nov 10 15:53:36 2010 (r6057)
+++ trunk/src/mainboard/intel/truxton/romstage.c Wed Nov 10 19:22:11 2010 (r6058)
@@ -15,7 +15,6 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
*/
#include <stdint.h>
@@ -54,6 +53,8 @@
/* #define TRUXTON_DEBUG */
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
static void main(unsigned long bist)
{
msr_t msr;
@@ -76,7 +77,9 @@
/* Set up the console */
i3100_enable_superio();
- i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE);
+ i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
uart_init();
console_init();
Modified: trunk/src/superio/intel/i3100/i3100.h
==============================================================================
--- trunk/src/superio/intel/i3100/i3100.h Wed Nov 10 15:53:36 2010 (r6057)
+++ trunk/src/superio/intel/i3100/i3100.h Wed Nov 10 19:22:11 2010 (r6058)
@@ -46,6 +46,19 @@
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */
-#define I3100_SUPERIO_CONFIG_PORT 0x4e
+/* Registers and bit definitions: */
+
+#define I3100_SIW_CONFIGURATION 0x29
+
+/*
+ * SIW_CONFIGURATION[3:2] = UART_CLK predivide
+ * 00: divide by 1
+ * 01: divide by 8
+ * 10: divide by 26
+ * 11: reserved
+ */
+#define I3100_UART_CLK_PREDIVIDE_1 0x00
+#define I3100_UART_CLK_PREDIVIDE_8 0x01
+#define I3100_UART_CLK_PREDIVIDE_26 0x02
#endif
Modified: trunk/src/superio/intel/i3100/i3100_early_serial.c
==============================================================================
--- trunk/src/superio/intel/i3100/i3100_early_serial.c Wed Nov 10 15:53:36 2010 (r6057)
+++ trunk/src/superio/intel/i3100/i3100_early_serial.c Wed Nov 10 19:22:11 2010 (r6058)
@@ -21,31 +21,36 @@
#include <arch/romcc_io.h>
#include "i3100.h"
-static void i3100_sio_write(u8 port, u8 ldn, u8 index, u8 value)
+static void pnp_enter_ext_func_mode(device_t dev)
{
- outb(0x07, port);
- outb(ldn, port + 1);
- outb(index, port);
- outb(value, port + 1);
-}
+ u16 port = dev >> 8;
-static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
-{
- /* Enter configuration state. */
outb(0x80, port);
outb(0x86, port);
+}
- /* Enable serial port. */
- i3100_sio_write(port, ldn, 0x30, 0x01);
-
- /* Set serial port I/O region. */
- i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
- i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
-
- /* Enable device interrupts, set UART_CLK predivide to 26. */
- i3100_sio_write(port, 0x00, 0x29, 0x0b);
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
- /* Exit configuration state. */
outb(0x68, port);
outb(0x08, port);
}
+
+/* Enable device interrupts, set UART_CLK predivide. */
+static void i3100_configure_uart_clk(device_t dev, u8 predivide)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void i3100_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
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