[coreboot] Question about smm handler bin

[Scott Duplichan]

  _____  

From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of fengwei zhang
Sent: Wednesday, November 10, 2010 11:30 AM
To: coreboot at coreboot.org
Subject: [coreboot] Question about smm handler bin

 

Hi all,

I am trying to impelement SMM support for K8/vt8237r, but I am strarking on build smm handler bin. I understand I need to copy real
smm handler to location 0xa0000. From the ICH4 example, there are two extern varaibles binary_smm_start and binary_smm_end, I know
it defines in /build/cpu/x86/smm/smm_wrap.ramstage.o. but how does that work? 

Suppose I just want to put RSM instruction in the smmhandler, can I just write instruction "0f aa"(bianry code of RSM) to location
0xa0000 and 0xa0001. I tried this, but my machine went freeze after I invoke SMI. 

I am thinking I may need to more instructons, because the SMM start with 16 bits real mode, it may not recongnize the instruction,
right?
But I am starking on how to build and copy SMM handler. 

I would really appreciate if some one could help me this out. 

Best,
Fengwei

 

 

Hello Fengwei,

 

I think the first instruction executed in your case will be at address A8000. The AMD BKDG states:

 

MSRC001_0111[SMM_BASE] + 8000h: SMI handler entry point.

 

As Rudolf said, you need to copy the code into the SMM code space, not the legacy video frame buffer space that occupies the same
address range. The BKDG explains how to do this.

 

Thanks,

Scott

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