[coreboot] [patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Carl-Daniel Hailfinger]

On 08.11.2010 00:31, Tobias Diedrich wrote:
> When coreboot reserves the full decode range (so it can't be
> expanded any further) it should be fine though.
>   

So far I have not seen flash decode ranges larger than 16 MB on any x86
chipset. Reserving less than 16 MB is very dangerous on all Intel/AMD
chipsets released in the last 6+ years because flashrom may maximize the
decode area to 16 MB after the machine has booted.

Regards,
Carl-Daniel

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