[coreboot] PCI IO Address space over 0xffff

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri May 21 23:04:26 CEST 2010

Hi Joe,

On 21.05.2010 22:07, Joe Korty wrote:
> On Fri, May 21, 2010 at 12:10:51PM -0400, Myles Watson wrote:
>> On Fri, May 14, 2010 at 1:49 PM, Joe Korty <joe.korty at ccur.com> wrote:
>>> Unfortunately we have an even bigger PCI-e loaded expansion
>>> chassis (configuration #2), for which coreboot also hangs.
>>> It's not an out-of-memory hang; it happens (apparently)
>>> during the bus walk. ?I haven't looked into this hang in
>>> detail yet, so I don't have much to report. ?But I do fear
>>> it may be something more fundamental.
>> If you send the log to the list we might be able to help.
> I've solved this one, kind of.  It is PCI IO Space
> overflow, we are going over 0xffff which apparently is
> a hard limit.  I image this is there so that inb, outw,
> etc instructions can be used to reference these devices.
> But if one doesn't use such instructions (instead using
> memory mapped PCI IO space), I see no reason why Linux
> and coreboot couldn't work with PCI IO Space addresses
>> 0xffff.

I'm interested in how you want to map port IO space to memory.
Please explain.

AFAIK PCI register space is totally independent of port IO space which
is totally independent of memory space. You can access PCI register
space via CF8/CFC port IO and via MMCONFIG memory, but I'm unaware of
any mechanisms to map IO ports to memory or the other way round.



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