[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

Keith Hui buurin at gmail.com
Tue May 18 17:42:18 CEST 2010

ping... Is this too much? :-)

On Thu, May 13, 2010 at 10:03 PM, Keith Hui <buurin at gmail.com> wrote:
> Hi all,
> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
> related changes (below), so it is gzipped. I may have committed a few
> "crimes" here, but anyway...

> This patch:
> 1. Brings back L2 initialization from coreboot v1 for family 63x,65x
> and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> entire 128k of L2 is still enabled.
> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> serves model 65x because they share too much code. Also included are
> Intel microcode for all CPUs in these families. There's just one file
> for all microcodes in one family.
> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> 63x/67x/6bx only when the proper config has been selected in Kconfig.
> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> been selected.
> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> Once we're sure nothing really are using it, then remove them.
> Bootlog with a PIII 600MHz can be found here:
> http://coreboot.pastebin.com/PNUzJXZT

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