[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done
post-raminit so it's not available for CAR. Your CPU only has 16k of
L1 cache available for CAR.

HTH
Keith

On Fri, May 14, 2010 at 12:51 PM, Idwer Vollering <vidwer at gmail.com> wrote:
> 2010/5/14 Keith Hui <buurin at gmail.com>
>
>> BTW enable CAR and try again.
>
> Like this (note that it doesn't boot my asus p2b, rev 1.04):
>
>  svn diff src/mainboard/asus/p2b/Kconfig
> Index: src/mainboard/asus/p2b/Kconfig
> ===================================================================
> --- src/mainboard/asus/p2b/Kconfig      (revision 5543)
> +++ src/mainboard/asus/p2b/Kconfig      (working copy)
> @@ -25,7 +25,9 @@
>         select NORTHBRIDGE_INTEL_I440BX
>         select SOUTHBRIDGE_INTEL_I82371EB
>         select SUPERIO_WINBOND_W83977TF
> -       select ROMCC
> +#      select ROMCC
> +       select USE_PRINTK_IN_CAR
> +       select CONFIG_USE_DCACHE_RAM
>         select HAVE_PIRQ_TABLE
>         select UDELAY_TSC
>         select BOARD_ROMSIZE_KB_256
> @@ -50,3 +52,13 @@
>         default 6
>         depends on BOARD_ASUS_P2B
>
> +config DCACHE_RAM_BASE
> +       hex
> +       default 0xffdf8000
> +       depends on BOARD_ASUS_P2B
> +
> +config DCACHE_RAM_SIZE
> +       hex
> +       default 0x8000
> +       depends on BOARD_ASUS_P2B
> +
>
>